DRM 85-C, DRM 85
8/41
09/2007
This circuit operates in two modes, burst and fixed frequency, selected by
controlling Pin2 by the processor (0=Fixed frequency, 1=Burst Mode). Fixed
frequency mode operation is used when the DRM is switched into the active
state, burst mode when it is switched off into the standby state to maximize
battery life.
When switched off the device the control signal from the processor is low, so it has
to be inverted via Q604 to high for the burst mode of U600.
Notice that this voltage EVER_3.3 V is constantly available, even when the unit is
turned off.
If the battery vUbatt reaches the threshold of low battery, the backlight,
the Rec. LED and also the Batt. Symbol on LCD flashes. A next threshold downwards
triggers a shutdown of the device.
Exact values for all thresholds are defined in the software documentation. DRM 85
has about 7 hours life time, measured with VARTA blue batteries and also with
Panasonic Accu 2000 mAh.
The converting to 1.8 V is done by U601, L602 and C619 to run in the PWM pulse
skipping mode with mode Pin 6 set to V
in
.
The connector board also hosts an additional power source for the system by way
of the USB connector, which becomes energized with 5 V whenever a connection to
a PC is made. U201 on the connector board converts the inbound 5 V to the system
EVER_3.3 V rail.
3.3.2 CPU and memory section
The code memory can be programmed with the operating system software using
the Background Debug Mode (BDM) development tools from Windriver via the
BDM port J500.
The code memory is also protected from inadvertent erasure or programming by
way of a control signal FWP, which is pulled to O V. When it is desired to program
or erase the code flash, the FWP signal must be pulled to 3.3 V (High or H state)
which is achieved by software control of CPU port pin GP033.
The unit is turned on by the user operating S500. S500 is a rotary multifunction
control switch.
When S500 is pushed, the signal PUSH_SEL goes to O V causing Q602, the main
power control FET, to turn-on producing the system 3.3 V rail. After booting, control
signal PWR_CTL from the CPU changes to High state, taking over control of the
power control FET by way of a second FET Q603. From this point the user may
release switch S500 and the power remains on. When the main 3.3 V rail is present,
a second switching supply U601 produces the second system rail 1.8 V for the CPU
core. As the system 3.3 V rail becomes stable, reset controller U502 unblocks the
system reset signal RST*. When the reset signal RST* is in H-state the CPU will begin
the boot process fetching instructions from the boot memory U400. U400 is a
sixteen bit width flash memory type Atmel AT49BV160C/ ST M28W160ECB70ZB6E
which provides 1 MWord (x16) of code storage space. The code contained within
U400 runs the entire system. This code can be relocated to run from the CPU´s
internal RAM for higher speed operation if desired.
