LEVY
LEVY User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.O. - Reviewed by N.P. - Copyright © 2022 SECO S.p.A.
39
For EMI/ESD protection, common mode chokes on USB data lines, and clamping diodes on USB data and voltage lines, are also needed. Switch with settable
current limit on power lines are recommended.
3.2.2.11
PCI Express interface signals
The module can offer one PCI Express x1 lanes, which is directly managed by i.MX 8M Plus processor (PCI express Gen 3.0 is supported).
Here following the signals involved in PCI express management
PC/ PCIE_A_RX-: PCI Express lane #0, Transmitting Output Differential pair
PC/PCIE_A_TX-: PCI Express lane #0, Receiving Input Differential pair
PCIE_/ PCIE_A_REFCK-: PCI Express Reference Clock for lane #0, Differential Pair
PCIE_A_RST#: Reset Signal that is sent from SMARC Module to a PCI-e device available on the carrier board. Active Low, +3.3V_RUN electrical level.
PCIE_A_CKREQ#: PCIe Port A clock request, can be used for power saving mode on PCIe. Active low, driven by open drain circuitry on the carrier board.
PCIE_WAKE#: PCIe wake up interrupt to host input signal. Active low, +3.3V_ALW electrical level.
