LEVY
LEVY User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.O. - Reviewed by N.P. - Copyright © 2022 SECO S.p.A.
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/LVDS1_2-: LVDS Channel #1 differential data pair #2
/ LVDS1_3-: LVDS Channel #1 differential data pair #3
L/ LVDS1_CK-: LVDS Channel #1 differential Clock
Please refer to the following schematics as an example of connection of dual channel LVDS interface on the carrier board, with EMI filtering section included.
3.2.2.3
Secondary Display (HDMI interface) signals
The NXP i.MX 8M processor has an HD Display Transmitter Controller (HDMI TX), which provides a HDMI interface with resolution limited by the NXP SoC up to
3840x2160 @ 30Hz.
The signals are:
/HDMI_D0-: HDMI Output Differential Pair #0
