LEVY
LEVY User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.O. - Reviewed by N.P. - Copyright © 2022 SECO S.p.A.
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/HDMI_D1-: HDMI Output Differential Pair #1
/HDMI_D2-: HDMI Output Differential Pair #2
/HDMI_CK-: HDMI Differential Clock
HDMI_HPD: Hot Plug Detect Input signal. +1.8V_RUN electrical level signal
-up resistor
HDMI_CTRL_DAT: DDC Data line for HDMI pa
-up resistor
Since HDMI Tx module is embedded in the i.MX 8M processors it is not necessary to implement voltage level shifter for TMDS differential pairs on the Carrier board.
It is still necessary, however, to implement voltage level shifters on Control data/Clock signals, as well as for Hot Plug Detect signal.
3.2.2.4
Serial Cameras
There are two MIPI-CSI2 interfaces available. The CSI0 interface supports two lanes, the CSI1 interface supports 4 lanes with limited bandwidth. Consider that from
the SoC the CSI0 interface is managed by the MIPI_CSI1 group signals and I2C2 bus, while CSI1 is managed by MIPI_CSI2 group signals and I2C3 bus.
/CSI0_CK-: 2-lane CSI Input Clock Differential Pair
C/CSI0_RX0-: 2-lane CSI Input Differential Pair 0
C/CSI0_RX1-: 2-lane CSI Input Differential Pair 1
/CSI1_CK-: 4-lane CSI Input Clock Differential Pair
C/CSI1_RX0- 4-lane CSI Input Differential Pair 0
C/CSI1_RX1-: 4-lane CSI Input Differential Pair 1
C/CSI1_RX2-: 4-lane CSI Input Differential Pair 2
C/CSI1_RX3-: 4-lane CSI Input Differential Pair 3
CAM_MCK: Master clock Output for CSI Port #0 and/or #1 support, electrical level 1.8V_RUN
I2C_CAM0_CK: CSI Port #0 dedicated I2C Bus Clock signal, Bi-Directional, electrical level +1.8V_RUN with a 2k2
Ω
pull-up resistor.
I2C_CAM0_DAT: CSI Port #0 dedicated I2C Bus Data signal, Bi-Directional, electrical level +1.8V_RUN with a 2k2
Ω
pull-up resistor.
On this bus a selection of addresses must be left reserved for on-board peripherals as presented in this table (also consider that this bus is shared with LCD signals
from par. 3.2.2.1):
I2C2 Bus
Address
Peripheral
0x2D
DSI Bridge
