Seco Smarc LEVY User Manual Download Page 1

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LEVY

SMARC Rel. 2.1.1 compliant module with

NXP i.MX 8M Plus Applications Processors

Summary of Contents for Smarc LEVY

Page 1: ...LEVY SMARC Rel 2 1 1 compliant module with NXP i MX 8M Plus Applications Processors...

Page 2: ...A accepts no responsibility for any inaccuracies errors or omissions herein SECO S p A reserves the right to change precise specifications without prior notice to supply the best product possible For...

Page 3: ...mpliance 7 1 7 Safety Policy 8 1 8 Terminology and definitions 9 1 9 Reference specifications 11 OVERVIEW 12 2 1 Introduction 13 2 2 Technical Specifications 14 2 3 Electrical Specifications 15 2 3 1...

Page 4: ...ion 1 0 Last Edition 1 0 Author S O Reviewed by N P Copyright 2022 SECO S p A 4 Warranty Information and assistance RMA number request Safety Electrostatic Discharges RoHS compliance Terminology and d...

Page 5: ...The RMA authorisation number must be put both on the packaging and on the documents shipped with the items which must include all the accessories in their original packaging with no signs of damage t...

Page 6: ...r it is possible to send the faulty product to the SECO Repair Centre In this case follow this procedure o Returned items must be accompanied by a RMA Number Items sent without the RMA number will be...

Page 7: ...nts and is manufactured on a lead free production line It is therefore fully RoHS compliant Always switch the power off unplug the power supply unit and wait until the unit has cooled down before hand...

Page 8: ...the mechanical characteristics indicated in par 2 4 The manufacturer which includes a LEVY module in his end user product shall Install the device inside an enclosure compliant with all applicable IE...

Page 9: ...t HDMI High Definition Multimedia Interface a digital audio and video interface I2C Bus Inter Integrated Circuit Bus a simple serial bus consisting only of data and clock line with multi master capabi...

Page 10: ...ace to drive different Input Output devices like cameras GPS Tuners and so on SM Bus System Management Bus a subset of the I2C bus dedicated to communication with devices for system management like a...

Page 11: ...sheets BreakoutBoards I2SBUS pdf LVDS http www ti com ww en analog interface lvds shtml and http www ti com lit ml snla187 snla187 pdf MIPI http www mipi org MMC eMMC http www jedec org committees jc...

Page 12: ...v First Edition 1 0 Last Edition 1 0 Author S O Reviewed by N P Copyright 2022 SECO S p A 12 Introduction Technical Specifications Electrical Specifications Mechanical Specifications Supported Operati...

Page 13: ...nd real time response The module offers a very high level of integration both for all most common used peripherals in the ARM domain and for bus interfaces typically used in the x86 domain like PCI Ex...

Page 14: ...4 bit SDIO 3 0 interface PCI Express Up to 1 x PCI e x1 Gen3 port Networking 2 x Gigabit Ethernet interface Optional WiFi 802 11a b g n ac BT 5 1 module onboard USB 1 x USB 2 0 Host or 1 x USB 2 0 Cl...

Page 15: ...is strongly dependent on the board s configuration on number of processor cores active and from the interfaces that are SW enabled 2 3 2 Power Rails meanings In all the tables contained in this manual...

Page 16: ...sider that according to SMARC specifications components placed on bottom side of the module will have a maximum height of 1 3mm Keep this value in mind when choosing the MXM connector s height if ther...

Page 17: ...lus Application processor DSI to eDP Bridge LPDDR4 Memory Power section VDD_RTC eDP 1x USB 2 0 Host Client Boot Select Signals Watchdog Power Mgmt VDD_IN Embedded Controller 2x USB 2 0 USB 3 0 Hub 2x...

Page 19: ...2022 SECO S p A 19 3 1 Introduction According to SMARC specifications all interfaces to the board are available through a single card edge connector TOP SIDE Card edge golden finger pin P1 Card edge g...

Page 20: ...onnectors description 3 2 1 WiFi BTLE Module This SMARC module can be equipped by factory option with a Dual band 2 4GHz 5 0 GHz WLAN 802 11 a b g n ac BT 5 0 combo embedded module AzureWave p n AW CM...

Page 21: ...be left unused otherwise the module may not boot or function properly For accurate signals description please consult the following paragraphs SMARC Golden Finger Connector CN2 TOP SIDE BOTTOM SIDE SI...

Page 22: ...P28 S29 N C GBE I O GBE0_MDI0 P29 S30 N C GBE I O GBE0_MDI0 P30 S31 GBE1_LINK_ACT O GBE SPI_INTERFACE O SPI0_CS1 P31 S32 N C GND P32 S33 N C SDIO_CARD I SDIO_WP P33 S34 GND SDIO_CARD I O SDIO_CMD P34...

Page 23: ...S58 N C SPI_INTERFACE I O QSPI_IO_0 P58 S59 N C GND P59 S60 N C USB I O USB0 P60 S61 GND USB I O USB0 P61 S62 USB3_SSTX O USB USB I O USB0_EN_OC P62 S63 USB3_SSTX O USB USB I USB0_VBUS_DET P63 S64 GN...

Page 24: ...0 S91 N C GND P91 S92 GND SECONDARY_DISPLAY O HDMI_D2 P92 S93 N C SECONDARY_DISPLAY O HDMI_D2 P93 S94 N C GND P94 S95 N C SECONDARY_DISPLAY O HDMI_D1 P95 S96 N C SECONDARY_DISPLAY O HDMI_D1 P96 S97 N...

Page 25: ...PM_CK P121 S122 LCD1_BKLT_PWM O LCD_SUPPORT MANAGEMENT I O I2C_PM_DAT P122 S123 GPIO13 I O GPIO BOOT_SEL I BOOT_SEL0 P123 S124 GND BOOT_SEL I BOOT_SEL1 P124 S125 LVDS0_0 eDP0_TX0 O PRIMARY_DISPLAY BOO...

Page 26: ...CAN0_TX P143 S144 eDP0_HPD I PRIMARY_DISPLAY CAN I CAN0_RX P144 S145 WDT_TIME_OUT O WATCHDOG CAN O CAN1_TX P145 S146 PCIE_WAKE I PCI_e CAN I CAN1_RX P146 S147 VDD_RTC VDD_IN P147 S148 LID I MANAGEMEN...

Page 27: ...oC I2C2 bus I2C_LCD_DAT LCD I2C Data This signal is used to read the LCD display EDID EEPROM 1 8V_RUN electrical level Bidirectional with a 2k2 pull up resistor I2C_LCD_CLK LCD I2C Clock This signal i...

Page 28: ...LVDS factory alternatives A dual channel LVDS interface is natively supported by the SOC with a maximum supported resolution of 1920x1200 60Hz while an eDP interface can be selected as a factory alte...

Page 29: ...P0_TX3 eDP0_TX3 eDP Channel 0 differential data pair 3 eDP0_AUX eDP0_AUX eDP Channel 0 differential Clock eDP0_HPD Hot Plug Detect Active high Input signal of 1 8V_RUN electrical level from carrier bo...

Page 30: ...1 differential Clock Please refer to the following schematics as an example of connection of dual channel LVDS interface on the carrier board with EMI filtering section included 3 2 2 3 Secondary Dis...

Page 31: ...y the MIPI_CSI1 group signals and I2C2 bus while CSI1 is managed by MIPI_CSI2 group signals and I2C3 bus CSI0_CK CSI0_CK 2 lane CSI Input Clock Differential Pair CSI0_RX0 CSI0_RX0 2 lane CSI Input Dif...

Page 32: ...dule The SDIO2 interface of the processor is externally accessible through the edge connector of the module Supporting 4 bit mode as per the SMARC specification The uSDHC controller complies with SD H...

Page 33: ...ght 2022 SECO S p A 33 SDIO_ D0 D3 SDIO data bus Signals for 4 bit SD SDIO MMC communication mode Please refer to the following schematics as an example of connection of SDIO interface on the carrier...

Page 34: ...PI slave output MISO SPI interface can support speed up to 20MHz 3 2 2 7 Audio interface signals Here are following the signals related to I2S Audio interfaces The first I2S interface managed by the S...

Page 35: ...8V_ALW with 2 2 up resistor I2C_PM_DAT Power management data signal Bi Directional between the module to the Carrier board electrical level 1 8V_ALW with 2 2 up resistor On this bus a selection of add...

Page 36: ...rical level SER2_CTS UART 3 Interface Handshake signal Clear to Send Input line 1 8V_RUN electrical level with a 100k pull up resistor SER3_RX UART 1 Interface Serial data Receive input line 1 8V_RUN...

Page 37: ...st Edition 1 0 Author S O Reviewed by N P Copyright 2022 SECO S p A 37 In the following schematic here is an example of UART interface on the carrier board with a multiprotocol transceiver allowing to...

Page 38: ...COV low Please take note that the OTG functionality on this port is not supported at runtime USB0 must be set to work as Client or Host at kernel compile time USB1 USB1 Universal Serial Bus Port 2 0 1...

Page 39: ...ted Here following the signals involved in PCI express management PCIE_A_RX PCIE_A_RX PCI Express lane 0 Transmitting Output Differential pair PCIE_A_TX PCIE_A_TX PCI Express lane 0 Receiving Input Di...

Page 40: ...ctional signal 3 3V_ALW electrical level Here following the signals involved in Gigabit Ethernet 1 management GBE1_MDI0 GBE1_MDI0 Media Dependent Interface MDI Transmit Receive differential pair GBE1_...

Page 41: ...ctrical voltage level signal with a 2k2 pull up resistor CAN0_RX CAN Receive Input for CAN Bus Channel 0 1 8V_RUN electrical voltage level signal with a 2k2 pull up resistor CAN1_TX CAN Transmit Outpu...

Page 42: ...ical level 3 2 2 16 Management pins According to the SMARC specifications the input pins listed below are all Active Low meant to be driven by open drain devices on the carrier board VIN_PWR_BAD Power...

Page 43: ...signals are active low and driven by open drain circuitry on the carrier board BOOT_SEL0 Boot Device Selection 0 Input 1 8V_ALW electrical level with a 10k pull up resistor BOOT_SEL1 Boot Device Selec...

Page 45: ...BOTTOM SIDE SoC signal SoC pad Pin name Pin nr Pin nr Pin name SoC pad SoC signal S1 I2C_CAM1_CK AJ7 I2C3_SCL P1 S2 I2C_CAM1_DAT AJ6 I2C3_SDA P2 S3 MIPI_CSI2_CLK_P A23I CSI1_CK P3 S4 MIPI_CSI2_CLK_N B...

Page 46: ...SD2_CD_B AD29 SDIO_CD P35 S36 SD2_CLK AB29 SDIO_CK P36 S37 SD2_RESET_B AD28 SDIO_PWR_EN P37 S38 AUDIO_MCK AJ15 SAI2_MCLK P38 S39 I2S0_LRCK AJ17 SAI2_TXFS SD2_DATA0 AC28 SDIO_D0 P39 S40 I2S0_SDOUT AH1...

Page 47: ...S0 P54 S55 P55 S56 QSPI_IO_2 L24 NAND_DATA02 NAND_ALE N25 QSPI_CK P56 S57 QSPI_IO_3 N24 NAND_DATA03 NAND_DATA01 L25 QSPI_IO_1 P57 S58 NAND_DATA00 R25 QSPI_IO_0 P58 S59 P59 S60 USB1_D_P D10 USB0 P60 S6...

Page 48: ..._TX P89 S90 PCIE_TXN_N B15 PCIE_A_TX P90 S91 P91 S92 HDMI_TX2_P AH27 HDMI_D2 P92 S93 HDMI_TX2_N AJ27 HDMI_D2 P93 S94 P94 S95 HDMI_TX1_P AH26 HDMI_D1 P95 S96 HDMI_TX1_N AJ26 HDMI_D1 P96 S97 P97 S98 HDM...

Page 49: ...AH7 I2C_PM_DAT P122 S123 GPIO13 B8 GPIO1_IO09 P123 S124 P124 S125 LVDS0_0 eDP0_TX0 D29 N A LVDS0_D0_P N A P125 S126 LVDS0_0 eDP0_TX0 E28 N A LVDS0_D0_N N A P126 S127 LCD0_BKLT_EN A3 GPIO1_IO06 P127 S1...

Page 50: ...ECSPI1_SS0 AE20 SER2_CTS P139 S140 I2C_LCD_DAT AE8 I2C2_SDA UART1_TXD AJ3 SER3_TX P140 S141 LCD0_BKLT_PWM AC18 SPDIF_EXT_CLK UART1_RXD AD6 SER3_RX P141 S142 GPIO12 A8 GPIO1_IO08 P142 S143 SAI5_RXD1 A...

Page 51: ...f ensuring that the heat spreader heat sink temperature remain within the indicated range of the module It is an absolute requirement that the customer after thorough evaluation of the processor s wor...

Page 52: ...EVY User Manual Rev First Edition 1 0 Last Edition 1 0 Author S O Reviewed by N P Copyright 2022 SECO S p A 52 SECO S p A Via A Grandi 20 52100 Arezzo ITALY Ph 39 0575 26979 Fax 39 0575 350210 www sec...

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