9.7
Date Code 20020903
SEL-587Z Instruction Manual
Event Reports and SER
Event Reports
Table 9.4
Digital Element Columns
(Sheet 1 of 7)
Column Heading
Corresponding
Elements
(Relay Word Bits)
Symbol
Definition
All columns
.
Element/input/output
not picked up or not
asserted, unless otherwise stated
87ABC1
87A1, 87B1, 87C1
87A1, 87B1
87B1, 87C1
87C1, 87A1
87A1
87B1
87C1
3
a
b
c
A
B
C
Phases A, B, and C
level 1 high-impedance
differential elements asserted
Phases A and B
level 1 high-impedance
differential elements asserted
Phases B and C
level 1 high-impedance
differential element asserted
Phases C and A
level 1 high-impedance
differential elements asserted
Phase A level 1 high-impedance
differential elements asserted
Phase B level 1 high-impedance
differential elements asserted
Phase C level 1 high-impedance
differential elements asserted
87ABC2
87A2, 87B2, 87C2
87A2, 87B2
87B2, 87C2
87C2, 87A2
87A2
87B2
87C2
3
a
b
c
A
B
C
Phases A, B, and C
level 2 high-impedance
differential elements asserted
Phases A and B
level 2 high-impedance
differential elements asserted
Phases B and C
level 2 high-impedance
differential element asserted
Phases C and A
level 2 high-impedance
differential elements asserted
Phase A level 2 high-impedance
differential elements asserted
Phase B level 2 high-impedance
differential elements asserted
Phase C level 2 high-impedance
differential elements asserted
51P
51P, 51PT, 51PR
r
.
p
T
l
Phase time-overcurrent
element deasserted but not reset
Phase time-overcurrent
element deasserted and fully reset
Phase time-overcurrent
element picked up and timing
Phase time-overcurrent
element picked up and timed out
Phase time-overcurrent
element is not picked up
but timing element is asserted
Summary of Contents for SEL-587Z
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