8
this space. Because this space is within the address decoding of the IndustryPack
Memory space, the 2K block will appear at memory address 0 only for slot A. The other
slots will be offset from 0 in 2K increments.
Interrupt Space
The PCI-60A maps all interrupt levels to the INTA# signal on the PCI back plane as
required for single function devices by the PCI Specification 2.1. Because the PCI
interrupts are shared, an interrupt can be from any slot on the back plane or from the
motherboard itself. The interrupt service routine (ISR) must first check that the interrupt
came from the PCI-60A by reading the CNTL2 register on the PCI-60A. If an
IndustryPack is requesting the interrupt, the CNTL1 register can be read to determine
which one. Each of the twelve IndustryPack interrupt lines (2 per IndustryPack) has a bit
in this register. An interrupt will be generated whenever one of these bits is set and
interrupts are enabled. It is up to the ISR to prioritize multiple interrupts if more than one
bit is set. Each bit can be cleared only by clearing the interrupt source on the Industry
Pack.
The interrupt space of each IndustryPack slot is directly accessible at any time. Typically,
the ISR will access the INT space to determine the local cause of the interrupt. A read to
the INT space will generate an IndustryPack Interrupt Cycle. During this cycle, the
IndustryPack places its interrupt vector on the data lines. Some IndustryPacks may
require this access to clear the interrupt. Check the IndustryPack's User Manual for
specific details on clearing interrupts.
Please refer to the Control and Status register bit map section for more information.
IndustryPack Bus Time-Out
The PCI-60A has a programmable IndustryPack bus error timer. When enabled, the PCI-
60A will time out if the IndustryPack being accessed does not respond. This allows the
IndustryPack slots to be interrogated during start up to determine what IndustryPacks are
installed in what slots. Without this feature, accessing an IndustryPack slot that does not
respond will usually put the PCI bus in an infinite retry loop, essentially locking up the
host processor.
When the Bus Error feature is enabled, the hardware will create a “bus reply” for an
IndustryPack that does not respond within 3.2 µs. The hardware can also generate an
interrupt to the host when the reply is from the timer instead of the IndustryPack.
Interrupts may also be disabled and the bus error timer status may be polled. Three bits
are used to control the way the bus error timer works. The AUTO_ACK bit in CNTL0
enables the bus error timer. When it is set to “1”, the bus error timer will generate an Ack*
whenever an IndustryPack is accessed but does not respond. A status bit in CNTL2,
AUTO_INT_SET, will be set if the CLR_AUTO bit in CNTL0 is set to “1”. Once set, the
AUTO_ INT_SET bit will stay set until the CLR_AUTO bit is cleared to “0”. The AUTO_
INT_SET bit will generate an interrupt if the INT_EN bit in CNTL0 is set to “1” and the
Local Interrupt Enable bit in the PCI 9080 Interrupt Control/Status Register is set to “1”.
With the INT_EN bit cleared to “0”, the AUTO_ INT_SET bit may be polled.
The PCI 9080 always posts to its internal write FIFO before actually performing the write
to the local bus side (i.e., the IndustryPack or CNTRL register). This leads to problems
when a write causes a bus error on the local bus side and the AUTO_ACK feature is not
enabled. The write appears to complete with no problems. However, the next access to
the PCI-60A puts the PCI bus in an infinite retry loop as the PCI 9080 is still waiting for
the previous access to complete. This effectively locks up the host computer.
Please refer to the
Bit Map
section for more information.
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