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host is the only bus master, performance should not be affected. The 2.1 compliant mode
only affects read cycles, as writes are always posted to the PCI-9080's internal write
FIFO. The PCI-9080 terminates the PCI bus write cycle, then writes the data out to the
local bus.
When not in the 2.1 compliant mode, the PCI-9080 uses a retry delay timer that issues a
retry when the timer expires. The factory default setting for the timer is the maximum
allowed 128 PCI clock cycles, which is 3.8 µsec for a 33 MHz PCI bus. An IndustryPack
must respond within 3.5 µsecs to keep the timer from expiring, taking into account the
overhead to translate the access to the IndustryPack bus. Some IndustryPacks may not
be able to meet this requirement, particularly those IndustryPacks that read serial
EEPROMs. IndustryPacks that have processors with which the IndustryPack control
hardware must arbitrate to gain access to the local bus may also have problems meeting
this response time. This should not be a problem if it happens infrequently. However,
other cards on the PCI bus may suffer due to the loss of PCI bandwidth while the PCI-
60A holds onto the bus.
The PCI 2.1 compliant mode is set with bits 24 and 26 in the Mode/Arbitration Register of
the PCI 9080 chip. It gets loaded from the configuration EEPROM, but may be changed
at run time. See the PLX PCI-9080 data sheet and the EEPROM Programming section
for more information.
Read Ahead Mode
The PCI 9080 can operate in a read ahead mode, where it will prefetch the data from the
next address on the IndustryPack. On subsequent reads, the data will be read from the
PCI 9080's internal FIFO rather than from the IndustryPack. This is incompatible with
most IndustryPacks. The default setting is to leave this mode disabled. The bit controlling
this feature is the Memory Space 0 Prefetch Disable bit [8] in the Local Address Space
0/Expansion ROM Bus Region Descriptor Register. The Read Prefetch Count Enable bit
[10] in the same register must be set to a “1” to disable the prefetch mode. Refer to the
PCI 9080 Data Sheet for more information.
Interrupts
The PCI-60A maps all 12 of the IndustryPack interrupts as well as its internal interrupts
into the Local Interrupt In pin on the PCI 9080. These are routed in the PCI 9080 to the
PCI bus INTA line, per the PCI 2.1 specification for single function devices. To enable
interrupts, the INTEN bit, the CNTL0 Bit[6], and both the PCI Interrupt Enable Bit[8] and
the PCI Local Interrupt Enable Bit[11] in the PCI 9080 Interrupt Control/Status must be
set to one. The PLX Interrupt Control/Status register is located at an offset of 0x68 from
the address held in the BAR0. The following is an example of the steps and values to
enable the IndustryPacks to interrupt the host CPU.
•
Set CNTL0 to 0x007X. This value enables interrupts from the IndustryPacks to reach
the PCI 9080, enables bus timeout on an access to an empty IndustryPack slot, and
enables the bus timeout interrupt to reach the PCI 9080. The X value should be set
to the proper clock speed bits for each IndustryPack slot. CNTL0 is relative to BAR2.
•
Set PCI 9080 Interrupt Control/Status Register (INTCSR) to 0x000D0900. This value
enables interrupts from the IndustryPacks or the bus timeout to reach the host CPU.
INTCSR is relative to BAR0.
All IndustryPacks capable of generating interrupts must also supply an Interrupt Vector
during an interrupt acknowledge (IACK) cycle. Since the PCI bus does not have an
inherent IACK cycle, the PCI-60A has a separate address space for each IndustryPack
that will create an IACK cycle when read. Reading from offset address 0x0 in the
Interrupt Space will read the IntReq0* Interrupt Vector. Address 0x2 will read the
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