15
To ensure software compatibility with other versions of PCI 9080
family and to ensure compatibility with future enhancements, write
0 to all unused bits.
PCI CFG
Register
Address
31 24
23 16
15 8
7 0
PCI
Writeable
Written by
Serial
EEPROM
0x00
Device ID
Vendor ID
N
Y
0x04 Status Command
Y
N
0x 08
Class Code
Revision ID
Local
Y
Y[15:0]
N
0x 0C
BIST
Header Type
PCI Latency Timer
Cache Line Size
Y
N
0x 10
PCI Base Address 0 for Memory Mapped Configuration Registers
(BAR0) Y
N
0x 14
PCI Base Address 1 for I/O Mapped Configuration Registers (BAR1)
Y
N
0x 18
PCI Base Address 2 for Local Address Space 0 (BAR2)
Y N
0x 1C
PCI Base Address 3 for Local Address Space 1 (BAR3)
Y N
0x 20
Unused Base Address (BAR4)
N N
0x 24
Unused Base Address (BAR5)
N N
0x 28
Cardbus CIS Pointer (Not Supported)
N N
0x 2C
Subsystem ID Subsystem Vendor ID
N Y
0x 30
PCI Base Address for Local Expansion ROM
Y N
0x 34
Reserved
N N
0x 38
Reserved
N N
0x 3C
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Y [7:0]
Y
Figure 6. PCI Configuration Registers
Programming the PCI 9080 Registers
At power on, or after a PCI bus reset, the PCI 9080 reads a serial EEPROM to determine
what responses to give to the BIOS. The EEPROM must be programmed to indicate
whether the PCI-60A is an interrupt generator, how much memory should be allocated,
and re-mapping of the memory, etc. The following sections describe some of the modes
that may be applicable to IndustryPacks. Please refer to the PCI 9080 Data Sheet for a
complete description of the registers.
PCI 2.1 Mode
The PCI-9080 chip has two modes of operation, one in which it will hold onto the PCI bus
during the entire IndustryPack read access and one in which it will issue an immediate
retry on the PCI bus and continue issuing retries until the IndustryPack has responded.
This second mode is compliant with the PCI 2.1 specification that requires all targets to
respond within sixteen PCI clock cycles. It is the factory default and, for a 33 MHz PCI
bus, it is equivalent to 485 ns. It is not possible for the PCI-60A to respond within this
time, even with a zero wait state 32 MHz IndustryPack. This mode may slow overall
access to the IndustryPack as the master gives up ownership of the bus when it receives
the retry and must arbitrate to get it back. In lightly loaded systems, or systems where the
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