-98-
■
Control Port Functions
●
System Control & I/O Port Table (IC801, HD6417727)
1
Vcc-RTC
1.9V
Vcc for RTC (1.9V)
-
-
2
XTAL2
(Open)
-
3
EXTAL2
(Vcc)
-
4
Vss-RTC
GND
Vss for RTC (0V)
-
-
5
MD1
MD1
Clock Mode Setting [Default:L]
I
6
MD2
MD2
Clock Mode Setting [Default:L]
I
7
NMI
NMI
Non Maskable Interrupt
I
8
IRQ0/IRL0/PTH[0]
FPGA2_INTR
FPGA2 Interrupt Signal
I
9
IRQ1/IRL1/PTH[1]
USB_INTR
USB Interrupt Signal
Active L
I
10
IRQ2/IRL2/PTH[2]
VSYNC_INTR
LCD Panel Driving V_Sync Interrupt Signal
Active L
I
11
IRQ3/IRL3/PTH[3]
FPGA1_INTR
FPGA1 Interrupt Signal
Active L
I
12
IRQ4/PTH[4]
R/C
Remote Control Signal Input
Active L
I
13
VEPWC
(Open)
-
14
VCPWC
(Open)
-
15
MD5
MD5
I
16
BREQ
(Pull-up)
-
17
BACK
(Open)
-
18
VssQ
GND
Vss for I/O (0V)
-
-
19
CKIO2
(Open)
-
20
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
21 - 28
D31/PTB[7] - D24/PTB[0]
D31 - D24
Data Bus
-
I/O
29
VssQ
GND
Vss for I/O (0V)
-
-
30
D23/PTA[7]
D23
Data Bus
-
I/O
31
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
32 - 34
D22/PTA[6] - D20/PTA[4]
D22
Data Bus
-
I/O
35
Vss
GND
Vss (0V)
-
-
36
D19/PTA[3]
D19
Data Bus
-
I/O
37
Vcc
1.9V
Vcc (1.9V)
-
-
38 - 40
D18/PTA[2] - D16/PTA[0]
D18
Data Bus
-
I/O
41
D15
D15
Data Bus
-
I/O
42
VssQ
GND
Vss for I/O (0V)
-
-
43
D14
D14
Data Bus
-
I/O
44
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
45 - 52
D13 - D6
D13
Data Bus
-
I/O
53
VssQ
GND
Vss for I/O (0V)
-
-
54
D5
D5
Data Bus
-
I/O
55
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
56 - 60
D4 - D0
D4
Data Bus
-
I/O
61
A0
A0
Address Bus
-
O
62
A1
A1
Address Bus
-
O
63
A2
A2
Address Bus
-
O
64
VssQ
GND
Vss for I/O (0V)
-
-
65
A3
A3
Address Bus
-
O
66
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
67 - 74
A4 - A11
A4
Address Bus
-
O
75
VssQ
GND
Vss for I/O (0V)
-
-
76
A12
A12
Address Bus
-
O
77
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
78 - 85
A13 - A20
A13
Address Bus
-
O
86
VssQ
GND
Vss for I/O (0V)
-
-
87
A21
A21
Address Bus
-
O
88
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
89
A22
A22
Address Bus
-
O
90
A23
A23
Address Bus
-
O
91
Vss
GND
Vss (0V)
-
-
92
A24
A24
Address Bus
-
O
93
Vcc
1.9V
Vcc (1.9V)
-
-
94
A25
A25
Address Bus
-
O
95
BS/PTK[4]
BS [for ICE]
Bus Cycle Starting Signal
O
96
RD
RD
Read Strobe
O
97
WE0/DQMLL
WE0
D7-D0 Select Signal / DQM (SDRAM)
O
98
WE1/DQMLU/WE
WE1
D15-D8 Select Signal / DQM (SDRAM)
O
99
WE2/DQMUL/ICIORD/PTK[6]
WE2
D23-D16 Select Signal / DQM (SDRAM)
O
100
VssQ
GND
Vss for I/O (0V)
-
-
101
WE3/DQMUU/ICIOWR/PTK[7]
WE3
D31-D24 Select Signal / DQM (SDRAM)
O
102
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
Pin No.
Name
Function Name
Function
Polarity
I/O
Summary of Contents for PLV-HD2000E
Page 109: ... 109 IC Block Diagrams ICS1523M Clock Driver IC8209 CXA2151Q RGB Matrix IC271 ...
Page 166: ... 166 MEMO ...
Page 167: ... 167 MEMO ...
Page 168: ... PLV HD2000N E JUL 2006 BB 350 Printed in Japan SANYO Electric Co Ltd ...
Page 194: ...A26 PCB_MA4A BGA side A FANNET_3 K16W MAIN K8L MAIN K401 MAIN K8K MAIN K2203 BGA side B ...
Page 196: ...A28 PCB_MA4A ...
Page 198: ...Diagrams Drawings MA4 HD2000N00 PA4 HD2000E00 ...