Sanyo PLV-55WM1, Service Manual

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I/O Port Table of Main CPU (IC301, PW172A)
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Control Port Functions
178 Port A7 LAMP_PWM PWM Output to Lamp_CPU PWM O
115 Port A6 NMI I
44 Port A5 SCL1 I/O
116 Port A4 SDA1 O
45 Port A3 SCL2 I/O
46 Port A2 SDA2 O
117 Port A1 SCL 3 Line Serial Bus Clock O
180 Port A0 SDA 3 Line Serial Bus Data O
173 Port B7 GAMMA_RS Reset Input I
111 Port B6 GAMMA_ST 3 Line Serial Bus Strobe O
40 Port B5 Not used
174 Port B4 POWER_FAIL Power Fail Detection Error = L I
41 Port B3 A23 Address Bus 23
175 Port B2 A22 Address Bus 22
112 Port B1 A21 Address Bus 21
229 Port B0 A20 Address Bus 20
71 Port E7 -
139 Port E6 BOX_SW PJ-Net Connection Connect = L I
200 Port E5 -
140 Port E4 NET_SW PJ-Net ON/OFF ON = L O
201 Port E3 DDC_DAT2
141 Port E2 DDC_CLK2
72 Port E1 DDC_DAT1 Standby 15V OFF Standby = L O
142 Port E0 DDC_CLK1 USB Device Enable Output O
119 Port F7 IRRCVR1 IR Receiver Input 1 Not used I
182 Port F6 IRRCVR0 IR Receiver Input 0 I
47 Port F5 RXD I
181 Port F4 TXD O
189 Port F3 CS0 I/O Expander Chip Select (Output) O
55 Port F2 CS1 I/O Expander Chip Select (Input) O
207 Port F1 DCLKEXT D-port Clock External Input Not used I
257 Port F0 MCLKEXT Memory System Clock Input Not used I
194 A19 A19 Address Bus 19
63 A19 A18 Address Bus 18
132 A17 A17 Address Bus 17
62 A16 A16 Address Bus 16
61 A15 A15 Address Bus 15
131 A14 A14 Address Bus 14
193 A13 A13 Address Bus 13
247 A12 A12 Address Bus 12
60 A11 A11 Address Bus 11
246 A10 A10 Address Bus 10
59 A9 A9 Address Bus 9
130 A8 A8 Address Bus 8
129 A7 A7 Address Bus 7
192 A6 A6 Address Bus 6
128 A5 A5 Address Bus 5
58 A4 A4 Address Bus 4
191 A3 A3 Address Bus 3
190 A2 A2 Address Bus 2
245 A1 A1 Address Bus 1
244 A0 A0 Address Bus 0
242 D15 D15 Data Bus 15 I/O
241 D14 D14 Data Bus 14 I/O
187 D13 D13 Data Bus 13 I/O
53 D12 D12 Data Bus 12 I/O
124 D11 D11 Data Bus 11 I/O
186 D10 D10 Data Bus 10 I/O
240 D9 D9 Data Bus 9 I/O
123 D8 D8 Data Bus 8 I/O
185 D7 D7 Data Bus 7 I/O
122 D6 D6 Data Bus 6 I/O
51 D5 D5 Data Bus 5 I/O
184 D4 D4 Data Bus 4 I/O
121 D3 D3 Data Bus 3 I/O
50 D2 D2 Data Bus 2 I/O
49 D1 D1 Data Bus 1 I/O
183 D0 D0 Data Bus 0 I/O
118 BHEN BHEN High Byte Enable I/O
230 Port C0 CS2 Chip Select 2 O
48 RESET RESET Master Reset Input I
Pin No. Name Function Name Function Polarity I/O
1
4 49
183
4
1
D1
D0 D
D0 D
D
ata B
ata B
B
2
s 1
0
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Pin
O Po ort Table of Main CPU (IC3
N
01, PW17
Func O olarit
2
19
Por
A19 t F0
9
M
A CLK
9
I ed us Not put k In lock m C stem
s 19 mory
ess
Mem
Addre m
re