Sanyo AVD-8501, Service Manual

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IC BLOCK DIAGRAM & DESCRIPTION
IC861 PCM1602Y (Digital to Analog Converter)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
O
O
O
O
O
O
-
-
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
I
I
I
I
I
O
I
I
-
-
-
I
I
I
O
NAME
ZERO1/GPO1
ZERO2/PGO2
ZERO3/PGO3
ZERO4/PGO4
ZERO5/PGO5
ZERO6/PGO6
NC
NC
V
OUT
6
V
OUT
5
V
OUT
4
V
OUT
3
V
OUT
2
V
OUT
1
V
COM
NC
AGND5
V
CC
5
AGND6
NC
AGND4
V
CC
4
AGND3
V
CC
3
AGND2
V
CC
2
AGND1
V
CC
1
NC
NC
NC
NC
MDO
MDI
MC
ML
RST
SCKI
SCKO
BCK
LRCK
TEST
V
DD
DGND
DATA1
DATA2
DATA3
ZEROA
DESCRIPTION
Zero Data Flag for V
OUT
1. Can also be used as GPO pin.
Zero Data Flag for V
OUT
2. Can also be used as GPO pin.
Zero Data Flag for V
OUT
3. Can also be used as GPO pin.
Zero Data Flag for V
OUT
4. Can also be used as GPO pin.
Zero Data Flag for V
OUT
5. Can also be used as PGO pin.
Zero Data Flag for V
OUT
6. Can also be used as PGO pin.
No Connection
No Connection
Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DAYA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA1. Up to 192kHz.
Common Voltage Output. This pin should be bypassed with a 10 F capacitor to AGND.
No Connection
Analog Ground
Analog Power Supply, +5V
Analog Ground
No Connection
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
No Connection
No Connection
No Connection
No Connection
Serial Data Output for Serial Control Port
Serial Data Input for Serial Control Port
Shift Clock for Serial Control Port
Latch Enable for Serial Control Port
System Reset, Active LOW
System Clock Inout. Input frequency is 128,192,256,384,512, or 768f
s
.
Buffered Clock Output. Output frequency is 128,192,256,384,512, or 768f
s
, or one-half of 128,192,256,384,512, or 768f
s
.
Shift Clock Input for Serial Audio Data. Clock must be 32,48, or 64f
s
.
Left and Right Clock Input. This clock is equal to the sampling rate, f
s
.
Test Pin. This pin should be connected to DGND.
Digital Power Supply, +3.3V
Digital Ground
Serial Audio Data Input for V
OUT
1 and V
OUT
2
Serial Audio Data Input for V
OUT
3 and V
OUT
4
Serial Audio Data Input for V
OUT
5 and V
OUT
6
Zero Data Flag. Logical "AND" of ZERO1 through ZERO6.
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger inout, 5V tolerant. (3) Tri-state output.
PIN ASSIGNMENTS