Sanyo AVD-8501, Service Manual

Page: 51 / 110

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IC BLOCK DIAGRAM & DESCRIPTION
-MPEG SECTION-
IC871,881 LE28DW8102T-90-MPB (Flash Memory)
Control Logic
CE#
OE#
WE#
A18-A0
Address Buffer
&
Latch Circuit
Charge Pump
&
Constant Voltage
Circuit
Input/Output
Buffer Data Latch
DQ15.DQ0
256Kx16
Flash
Bank 1
256Kx16
Flash
Bank 2
Low Decoder
Column Decoder
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
A0
A1
A15
A14
A13
A12
A11
A10
A9
A8
WE#
NC
NC
NC
NC
NC
NC
A18
A17
A78
A6
A5
A4
A3
A2
ACE#
Symbol
Description
Function
A18
A17-A0
A17-A15
A17-A10
DQ15-DQ0
CE#
OE#
WE#
VDD
GND
NC
Bank select address
Flash bank address
Flash bank block address
Flash bank selector address
Data input/output
Use able the chip
Able to output
Able to write on
Power supply
Ground
No connect
Select Bank 1 (negative) or Bank 2 (positive)
Flash bank address at write on
Select at flash bank for erase
Select at flash bank sector for erase
Use able the data flash bank when CE# is negative
Use able the data output buffer
Write on, Erase, Program control
Power supply (2.07V~3.6V)
Ground
No connect
Output the data while lead cicle and receive the input data
while write on cicle
IC804,805 TC74LCX373FT (Low Voltage Octal D-type Latch with 5V Tolerant Inputs and Outputs)
1
2
3
4
5
6
7
8
9
10
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Truth Table
OE
H
L
L
L
D
X
X
L
H
OUTPUTS
Z
Qn
L
H
INPUTS
LE
X
L
H
H
X : Don't Care
Z : High impedance
Qn : Q Output level before LE turn into "L"
3
11
1
D0
2
Q0
D
Q
L
4
D1
5
Q1
D
Q
L
7
D2
6
Q2
D
Q
L
8
D3
9
Q3
D
Q
L
13
D4
12
Q4
D
Q
L
14
D5
15
Q5
D
Q
L
17
D6
16
Q6
D
Q
L
18
D7
19
Q7
D
Q
L
LE
OE