SDP3B FlashDisk Product Manual
SanDisk SDP3B FlashDisk Product Manual © 1998 SANDISK CORPORATION
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Table 6-5 Features Supported
Feature
Operation
01H
Enable 8 bit data transfer.
55H
Disable Read Look Ahead.
66H
Disable Power on Reset (POR) establishment of defaults at Soft Reset.
69H
Accepted for backward compatibility with the SDP Series but has no impact on the SDP3B FlashDisk.
81H
Disable 8 bit data transfer.
96H
Accepted for backward compatibility with the SDP Series but has no impact on the SDP3B FlashDisk.
9AH
Set the host current source capability. Allows tradeoff between current drawn and read/write speed.
BBH
4 bytes of data apply on Read/Write Long commands.
CCH
Enable Power on Reset (POR) establishment of defaults at Soft Reset.
Features 01H and 81H are used to enable and clear
8 bit data transfer mode. If the 01H feature com-
mand is issued, all data transfers will occur on the
low order D7-D0 data bus and the IOIS16 signal
will not be asserted for data register accesses.
Features 55H and BBH are the default features
for the SDP3B FlashDisk; thus, the host does not
have to issue this command with these features
unless it is necessary for compatibility reasons.
The 9AH Feature is a SDP3B FlashDisk unique
option that provides a mechanism for the host
system to adjust how much current the SDP3B
FlashDisk will use. The SDP3B FlashDisk
reduces the current it draws by reducing its
operating frequency. This has the impact of also
reducing the performance of the
SDP3B
FlashDisk. The default for the SDP3B FlashDisk
after a power on reset is to operate at the highest
performance and therefore the highest current
mode. However after a power on, the SDP3B
FlashDisk will not draw more than its minimum
current as long as the host does not issue any
command which reads or writes to the flash
memory. This allows the host to issue the Set
Features command to set the desired power level
without exceeding the minimum requirement of
the SDP3B FlashDisk.
To reduce the current the SDP3B FlashDisk
draws, the host issues the Set Features command
with the Feature register set to 9AH and the
Sector Count register (Config) set to a current value
which is equal to 4 mA times the value in the
Sector Count register. When this is done, the
controller will utilize a look-up table to program
the controller’s frequency, microprocessor’s speed
and flash clocks with an optimum value to
provide the highest performance without
exceeding the host’s current limit. For example, if
a host can supply 75 mA of current to the SDP3B
FlashDisk, the Sector Count register would be set
to 75 divided by 4 (rounded down) or a value of 18.
The SDP3B FlashDisk would then automatically
reduce its clock frequencies so that it will not draw
more than 75 mA (average, at nominal Vcc and
room temperature) of current. If the host always
wanted to operate at the lowest possible current
the Sector Count value should be set to 1. The
SDP3B FlashDisk will then operate at the lowest
possible
current
(and
also
the
lowest
performance).
At the completion of this command, the controller
will update the Cylinder Low register with the
controller’s minimum valid current value (i.e. the
minimum current with which the SDP3B
FlashDisk can operate) and the Cylinder High
register with the maximum current it will use (i.e.
the maximum current the SDP3B FlashDisk will
draw at the highest performance level). The
controller will use its minimum value for any
Sector Count value which is less than its minimum
value. For example, if the Sector Count is set to 4
which is equivalent to 16 mA, the controller will
operate at the lowest possible power point but
will not reject the command. Similarly the
controller will use its maximum value for any
Sector Count value which is more than the
maximum current it can use.
There is no error associated with the 9AH feature.
Features 66H and CCH can be used to enable and
disable whether the Power On Reset (POR)
Defaults will be set when a soft reset occurs. The
default setting is to revert to the POR defaults
when a soft reset occurs. POR defaults the number
of heads and sectors along with 16 bit data
transfers and the read/write multiple block count.