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SDP3B FlashDisk Product Manual

5.4

True IDE Mode Addressing

When the SDP3B FlashDisk is configured in the
True IDE Mode the I/O decoding is as follows:

Table 5-5 True IDE Mode I/O Decoding

- C E 2

- C E 1

- I O R D = 0

- I O W R = 0

Note

Even RD Data

Even WR Data

Error Register

Features

Sector Count

Sector No.

Cylinder Low

Cylinder High

Select Card/Head

Status

Command

Alt Status

Device Control

Drive Address

Reserved

Summary of Contents for SDP3B

Page 1: ...SDP3B FlashDisk Product Manual CORPORATE HEADQUARTERS 140 Caspian Court Sunnyvale CA 94089 408 542 0500 FAX 408 542 0503 URL http www sandisk com ...

Page 2: ...rial All parts of the SanDisk SDP3B FlashDisk documentation are protected by copyright law and all rights are reserved This documentation may not in whole or in part be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form without prior consent in writing from SanDisk Corporation SanDisk and the SanDisk logo are registered trademarks of SanDisk Corpo...

Page 3: ...t Erase Commands 12 1 7 5 1 Interaction with Systems not Aware of the Erase Sector and Write without Erase Commands 12 1 7 5 2 Limitations and Issues 13 1 7 6 Automatic Sleep Mode 13 1 7 7 Dynamic Adjustment of Performance versus Power Consumption 13 1 7 8 Power Supply Requirements 13 2 0 Product Specifications 14 2 1 SDP3B FlashDisk System Environmental Specifications 14 2 2 SDP3B FlashDisk Syste...

Page 4: ...O Transfer Function 45 4 7 1 True IDE Mode I O Function 45 5 0 ATA Drive Register Set Definition and Protocol 46 5 1 I O Primary and Secondary Address Configurations 47 5 2 Contiguous I O Mapped Addressing 48 5 3 Memory Mapped Addressing 49 5 4 True IDE Mode Addressing 50 5 5 ATA Registers 51 5 5 1 Data Register Address 1F0 170 Offset 0 8 9 51 5 5 2 Error Register Address 1F1 171 Offset 1 0Dh Read...

Page 5: ... 1 5 20 Current Number of Cylinders Heads Sectors Track 63 6 1 5 21 Current Capacity 63 6 1 5 22 Multiple Sector Setting 63 6 1 5 23 Total Sectors Addressable in LBA Mode 63 6 1 6 Idle 97H E3H 64 6 1 7 Idle Immediate 95H E1H 64 6 1 8 Initialize Drive Parameters 91H 65 6 1 9 Read Buffer E4H 65 6 1 10 Read Multiple C4H 66 6 1 11 Read Long Sector 22H 23H 67 6 1 12 Read Sector s 20H 21H 67 6 1 13 Read...

Page 6: ...upport 99 Ordering Information 101 SanDisk SDP3B FlashDisk Series 101 SanDisk FlashDisk Evaluation Kit 101 SanDisk FlashDisk Adapter Board 102 Technical Support Services 103 Direct SanDisk Technical Support 103 SanDisk Worldwide Web Site 103 System Software and Card Reader Writers Compatible with the SanDisk SDP3B FlashDisk 104 SanDisk Worldwide Sales Offices 107 Limited Warranty 110 ...

Page 7: ...h memory chips the SDP3B FlashDisks include an on card intelligent controller that provides a high level interface to the host computer This interface allows a host computer to issue commands to the memory card to read or write blocks of memory A block of memory consists of 512 bytes of data and is protected by a powerful Error Correcting Code ECC The SDP3B FlashDisk on card intelligent controller...

Page 8: ...N First St Suite 209 San Jose CA 95134 USA Phone 408 433 2273 Fax 408 433 9558 1 PCMCIA PC Card Standard January 1995 2 PCMCIA PC Card ATA Specification January 1995 1 5 Related Documentation 1 American National Standard X3 221 AT Attachment for Interface for Disk Drives Document This document can be obtained by calling Global Engineering at 1 800 854 7179 1 6 The SDP3B FlashDisk Compared to Previ...

Page 9: ... 2 Sleep mode currently is specified under the condition that all card inputs are static CMOS levels and in a Not Busy operating state Note 3 The currents specified show the bounds of programmability of the product Model SDP5A Standard FlashDisk Industrial FlashDisk DC Input Voltage VPP Note 4 Not Used Not Used DC Input Voltage VCC 100 mv max ripple p p 5 V 10 5 V 5 5 V Currents maximum average va...

Page 10: ...ers SDP5A 5 Type II 5 242 880 bytes 10 240 2 32 160 SDP5A 10 Type II 10 485 760 bytes 20 480 2 32 320 SDP5A 20 Type II 20 971 520 bytes 40 960 2 32 640 SDP5A 40 Type II 41 943 040 bytes 81 920 4 32 640 SDP5A 110 Type III 110 100 480 bytes 215 040 8 32 840 SDP5A 175 Type III 175 374 336 bytes 342 528 12 32 892 Model Number Form Factor Capacity formatted Sectors Card Max LBA 1 No of Heads No of Sect...

Page 11: ...overy including a powerful error correction code ECC 5 Power management for low power operation 1 7 1 Flash Technology Independence The 512 byte sector size of SDP3B FlashDisk is the same as that in an IDE magnetic disk drive To write or read a sector or multiple sectors the host computer software simply issues a Read or Write command to the SDP3B FlashDisk This command contains the address and th...

Page 12: ...The Erase Sector and Write without Erase commands provide the capability to substantially increase the write performance of the SDP3B FlashDisk Once a sector has been erased using the Erase Sector command a write to that sector will be much faster This is because a normal write operation includes a separate sector erase prior to write An example of where these commands may be useful is in a digita...

Page 13: ...ompletion to entering sleep mode can be adjusted When the host is ready to access the SDP3B FlashDisk and it is in sleep mode any command issued to the SDP3B FlashDisk will cause it to exit sleep and respond The host does not have to follow the ATA protocol of issuing a reset first It may do this if desired but it is not needed By not issuing the reset performance is improved through the reduction...

Page 14: ...Standard Version SDP3BI Industrial Version DC Input Voltage VCC 100 mV max ripple p p 3 3V 5 5V 10 3 3V 5 5V 5 Only Capacities of 85 MB Lower 5 V Currents maximum Average value See Notes 1 to 3 Sleep Reading Writing Read Write Peak 200 µA Slow Fast 32 mA 45 mA 32 mA 60 mA 150 mA 50µs 500 µA Slow Fast 46 mA 75 mA 46 mA 90 mA 150 mA 50µs 200 µA Slow Fast 32 mA 45 mA 32 mA 60 mA 150 mA 50µs 500 µA Sl...

Page 15: ...hen any command is issued by the host to when the card is reading or writing SDP3B FlashDisks do not require a reset to exit sleep mode See section 1 7 6 2 4 System Reliability and Maintenance MTBF 25 C 1 000 000 hours for Type II SDP3B FlashDisk 500 000 hours for Type III SDP3B FlashDisk Preventive Maintenance None Data Reliability 1 non recoverable error in 1014 bits read Endurance SDP3B XX 300 ...

Page 16: ...SDP3B FlashDisk Product Manual SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 16 Figure 2 1 SDP3B Type II FlashDisk Dimensions ...

Page 17: ...SDP3B FlashDisk Product Manual SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 17 Figure 2 2 SDP3B Type III FlashDisk Dimensions ...

Page 18: ...ytes 3 936 2 16 123 SDP3B 4 Type II 4 030 464 bytes 7 872 2 32 123 SDP3B 6 Type II 6 029 312 bytes 11 776 2 32 184 SDP3B 8 Type II 8 028 160 bytes 15 680 2 32 245 SDP3B 10 Type II 10 485 760 bytes 20 480 2 32 320 SDP3B 20 Type II 20 971 520 bytes 40 960 2 32 640 SDP3B 40 Type II 41 943 040 bytes 81 920 4 32 640 SDP3B 60 Type II 60 162 048 bytes 117 504 6 32 612 SDP3B 85 Type II 85 196 800 bytes 16...

Page 19: ...lashDisk Product Manual 1998 SANDISK CORPORATION 19 3 0 Installation 3 1 Mounting The Type II SDP3B FlashDisks fit into any standard PCMCIA Type II 5 mm or Type III 10 5 mm socket The Type III SDP3B FlashDisks only fit into Type III PCMCIA sockets ...

Page 20: ... Description The SDP3B FlashDisk is optimized for operation with hosts which support the PCMCIA I O interface standard conforming to the PC Card ATA specification However the SDP3B FlashDisk may also be configured to operate in systems that support only the memory interface standard The configuration of the SDP3B FlashDisk will be controlled using the standard PCMCIA configuration registers starti...

Page 21: ...EQ O OT1 16 INTRQ O OZ1 17 VCC Power 17 VCC Power 17 VCC Power 18 VPP Not Used 18 VPP Not Used 18 VPP Not Used 19 19 19 20 20 20 21 21 21 22 A07 I I1Z 22 A07 I I1Z 22 A072 I I1Z 23 A06 I I1Z 23 A06 I I1Z 23 A062 I I1Z 24 A05 I I1Z 24 A05 I I1Z 24 A052 I I1Z 25 A04 I I1Z 25 A04 I I1Z 25 A042 I I1Z 26 A03 I I1Z 26 A03 I I1Z 26 A032 I I1Z 27 A02 I I1Z 27 A02 I I1Z 27 A02 I I1Z 28 A01 I I1Z 28 A01 I I...

Page 22: ...57 VS2 O OPEN 57 VS2 O OPEN 57 VS2 O OPEN 58 RESET I I2Z 58 RESET I I2Z 58 RESET I I2Z 59 WAIT O OT1 59 WAIT O OT1 59 IORDY O ON1 60 INPACK O OT1 60 INPACK O OT1 60 INPACK O OZ1 61 REG I I3U 61 REG I I3U 61 REG3 I I3U 62 BVD2 I O I1U OT1 62 SPKR I O I1U OT1 62 DASP I O I1U ON1 63 BVD1 I O I1U OT1 63 STSCHG I O I1U OT1 63 PDIAG I O I1U ON1 64 D081 I O I1Z OZ3 64 D081 I O I1Z OZ3 64 D081 I O I1Z OZ3...

Page 23: ...r Slave handshake protocol BVD2 PC Card Memory Mode I O 62 This output line is always driven to a high state in Memory Mode since a battery is not required for this product SPKR PC Card I O Mode This output line is always driven to a high state in I O Mode since this product does not support the audio function DASP True IDE Mode In the True IDE Mode this input output is the Disk Active Slave Prese...

Page 24: ... IDE Mode all Task File operations occur in byte mode on the low order bus D00 D07 while all data transfers are 16 bit using D00 D15 GND PC Card Memory Mode 1 34 35 68 Ground GND PC Card I O Mode This signal is the same for all modes GND True IDE Mode This signal is the same for all modes INPACK PC Card Memory Mode O 60 This signal is not used in this mode INPACK PC Card I O Mode Input Acknowledge...

Page 25: ...ready to accept a new data transfer operation and held low when the card is busy The Host memory card socket must provide a pull up resistor At power up and at Reset the RDY BSY signal is held low busy until the SDP3B FlashDisk has completed its power up or reset function No access of any type should be made to the SDP3B FlashDisk during this time The RDY BSY signal is held high disabled from bein...

Page 26: ...P True IDE Mode This signal is the same for all modes VS1 VS2 PC Card Memory Mode O 43 57 Voltage Sense Signals VS1 is grounded so that the SDP3B FlashDisk CIS can be read at 3 3 volts and VS2 is open and reserved by PCMCIA for a secondary voltage VS1 VS2 PC Card I O Mode This signal is the same for all modes VS1 VS2 True IDE Mode This signal is the same for all modes WAIT PC Card Memory Mode O 59...

Page 27: ...ch This signal is held low after the completion of the reset initialization sequence IOIS16 PC Card I O Mode I O Operation When the SDP3B FlashDisk is configured for I O Operation Pin 24 is used for the I O Selected is 16 Bit Port IOIS16 function A Low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port IOCS16 True IDE Mode In True IDE Mode this output ...

Page 28: ...ics described in section 4 3 2 For example I1U indicates a pull up resistor with a type 1 input characteristic Type Parameter Symbol Conditions MIN TYP MAX Units IxZ Input Leakage Current IL Vih Vcc Vil Gnd 1 1 µA IxU Pull Up Resistor RPU1 Vcc 5 0V 50k 500k Ohm IxD Pull Down Resistor RPD1 Vcc 5 0V 50k 500k Ohm Note The minimum pullup resistor leakage current meets the PCMCIA specification of 10k o...

Page 29: ... Type Output Type Valid Conditions OTx Totempole Ioh Iol OZx Tri State N P Channel Ioh Iol OPx P Channel Only Ioh Only ONx N Channel Only Iol Only 4 3 4 Output Drive Characteristics Type Parameter Symbol Conditions MIN TYP MAX Units 1 Output Voltage Voh Vol Ioh 4 mA Iol 4 mA Vcc 0 8V Gnd 0 4V Volts 2 Output Voltage Voh Vol Ioh 8 mA Iol 8 mA Vcc 0 8V Gnd 0 4V Volts 3 Output Voltage Voh Vol Ioh 8 mA...

Page 30: ... Read Timing Speed Version 300 ns Item Symbol IEEE Symbol Min ns Max ns Read Cycle Time tc R tAVAV 300 Address Access Time ta A tAVQV 300 Card Enable Access Time ta CE tELQV 300 Output Enable Access Time ta OE tGLQV 150 Output Disable Time from CE tdis CE tEHQZ 100 Output Disable Time from OE tdis OE tGHQZ 100 Address Setup Time tsu A tAVWL 30 Output Enable Time from CE ten CE tELQNZ 5 Output Enab...

Page 31: ...ation register are allowed Table 4 4 Attribute Memory Write Timing Speed Version 250 ns Item Symbol IEEE Symbol Min ns Max ns Write Cycle Time tc W tAVAV 250 Write Pulse Width tw WE tWLWH 150 Address Setup Time tsu A tAVWL 30 Write Recovery Time trec WE tWMAX 30 Data Setup Time for WE tsu D WEH tDVWH 80 Data Hold Time th D tWMDX 30 An WE CE Din tc W tsu D WEH tsu A th D trec WE tw WE Data In Valid...

Page 32: ...h CE tGHEH 20 Wait Delay Falling from OE tv WT OE tGLWTV 35 Data Setup for Wait Release tv WT tQVWTH 0 Wait Width Time Default Speed tw WT tWTLWTH 350 An REG Dout tsu A CE OE tsu CE WAIT tdis OE tw WT tv WT OE tv WT ta OE th A th CE Figure 4 3 Common Memory Read Timing Diagram Notes The maximum load on WAIT is 1 LSTTL with 50pF total load All times are in nanoseconds Dout signifies data provided b...

Page 33: ...te Recovery Time trec WE tWMAX 30 CE Hold following WE th CE tGHEH 20 Wait Delay Falling from WE tv WT WE tWLWTV 35 WE High from Wait Release tv WT tWTHWH 0 Wait Width Time Default Speed tw WT tWTLWTH 350 Figure 4 4 Common Memory Write Timing Diagram Notes The maximum load on WAIT is 1 LSTTL with 50pF total load All times are in nanoseconds Din signifies data provided by the system to the SDP3B Fl...

Page 34: ...ORD tRGLIGL 5 REG Hold following IORD thREG IORD tlGHRGH 0 INPACK Delay Falling from IORD tdfINPACK IORD tlGLIAL 0 45 INPACK Delay Rising from IORD tdrINPACK IORD tlGHIAH 45 IOIS16 Delay Falling from Address tdfIOIS16 ADR tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 ADR tAVISH 35 Wait Delay Falling from IORD tdWT IORD tlGLWTL 35 Data Delay from Wait Rising td WT tWTHQV 0 Wait Width Time De...

Page 35: ...OWR tlWHEH 20 REG Setup before IOWR tsuREG IOWR tRGLIWL 5 REG Hold following IOWR thREG IOWR tlWHRGH 0 IOIS16 Delay Falling from Address tdfIOIS16 ADR tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 ADR tAVISH 35 Wait Delay Falling from IOWR tdWT IOWR tlWLWTL 35 IOWR high from Wait high tdrIOWR WT tWTJIWH 0 Wait Width Time Default Speed Set Feature Speed 68 mA tw WT tWTLWTH 350 700 Figure 4 6...

Page 36: ...e IORD tsuA IORD tAVIGL 70 Address Hold following IORD thA IORD tlGHAX 20 CE Setup before IORD tsuCE IORD tELIGL 5 CE Hold following IORD thCE IORD tlGHEH 20 IOIS16 Delay Falling from Address tdfIOIS16 ADR tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 ADR tAVISH 35 Figure 4 7 True IDE Mode I O Read Timing Diagram Notes The maximum load on IOIS16 is 1 LSTTL with 50pF total load All times are...

Page 37: ...fore IOWR tsuA IOWR tAVIWL 70 Address Hold following IOWR thA IOWR tlWHAX 20 CE Setup before IOWR tsuCE IOWR tELIWL 5 CE Hold following IOWR thCE IOWR tlWHEH 20 IOIS16 Delay Falling from Address tdfIOIS16 ADR tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 ADR tAVISH 35 Figure 4 8 True IDE Mode I O Write Timing Diagram Notes The maximum load on IOIS16 is 1 LSTTL with 50pF total load All times...

Page 38: ...Memory Write 8 Bit D7 D0 0 1 1 1 0 X X XX X X X X Common Memory Write 8 Bit D15 D8 0 0 1 1 0 X X XX X X X 0 Common Memory Write 16 Bit D15 D0 X 0 0 0 1 0 0 XX X X X 0 Card Information Structure Read 1 0 0 1 0 0 0 XX X X X 0 Invalid Access CIS Write 1 0 0 0 1 X X XX X X X 1 Invalid Access Odd Attribute Read 1 0 0 1 0 X X XX X X X 1 Invalid Access Odd Attribute Write 0 1 0 0 1 X X XX X X X X Invalid...

Page 39: ...nal states and bus validity for the Attribute Memory function Table 4 12 Attribute Memory Function Function Mode REG CE2 CE1 A9 A0 OE WE D15 D8 D7 D0 Standby Mode X H H X X X X High Z High Z Read Byte Access CIS ROM 8 bits L H L L L L H High Z Even Byte Write Byte Access CIS 8 bits Invalid L H L L L H L Don t Care Even Byte Read Byte Access Configuration 8 bits L H L H L L H High Z Even Byte Write...

Page 40: ...nd hardware reset Using the PCMCIA Soft Reset is considered a hard Reset by the ATA Commands Contrast with Soft Reset in the Device Control Register LevlREQ This bit is set to one 1 when Level Mode Interrupt is selected and zero 0 when Pulse Mode is selected Set to zero 0 by Reset Conf5 Conf0 Configuration Index Set to zero 0 by reset It s used to select operation mode of the SDP3B FlashDisk as sh...

Page 41: ...he SDP3B FlashDisk automatically powers down when it is idle and powers back up when it receives a command Int This bit represents the internal state of the interrupt request This value is available whether or not I O interface has been configured This signal remains true until the condition which caused the interrupt request has been serviced If interrupts are disabled by the IEN bit in the Devic...

Page 42: ...This register contains additional configuration information This register is always written by the system before writing the card s Configuration Index Register Socket and Copy Register Organization Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Reserved 0 0 Drive 0 0 0 0 Write 0 0 0 Drive 0 X X X X Reserved This bit is reserved for future standardization This bit must be set to zero 0 by the software whe...

Page 43: ...S16 is asserted for all addresses to which the SDP3B FlashDisk responds The SDP3B FlashDisk may request the host to extend the length of an input cycle until data is ready by asserting the WAIT signal at the start of the cycle Table 4 15 I O Function Function Code REG CE2 CE1 A0 IORD IOWR D15 D8 D7 D0 Standby Mode X H H X X X High Z High Z Byte Input Access 8 bits L L H H L L L H L L H H High Z Hi...

Page 44: ...extend the length of a memory read cycle until data is ready by asserting the WAIT signal at the start of the cycle Table 4 16 Common Memory Function Function Code REG CE2 CE1 A0 OE WE D15 D8 D7 D0 Standby Mode X H H X X X High Z High Z Byte ReadAccess 8 bits H H H H L L L H L L H H High Z High Z Even Byte Odd Byte Byte Write Access 8 bits H H H H L L L H H H L L Don t Care Don t Care Even Byte Od...

Page 45: ...ote Removing and reinserting the SDP3B FlashDisk while the host computer s power is on will reconfigure the SDP3B FlashDisk to PC Card ATA mode from the original True IDE Mode To configure the SDP3B FlashDisk in True IDE Mode the 68 pin socket must be power cycled with the SDP3B FlashDisk inserted and OE output enable grounded by the host The following table defines the function of the operations ...

Page 46: ...P3B FlashDisk is done using the Task File registers which provide all the necessary registers for control and status information The PCMCIA interface connects peripherals to the host using four register mapping methods The following is a detailed description of these methods Table 5 1 I O Configurations Standard Configurations Config Index IO or Memory Address Drive Description 0 Memory 0 F 400 7F...

Page 47: ...nd 0 3F 37 0 1 1 0 Alt Status Device Control 0 3F 37 0 1 1 1 Drive Address Reserved Notes 1 Register 0 is accessed with CE1 low and CE2 low and A0 Don t Care as a word register on the combined Odd Data Bus and Even Data Bus D15 D0 This register may also be accessed by a pair of byte accesses to the offset 0 with CE1 low and CE2 high Note that the address space of this word register overlaps the ad...

Page 48: ...ow and CE2 high Note that the address space of this word register overlaps the address space of the Error and Feature byte wide registers that lie at offset 1 When accessed twice as byte register with CE1 low the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access A byte access to register 0 with CE1 high and CE2 low acc...

Page 49: ...d byte accessed is the odd byte of the equivalent word access A byte access to address 0 with CE1 high and CE2 low accesses the error read or feature write register 2 Registers at offset 8 9 and D are non overlapping duplicates of the registers at offset 0 and 1 Register 8 is equivalent to register 0 while register 9 accesses the odd byte Therefore if the registers are byte accessed in the order 9...

Page 50: ...Table 5 5 True IDE Mode I O Decoding CE2 CE1 A2 A1 A0 IORD 0 IOWR 0 Note 1 0 0 0 0 Even RD Data Even WR Data 1 0 0 0 1 Error Register Features 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector No Sector No 1 0 1 0 0 Cylinder Low Cylinder Low 1 0 1 0 1 Cylinder High Cylinder High 1 0 1 1 0 Select Card Head Select Card Head 1 0 1 1 1 Status Command 0 1 1 1 0 Alt Status Device Control 0 1 1 1 1 Dr...

Page 51: ...ter access and is provided to assist in understanding the overlapped Data Register and Error Feature Register rather than to attempt to define general PCMCIA word and byte access modes and operations See the PCMCIA PC Card Standard Release 2 0 for definitions of the Card Accessing Modes for I O and Memory cycles Note that because of the overlapped registers access to the 1F1 171 or offset 1 are no...

Page 52: ...ormation regarding features of the SDP3B FlashDisk that the host can utilize This register is also accessed on data bits D15 D8 during a write operation to Offset 0 with CE2 low and CE1 high 5 5 4 Sector Count Register Address 1F2 172 Offset 2 This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the SDP3B FlashDisk If th...

Page 53: ...ow Register D7 D0 LBA23 LBA16 Cylinder High Register D7 D0 LBA27 LBA24 Drive Head Register bits HS3 HS0 Bit 5 This bit is set to 1 Bit 4 DRV This bit will have the following meaning DRV is the drive number When DRV 0 drive card 0 is selected When DRV 1 drive card 1 is selected The SDP3B FlashDisk is set to be Card 0 or 1 using the copy field of the PCMCIA Socket Copy configuration register Bit 3 H...

Page 54: ... 2 CORR This bit is set when a Correctable data error has been encountered and the data has been corrected This condition does not terminate a multi sector read operation Bit 1 IDX This bit is always set to 0 Bit 0 ERR This bit is set when the previous command has ended in some type of error The bits in the Error register contain additional information describing the error 5 5 10 Device Control Re...

Page 55: ...ent a socket adapter which can be programmed to conditionally tri state D7 of I 0 address 3F7 377 when a SDP3B FlashDisk is installed and conversely to tri state D6 D0 of I O address 3F7 377 when a floppy controller is installed 4 Do not use the SDP3B FlashDisk s Drive Address register This may be accomplished by either a If possible program the host adapter to enable only I O addresses 1F0 1F7 3F...

Page 56: ...he SDP3B FlashDisk is not busy The BUSY bit in the status and alternate status registers is 0 Upon receipt of a Class 1 command the SDP3B FlashDisk sets the BUSY bit within 400 nsec Upon receipt of a Class 2 command the SDP3B FlashDisk sets the BUSY bit within 400 nsec sets up the sector buffer for a write operation sets DRQ within 700 µsec and clears the BUSY bit within 400 nsec of setting DRQ Up...

Page 57: ...h or 99h D 1 Stand By E2h or 96h D 1 Stand By Immediate E0h or 94h D 1 Translate Sector Note 1 87h Y Y Y Y Y 1 Wear Level Note 1 F5h Y 2 Write Buffer E8h D 2 Write Long Sector 32h or 33h Y Y Y Y 3 Write Multiple C5h Y Y Y Y Y 3 Write Multiple w o Erase 1 CDh Y Y Y Y Y 2 Write Sector s 30h or 31h Y Y Y Y Y 2 Write Sector s w o Erase 1 38h Y Y Y Y Y 2 Write Verify Sector s 3Ch Y Y Y Y Y Note 1 This ...

Page 58: ...shDisk sets BSY sets the Sector Count Register to 00h clears BSY and generates an interrupt If the SDP3B FlashDisk is in Idle mode the SDP3B FlashDisk sets BSY sets the Sector Count Register to FFh clears BSY and generates an interrupt 6 1 2 Execute Drive Diagnostic 90H Bit 7 6 5 4 3 2 1 0 Command 7 90H C D H 6 X Drive X Cyl High 5 X Cyl Low 4 X Sec Num 3 X Sec Cnt 2 X Feature 1 X This command per...

Page 59: ...1 Drive Head LBA 27 24 Cyl High 5 Cylinder High LBA 23 16 Cyl Low 4 Cylinder Low LBA 15 8 Sec Num 3 Sector Number LBA 7 0 Sec Cnt 2 Sector Count Feature 1 X This command is used to pre erase and condition data sectors in advance of a Write without Erase or Write Multiple without Erase command There is no data transfer associated with this command but since an implied write ID header operation is p...

Page 60: ...ommand with the same protocol as the Write Sector s command although the information in the buffer is not used by the SDP3B FlashDisk If LBA 1 then the number of sectors to format is taken from the Sec Cnt register 0 256 6 1 5 Identify Drive ECH Bit 7 6 5 4 3 2 1 0 Command 7 ECH C D H 6 X X X Drive X Cyl High 5 X Cyl Low 4 X Sec Num 3 X Sec Cnt 2 X Feature 1 X The Identify Drive command enables th...

Page 61: ...passed on Read Write Long Commands 23 26 aaaa 8 Firmware revision in ASCII Rev M ms set by code Big Endian Byte Order in Word 27 46 aaaa 40 Model number in ASCII Left Justified Big Endian Byte Order in Word 47 0001H 2 Maximum of 1 sector on Read Write Multiple command 48 0000H 2 Double Word not supported 49 0200H 2 Capabilities DMA NOT Supported bit 8 LBA supported bit 9 50 0000H 2 Reserved 51 010...

Page 62: ... number of sectors per SDP3B FlashDisk This double word value is also the first invalid address in LBA translation mode 6 1 5 8 Memory Card Serial Number The contents of this field are right justified and padded with spaces 20h 6 1 5 9 Buffer Type This field defines the buffer capability with the 0002h meaning a dual ported multi sector buffer capable of simultaneous data transfers to or from the ...

Page 63: ...e 6 1 5 21 Current Capacity This field contains the product of the current cylinders times heads times sectors 6 1 5 22 Multiple Sector Setting This field contains a validity flag in the odd byte and the current number of sectors that can be transferred per interrupt for R W Multiple in the even byte The odd byte is always 01H which indicates that the even byte is always valid The even byte value ...

Page 64: ... an interrupt If the sector count is non zero it is interpreted as a timer count with each count being 5 milliseconds and the automatic power down mode is enabled If the sector count is zero the automatic power down mode is disabled Note that this time base 5 msec is different from the ATA specification 6 1 7 Idle Immediate 95H E1H Bit 7 6 5 4 3 2 1 0 Command 7 E1H or 95H C D H 6 X Drive X Cyl Hig...

Page 65: ...mmand Note SanDisk recommends NOT using this command in any system because DOS determines the offset to the Boot Record based on the number of heads and sectors per track If a SDP3B FlashDisk is Formatted with one head and sector per track value the same SDP3B FlashDisk will not operate correctly with DOS configured with another heads and sectors per track value 6 1 9 Read Buffer E4H Bit 7 6 5 4 3...

Page 66: ...number of requested sectors is not evenly divisible by the block count as many full blocks as possible are transferred followed by a final partial block transfer The partial block transfer is for n sectors where n sector count modulo block count If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled the Read Mult...

Page 67: ...the Read Sector s command 6 1 12 Read Sector s 20H 21H Bit 7 6 5 4 3 2 1 0 Command 7 20H 21H C D H 6 1 LBA 1 Drive Head LBA 27 24 Cyl High 5 Cylinder High LBA 23 16 Cyl Low 4 Cylinder Low LBA 15 8 Sec Num 3 Sector Number LBA 7 0 Sec Cnt 2 Sector Count Feature 1 X This command reads from 1 to 256 sectors as specified in the Sector Count register A sector count of 0 requests 256 sectors The transfer...

Page 68: ... completion the Command Block Registers contain the cylinder head and sector number of the last sector verified If an error occurs the verify terminates at the sector where the error occurs The Command Block Registers contain the cylinder head and sector number of the sector where the error occurred The Sector Count Register contains the number of sectors not yet verified 6 1 14 Recalibrate 1XH Bi...

Page 69: ...s command must be the next command issued to the SDP3B FlashDisk following the command which returned an error Table 6 4 Extended Error Codes Extended Error Code Description 00h No Error Detected 01h Self Test OK No Error 09h Miscellaneous Error 20h Invalid Command 21h Invalid Address Requested Head or Sector Invalid 2Fh Address Overflow Address Too Large 35h 36h Supply or generated Voltage Out of...

Page 70: ...mmand to the SDP3B FlashDisk although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range 6 1 17 Set Features EFH Bit 7 6 5 4 3 2 1 0 Command 7 EFH C D H 6 X Drive X Cyl High 5 X Cyl Low 4 X Sec Num 3 X Sec Cnt 2 Config Feature 1 Feature This command is used by the host to establish or select certain features Table 6 5 defines all f...

Page 71: ...he current the SDP3B FlashDisk draws the host issues the Set Features command with the Feature register set to 9AH and the Sector Count register Config set to a current value which is equal to 4 mA times the value in the Sector Count register When this is done the controller will utilize a look up table to program the controller s frequency microprocessor s speed and flash clocks with an optimum v...

Page 72: ...n of those commands is enabled If a block count is not supported an Aborted Command error is posted and Read Multiple and Write Multiple commands are disabled If the Sector Count Register contains 0 when the command is issued Read and Write Multiple commands are disabled At power on or after a hardware or unless disabled by a Set Feature command software reset the default mode is Read and Write Mu...

Page 73: ...lear BSY and return the interrupt immediately Recovery from sleep mode is accomplished by simply issuing another command a reset is not required 6 1 21 Standby Immediate 94H E0H Bit 7 6 5 4 3 2 1 0 Command 7 E0H or 94H C D H 6 X Drive X Cyl High 5 X Cyl Low 4 X Sec Num 3 X Sec Cnt 2 X Feature 1 X This command causes the SDP3B FlashDisk to set BSY enter the Sleep mode which corresponds to the ATA S...

Page 74: ... sector has been erased and programmed The controller responds with a 512 byte buffer of information on the desired cylinder head and sector with the actual Logical Address along with the Hot Count for that sector Table 6 6 represents the information in the buffer Please note that this command is unique to the SanDisk SDP3B FlashDisk Table 6 6 Translate Sector Information Address Information 00h 0...

Page 75: ...r backward compatability with earlier SanDisk SDP series products The Sector Count Register will always be returned with an 00H indicating Wear Level is not needed 6 1 24 Write Buffer E8H Bit 7 6 5 4 3 2 1 0 Command 7 E8H C D H 6 X Drive X Cyl High 5 X Cyl Low 4 X Sec Num 3 X Sec Cnt 2 X Feature 1 X The Write Buffer command enables the host to overwrite contents of the SDP3B FlashDisk s sector buf...

Page 76: ...tor with valid ECC fields This command has the same protocol as the Write Sector s command 6 1 26 Write Multiple Command C5H Bit 7 6 5 4 3 2 1 0 Command 7 C5H C D H 6 X LBA X Drive Head Cyl High 5 Cylinder High Cyl Low 4 Cylinder Low Sec Num 3 Sector Number Sec Cnt 2 Sector Count Feature 1 X Note The current revision of the SDP3B FlashDisk only supports a block count of 1 as indicated in the Ident...

Page 77: ... in error even if it is in the middle of a block Subsequent blocks are not transferred in the event of an error Interrupts are generated when DRQ is set at the beginning of each block or partial block The Command Block Registers contain the cylinder head and sector number of the sector where the error occurred and the Sector Count Register contains the residual number of sectors that need to be tr...

Page 78: ...ated When the final sector of data is transferred BSY is set and DRQ is cleared It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated If an error occurs during a write of more than one sector writing terminates at the sector where the error occurs The Command Block Registers contain the cylinder head and sector number of the sector w...

Page 79: ...he transfer begins at the sector specified in the Sector Number Register When this command is accepted the SDP3B FlashDisk sets BSY then sets DRQ and clears BSY then waits for the host to fill the sector buffer with the data to be written No interrupt is generated to start the first buffer fill operation No data should be transferred by the host until BSY has been cleared by the host For multiple ...

Page 80: ...3B FlashDisk Product Manual SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 80 6 2 Error Posting The following table summarizes the valid status and error value for all the ATA Command set ...

Page 81: ... V V V V V V V Read Long Sector V V V V V V V V Read Sector s V V V V V V V V V V Read Verify Sectors V V V V V V V V V V Recalibrate V V V V V Request Sense V V V V Seek V V V V V V Set Features V V V V V Set Multiple Mode V V V V V Set Sleep Mode V V V V V Stand By V V V V V Stand By Immediate V V V V V Translate Sector V V V V V V V V Wear Level V V V V V V V V V Write Buffer V V V V V Write Lo...

Page 82: ...SDP3B FlashDisk Product Manual SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 82 ...

Page 83: ...SDP3B FlashDisk Product Manual SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 83 7 0 CIS Description This section describes the Card Information Structure CIS for the SDP3B FlashDisk ...

Page 84: ...peed 01h 250ns ec I O Device No WPS Speed is 250 nsec with Wait Device ID WPS Speed 014h 01h 1x 2K units 2Kilobytes of Address Space Device Size 016h FFh List End Marker End of Devices End Marker 018h 18h CISTPL_JEDEC_C JEDEC ID Common Mem Tuple Code 01Ah 02h Link is 2 bytes Link Length 01Ch DFh PCMCIA JEDEC Manufacturer s ID First Byte of JEDEC ID for SanDisk PC Card ATA 12V Byte 1 JEDEC ID of De...

Page 85: ...INOR PCMCIA 2 0 JEIDA 4 1 Minor Version 034h 53h ASCII Manufacturer String S String 1 036h 75h u 038h 6Eh n 03Ah 44h D 03Ch 69h i 03Eh 73h s 040h 6Bh k 042h 00h End of Manufacturer String Null terminator 044h 53h ASCII Product Name String S Info String 2 046h 44h D 048h 50h P 04Ah 00h End of Product Name String Null terminator 04Ch 35h 5 Info String 3 04Eh 2Fh 050h 33h 3 052h 20h 054h 30h SanDisk ...

Page 86: ...es limited by link length 064h 08h R 0 R 0 R 0 R 0 E 1 T P R 0 T A R 0 R8 0 R8 8 bit ROM present TAR Temp Bsy on AT Reset TPR Temp Bsy on PCMCIA Reset E Erase Ahead Available R Reserved 0 for now This definition applies only to card with Manufacturer s ID tuple 1st 3 bytes 45 00 01 SanDisk Fields 1 to 4 bytes limited by link length 066h 00h For Specific platform use Only 068h 21h CISTPL_FUNCID Fun...

Page 87: ...p Mode Supported P1 Standby Mode Supported P2 Idle Mode Supported P3 Drive Auto Power Control N Some Config Excludes 3X7 E Index Bit is Emulated I Twin IOis16 Data Reg Only Extended ATA Option Parameters 082h 1Ah CISTPL_CONF Configuration Tuple Tuple Code 084h 05h Link Length is 5 bytes Link to next tuple 086h 01h RFS 00 RMS 00 RAS 01 Size of Reserved Field is 0 bytes Size of Register Mask is 1 By...

Page 88: ... Ready Busy and Wait for memory cycles active B Battery Volt Detects Used P Write Protect Used R Ready Busy Used W Wait Used for Memory Cycles TPCE_IF 098h A1h M 1 MS 1 IR 0 IO 0 T 0 P 1 Vcc only Power No Timing I O or IRQ 2 Byte Mem Space Length Misc Entry Present P Power info type T Timing info present IO I O port info present IR Interrupt info present MS Mem space info type M Misc info byte s p...

Page 89: ...Power Down Supported R Reserved X More Misc Fields Bytes TPCE_MI 0AAh 1Bh CISTPL_CE Configuration Entry Tuple Tuple Code 0ACh 06h Link to next tuple is 6 bytes Also limits size of this tuple to 8 bytes Link to next tuple 0AEh 00h I 0 D 0 Configuration Index 0 Memory mapped I O 3 3V configuration TPCE_INDX 0B0h 01h M 0 MS 0 IR 0 IO 0 T 0 P 1 P Power info type TPCE_FS 0B2h 21h R 0 DI 0 PI 1 AI 0 SI ...

Page 90: ...dy Busy active but Wait not used for memory cycles B Battery Volt Detects Used P Write Protect Used R Ready Busy Used W Wait Used for Memory Cycles TPCE_IF 0C2h 99h M 1 MS 0 IR 1 IO 1 T 0 P 1 Vcc Only Power Descriptors No Timing I O and IRQ present No Mem Space Misc Entry Present P Power info type T Timing info present IO I O port info present IR Interrupt info present MS Mem space info type M Mis...

Page 91: ... 1 P 1 L 1 M 1 V 0 B 0 I 0 N 0 IRQ Sharing Logic Active in Card Control Status Register Pulse and Level Mode Interrupts supported Recommended IRQ s any of 0 through 15 F S Share Logic Active P Pulse Mode IRQ Supported L Level Mode IRQ Supported M Bit Mask of IRQs Present V Vendor Unique IRQ B Bus Error IRQ I IO Check IRQ N Non Maskable IRQ TPCE_IR 0D2h FFh 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 IRQ Level...

Page 92: ...ent 5h 1 Nominal Operation Supply Voltage 3 0V Nominal Operation Supply Voltage 0E4h 1Eh X 0 1Eh 30 Nominal Operation Supply Voltage Extension Byte 0E6h 4Dh X 0 Mantissa 9h 4 5 Exponent 5h 10 Max Average Current over 10 msec is 45 mA Max Average Current 0E8h 1Bh CISTPL_CE Configuration Entry Tuple Tuple Code 0EAh 12h Link to next tuple is 18 bytes Also limits size of this tuple to 20 bytes Link to...

Page 93: ...tage SI Static Current AI Average Current PI Peak Current DI Power Down Current Power Parameters for Vcc 0F4h 55h X 0 Mantissa Ah 5 0 Exponent 5h 1V Vcc Nominal is 5Volts Vcc Nominal Value 0F6h 4Dh X 0 Mantissa 9h 4 5 Exponent 5h 1V Vcc Nominal is 4 5Volts Vcc Minimum Value 0F8h 5Dh X 0 Mantissa Bh 5 5 Exponent 5h 1V Vcc Nominal is 5 5Volts Vcc Maximum Value 0FAh 75h X 0 Mantissa Eh 8 0 Exponent 5...

Page 94: ...102h 01h 1st I O Base Address msb 1F0h 104h 07h 1st I O Range Length 1 8 bytes total 1F0 1F7h I O Length 1 106h F6h 2nd I O Base Address lsb 2nd I O Range base is 108h 03h 2nd I O Base Address msb 3F6h 10Ah 01h 2nd I O Range Length 1 2 bytes total 3F6 3F7h I O Length 1 10Ch EEh S 1 P 1 L 1 M 0 Recommend IRQ Level Eh 14 IRQ Sharing Logic Active in Card Control Status Register Pulse and Level Mode I...

Page 95: ...onfiguration Index 2 AT Fixed Disk Primary I O 3 3V configuration TPCE_INDX 116h 01h M 0 MS 0 IR 0 IO 0 T 0 P 1 P Power info type TPCE_FS 118h 21h R 0 DI 0 PI 1 AI 0 SI 0 HV 0 LV 0 NV 1 PI Peak Current NV Nominal Operation Supply Voltage Power Parameters for Vcc 11Ah B5h X 1 Mantissa 6h 3 0 Exponent 5h 1 Nominal Operation Supply Voltage 3 0V Nominal Operation Supply Voltage 11Ch 1Eh X 0 1Eh 30 Nom...

Page 96: ...ady Busy Used W Wait Used for Memory Cycles TPCE_IF 128h 99h M 1 MS 0 IR 1 IO 1 T 0 P 1 Vcc Only Power Descriptors No Timing I O and IRQ present No Mem Space Misc Entry Present P Power info type T Timing info present IO I O port info present IR Interrupt info present MS Mem space info type M Misc info byte s present TPCE_FS 12Ah 27h R 0 DI 0 PI 1 AI 0 SI 0 HV 1 LV 1 NV 1 Nominal Voltage Follows NV...

Page 97: ... 2 2Byte 16 bit Addresses 3 4Byte 32 bit Addresses LS Size of length 0 No Lengths Present 1 1Byte 8 bit Lengths 2 2Byte 16 bit Lengths 3 4Byte 32 bit Lengths I O Range Format Description 138h 70h 1st I O Base Address lsb First I O Range base is 13Ah 01h 1st I O Base Address msb 170h 13Ch 07h 1st I O Range Length 1 8 bytes total 170 177h I O Length 1 13Eh 76h 2nd I O Base Address lsb 2nd I O Range ...

Page 98: ... HV 0 LV 0 NV 1 PI Peak Current NV Nominal Operation Supply Voltage Power Parameters for Vcc 152h B5h X 1 Mantissa 6h 3 0 Exponent 5h 1 Nominal Operation Supply Voltage 3 0V Nominal Operation Supply Voltage 154h 1Eh X 0 1Eh 30 Nominal Operation Supply Voltage Extension Byte 156h 4Dh X 0 Mantissa 9h 4 5 Exponent 5h 10 Max Average Current over 10 msec is 45mA Max Average Current 158h 1Bh CISTPL_CE C...

Page 99: ...SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 99 Ordering Information and Technical Support ...

Page 100: ...SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 100 ...

Page 101: ...ard S1 With Protective Sleeve SanDisk FlashDisk Evaluation Kit The SanDisk SDP3B FlashDisk Series is a solid state mass storage system that is fully compatible with the PCMCIA ATA protocol for mass storage on a memory card SanDisk SDP3B FlashDisks support both PCMCIA Rev 2 1 and PCMCIA Rev 1 0 standards The FlashDisk Evaluation Kit Model SDPEV 1 permits designers to quickly and easily evaluate the...

Page 102: ...Board The SanDisk IDE AB 6 FlashDisk Adapter Board enables a CompactFlash with adapter Type II or Type III FlashDisk to be installed in a portable computer s 2 5 inch drive bay allowing users to replace a 2 5 inch rotating IDE disk drive with the SanDisk FlashDisk To order this adapter board use the following model number Model IDE AB 6 ...

Page 103: ...for technical support SanDisk Worldwide Web Site Internet users can obtain technical support and product information along with SanDisk news and much more from the SanDisk Worldwide Web Site 24 hours a day seven days a week The SanDisk Worldwide Web Site is frequently updated Visit this site often to obtain the most up to date information on SanDisk products and applications The SanDisk Web Site U...

Page 104: ... the SanDisk FlashDisk These reader writers can be installed in desktop PCs to enable the SDP3B FlashDisk to be used in those systems The SDP3B FlashDisk will operate in any of these reader writers Vendor Country Telephone FAX Number Product Model Product Type Adtron United States 602 926 9324 FAX 602 926 9359 http www adtron com SDDA SDDB SDDC SDDL SDDM SDDP SDDR SDDS Adapter for direct IDE mode ...

Page 105: ...upports Windows NT Windows 95 Windows 3 11 and MS DOS Single slot Type III external unit that connects to Centronics EPP port with professional software for binary data access ISA adapter with cable to dual slot one Type III and one Type II in a 3 5 inch frame ISA adapter with one slot Type III on card and cable to single slot Type III in a 3 5 inch frame ISA adapter with one slot Type III on card...

Page 106: ...Ordering Information and Technical Support SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 106 ...

Page 107: ...SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 107 SanDisk Sales Offices ...

Page 108: ...SanDisk Worldwide Sales Offices SanDisk SDP3B FlashDisk Product Manual 1998 SANDISK CORPORATION 108 ...

Page 109: ...481 9828 FAX 703 437 9215 Southern Region USA 407 667 4880 FAX 407 667 4834 Latin South America 407 667 4880 FAX 407 667 4834 Europe SanDisk Corporation Karlsruher Str 2C D 30519 Hannover Germany 011 49 511 8759185 FAX 011 49 511 8759187 Southern Europe SanDisk Corporation 4 rue de l abreuvoir 92415 Courbevoie Cedex France 011 33 1 4717 6510 FAX 011 33 1 4717 6531 Japan SanDisk K K 8F Nisso Bldg 1...

Page 110: ...ective within one year of purchase SanDisk will have the option of repairing or replacing the defective product if the following conditions are met A A warranty registration card for each defective product was submitted and is on file at SanDisk If not a warranty registration card must accompany each returned defective product This card is included in each product s original retail package B The d...

Page 111: ...ed SanDisk will issue a Return Material Authorization or Product Repair Authorization number Ship the defective product to SanDisk Corporation Attn RMA Returns Reference RMA or PRA 140 Caspian Court Sunnyvale CA 94089 V STATE LAW RIGHTS SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES OR LIMITATION ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITA...

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