SDP3B FlashDisk Product Manual
SanDisk SDP3B FlashDisk Product Manual © 1998 SANDISK CORPORATION
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6.0 ATA Command Description
This section defines the software requirements and
the format of the commands the host sends to the
SDP3B FlashDisks. Commands are issued to the
SDP3B FlashDisk by loading the required
registers in the command block with the supplied
parameters, and then writing the command code to
the Command Register. The manner in which a
command is accepted varies. There are three
classes (see Table 6-1) of command acceptance, all
dependent on the host not issuing commands unless
the SDP3B FlashDisk is not busy. (The BUSY bit
in the status and alternate status registers is 0.)
•
Upon receipt of a Class 1 command, the
SDP3B FlashDisk sets the BUSY bit within
400 nsec.
•
Upon receipt of a Class 2 command, the
SDP3B FlashDisk sets the BUSY bit within
400 nsec, sets up the sector buffer for a write
operation, sets DRQ within 700 µsec, and
clears the BUSY bit within 400 nsec of setting
DRQ.
•
Upon receipt of a Class 3 command, the
SDP3B FlashDisk sets the BUSY bit within
400 nsec, sets up the sector buffer for a write
operation, sets DRQ within 20 msec (assuming
no re-assignments), and clears the BUSY bit
within 400 nsec of setting DRQ.
6.1
ATA Command Set
Table 6-1 summarizes the ATA command set with
the paragraphs that follow describing the
individual commands and the task file for each.
