SDP3B FlashDisk Product Manual
SanDisk SDP3B FlashDisk Product Manual © 1998 SANDISK CORPORATION
47
5.1
I/O Primary and Secondary
Address Configurations
Table 5-2 Primary and Secondary I/O Decoding
- R E G
A9-A4
A3
A2
A1
A0
- I O R D = 0
- I O W R = 0
Note
0
1F(17)
0
0
0
0
Even RD Data
Even WR Data
1, 2
0
1F(17)
0
0
0
1
Error Register
Features
1
0
1F(17)
0
0
1
0
Sector Count
Sector Count
0
1F(17)
0
0
1
1
Sector No.
Sector No.
0
1F(17)
0
1
0
0
Cylinder Low
Cylinder Low
0
1F(17)
0
1
0
1
Cylinder High
Cylinder High
0
1F(17)
0
1
1
0
Select Card/Head
Select Card/Head
0
1F(17)
0
1
1
1
Status
Command
0
3F(37)
0
1
1
0
Alt Status
Device Control
0
3F(37)
0
1
1
1
Drive Address
Reserved
Notes:
1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don't Care) as a word register on the
combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte
accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register
overlaps the address space of the Error and Feature byte-wide registers which lie at offset 1. When
accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and
the second byte accessed is the odd byte of the equivalent word access.
2. A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write)
register.
