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TIMER 1

S3C80A5B

11-4

TIMER 1 CONTROL REGISTER (T1CON)

The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains
control settings for the following T1 functions:

— Timer 1 input clock selection

— Timer 1 operating mode selection

— Timer 1 16-bit down counter clear

— Timer 1 overflow interrupt enable/disable

— Timer 1 match interrupt enable/disable

— Timer 1 interrupt pending control (read for status, write to clear)

A reset operation clears T1CON to ‘00H’, selecting f

OSC

divided by 4 as the T1 clock, configuring timer 1 as a

normal interval timer, and disabling the timer 1 interrupts.

Timer 1 Control Register (T1CON)

FAH, R/W

.7

.6

.5

.4

.3

.2

.1

.0

MSB

LSB

Timer 1 counter clear bit:
0 = No effect
1 = Clear the timer 1 counter (when write)

Timer 1 input clock selection bits:
00 = f

OSC

/4

01 = f

OSC

/8

10 = f

OSC

/16

11 = Internal clock (T-F/F)

Timer 1 operating mode selection bits:
00 = Interval mode
01 = Overflow mode (OVF interrupt can occur)
01 = Overflow mode (OVF interrupt can occur)
01 = Overflow mode (OVF interrupt can occur)

Timer 1 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt

Timer 1 match interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt

Timer 1 match interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (write)
1 = Interrupt is pending

Figure 11-3. Timer 1 Control Register (T1CON)

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Summary of Contents for S3C80A5B

Page 1: ...RATA This document contains the corrections of errors typos and omissions in the following document Samsung 8 bit CMOS S3C80A5B Microprocessor User s Manual Document Number 21 1 S3 C80A5B 082005 Publication August 2005 ...

Page 2: ...Electrical Characteristics PAGE13 2 TA 25 C to 85 C VDD 2 0 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Operating voltage VDD fOSC 8 MHz Instruction clock 1 33 MHz 2 0 5 5 V 3 Table 13 2 D C Electrical Characteristics PAGE13 2 Parameter Symbol Conditions Min Typ Max Unit VOH1 VDD 2 4 V IOH 6 mA Port 2 1 only VDD 0 7 VOH2 VDD 2 4 V IOH 2 2mA Port 2 0 2 2 VDD 0 7 V Output high voltage VO...

Page 3: ... 1 0 4 1 0 V Supply current note IDD1 VDD 5 5 V 8 MHz crystal 5 9 mA IDD2 Idle mode VDD 5 5 V 8 MHz crystal 2 4 mA IDD3 Stop mode TA 25 C VDD 5 5V 1 6 UA NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads 5 Table 13 4 Data Retention Supply Voltage in Stop Mode PAGE13 4 Parameter Symbol Conditions Min Typ Max Unit Data retention su...

Page 4: ...e of S3C80A5 PAGE13 6 1 33 MHz 250 kHz 8 32 kHz 1 2 3 4 5 6 7 Supply Voltage V Instruction Clock 1 6n x oscillator frequency n 1 2 8 16 1 00 MHz 500 kHz 670 kHz Instruction Clock 8 MHz 6 MHz 4 MHz Instruction Clock 400 kHz Figure 13 2 Operating Voltage Range of S3C80A5B ...

Page 5: ...S3C80A5B 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 1 ...

Page 6: ...ions intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmle...

Page 7: ...describes the S3C80A5B interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each ...

Page 8: ...5 Register Set 1 2 6 Register Set 2 2 6 Prime Register Space 2 7 Working Registers 2 8 Using the Register Pointers 2 9 Register Addressing 2 11 Common Working Register Area C0H CFH 2 13 4 Bit Working Register Addressing 2 14 8 Bit Working Register Addressing 2 16 System and User Stacks 2 18 Chapter 3 Addressing Modes Overview 3 1 Register Addressing Mode R 3 2 Indirect Register Addressing Mode IR ...

Page 9: ...tem Mode Register SYM 5 10 Interrupt Mask Register IMR 5 11 Interrupt Priority Register IPR 5 12 Interrupt Request Register IRQ 5 14 Interrupt Pending Function Types 5 15 Interrupt Source Polling Sequence 5 16 Interrupt Service Routines 5 16 Generating interrupt Vector Addresses 5 17 Nesting of Vectored Interrupts 5 17 Instruction Pointer IP 5 17 Fast Interrupt Processing 5 17 Chapter 6 Instructio...

Page 10: ...e Reset Values 8 4 Power Down Modes 8 6 Stop Mode 8 6 Using POR to Release Stop Mode 8 6 Using an INTR to Release Stop Mode 8 6 Idle Mode 8 9 Summary Table of Stop Mode and Idle Mode 8 10 Chapter 9 I O Ports Overview 9 1 Port Data Registers 9 2 Pull Up Resistor Enable Registers 9 2 Port 0 9 3 Port 0 Interrupt Enable Register P0INT 9 4 Port 0 Interrupt Pending Register P0PND 9 4 Port 1 9 6 Port 2 9...

Page 11: ... Timer 1 Overflow Interrupt 11 2 Timer 1 Match Interrupt 11 2 Timer 1 Control Register T1CON 11 4 Chapter 12 Counter A Overview 12 1 Counter A Control Register CACON 12 3 Counter A Pulse Width Calculations 12 4 Chapter 13 Electrical Data Overview 13 1 Chapter 14 Mechanical Data Overview 14 1 ...

Page 12: ...13 2 11 4 Bit Working Register Addressing 2 15 2 12 4 Bit Working Register Addressing Example 2 15 2 13 8 Bit Working Register Addressing 2 16 2 14 8 Bit Working Register Addressing Example 2 17 2 15 Stack Operations 2 18 3 1 Register Addressing 3 2 3 2 Working Register Addressing 3 2 3 3 Indirect Register Addressing to Register File 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 I...

Page 13: ...s Register FLAGS 6 6 7 3 System Clock Circuit Diagram 7 2 7 4 System Clock Control Register CLKCON 7 3 8 1 Reset Block Diagram 8 1 8 2 Power on Reset Circuit 8 2 8 3 Timing Diagram for Power on Reset Circuit 8 3 9 1 S3C80A5B I O Port Data Register Format 9 2 9 2 Port 0 High Byte Control Register P0CONH 9 3 9 3 Port 0 Low Byte Control Register P0CONL 9 4 9 4 Port 0 External Interrupt Control Regist...

Page 14: ...agram Interval Timer Mode 11 2 11 2 Timer 1 Block Diagram 11 3 11 3 Timer 1 Control Register T1CON 11 4 11 4 Timer 1 Registers 11 5 12 1 Counter A Block Diagram 12 2 12 2 Counter A Control Register CACON 12 3 12 3 Counter A Registers 12 4 12 4 Counter A Output Flip Flop Waveforms in Repeat Mode 12 5 13 1 Input Timing for External Interrupts Port 0 13 5 13 2 Operating Voltage Range of S3C80A5B 13 6...

Page 15: ...ls 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Opcode Quick Reference 6 10 6 6 Condition Codes 6 12 8 1 Set 1 Register Values After Reset 8 4 8 2 Summary of Each Mode 8 10 9 1 S3C80A5B Port Configuration Overview 9 1 9 2 Port Data Register Summary 9 2 13 1 Absolute Maximum Ratings 13 2 13 2 D C Electrical Characteristics 13 2 13 3 Characteristics of Low Voltage Detect Circuit 13 4 13 4 Data R...

Page 16: ...rs 2 10 Addressing the Common Working Register Area 2 14 Standard Stack Operations Using PUSH and POP 2 19 Chapter 8 RESET and Power Down To Divide STOP Mode Releasing and POR 8 7 Chapter 10 Basic Timer and Timer 0 Configuring the Basic Timer 10 8 Programming Timer 0 10 9 Chapter 12 Counter A To Generate 38 kHz 1 3duty Signal Through P2 1 12 6 To Generate a One Pulse Signal Through P2 1 12 7 ...

Page 17: ...ister 4 13 P0CONH Port 0 Control Register High Byte 4 14 P0CONL Port 0 Control Register Low Byte 4 15 P0INT Port 0 Interrupt Control Register 4 16 P0PND Port 0 Interrupt Pending Register 4 17 P0PUR Port 0 Pull up Resistor Enable Register 4 18 P1CONH Port 1 Control Register High Byte 4 19 P1CONL Port 1 Control Register Low Byte 4 20 P1PUR Port 1 Pull up Resistor Enable Register 4 21 P2CON Port 2 Co...

Page 18: ...6 25 CALL Call Procedure 6 26 CCF Complement Carry Flag 6 27 CLR Clear 6 28 COM Complement 6 29 CP Compare 6 30 CPIJE Compare Increment and Jump on Equal 6 31 CPIJNE Compare Increment and Jump on Non Equal 6 32 DA Decimal Adjust 6 33 DEC Decrement 6 35 DECW Decrement Word 6 36 DI Disable Interrupts 6 37 DIV Divide Unsigned 6 38 DJNZ Decrement and Jump if Non Zero 6 39 EI Enable Interrupts 6 40 ENT...

Page 19: ...k Decrementing 6 64 POPUI Pop User Stack Incrementing 6 65 PUSH Push to Stack 6 66 PUSHUD Push User Stack Decrementing 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Carry Flag 6 69 RET Return 6 70 RL Rotate Left 6 71 RLC Rotate Left through Carry 6 72 RR Rotate Right 6 73 RRC Rotate Right through Carry 6 74 SB0 Select Bank 0 6 75 SB1 Select Bank 1 6 76 SBC Subtract with Carry 6 77 SCF Se...

Page 20: ...r is fabricated using a highly advanced CMOS process and is based on Samsung s newest CPU architecture The S3C80A5B is the microcontroller which has mask programmable ROM Using a proven modular design approach Samsung engineers developed the S3C80A5B by integrating the following peripheral modules with the powerful SAM87 RC core Three programmable I O ports including two 8 bit ports and one 3 bit ...

Page 21: ...trol Counter A Back up mode When VDD is lower than VLVD the chip enters Back up mode to block oscillation and reduce the current consumption Timers and Timer Counters One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function One 8 bit timer counter Timer 0 with two operating modes Interval mode and PWM mode One 16 bit timer counter with one operating mo...

Page 22: ...INT4 P1 0 P1 7 Port I O and Interrupt Control SAM87RI CPU Internal Bus XIN XOUT Port 0 INTR Port 1 Main OSC P2 0 T0PWM 15 Kbyte ROM 256 Byte Register File 8 bit Timer Counter 16 bit Timer Counter Port 2 Carrier Generator Counter A P2 1 REM P2 2 LVD TEST Figure 1 1 Block Diagram ...

Page 23: ...NTR P0 3 INT3 INTR P0 4 INT4 INTR P0 5 INT4 INTR P0 6 INT4 INTR P0 7 INT4 INTR S3C80A5B 24 SOP SDIP TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 VDD P2 2 SCLK P2 1 REM SDAT P2 0 T0PWM T0CK P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 24 23 22 21 20 19 18 17 16 15 14 13 Figure 1 2 Pin Assignment Diagram 24 Pin SOP SDIP Package ...

Page 24: ... 12 INT0 INT4 INTR P1 0 P1 7 I O I O port with bit programmable pins Configurable to input mode or output mode Pin circuits are either push pull or n channel open drain type Pull up resistors are assignable by software 2 13 20 P2 0 P2 1 P2 2 I O 3 bit I O port with bit programmable pins Configurable to input mode push pull output mode or n channel open drain output mode Input mode with pull up res...

Page 25: ...nterrupt with reset INTR is assigned to port 0 of S3C80A5B It is designed to release stop status with reset When the falling rising edge is detected at any pin of Port 0 during stop status non vectored interrupt INTR signal occurs after then system reset occurs automatically It is designed for a application which are using stop mode like remote controller If stop mode is not used INTR do not opera...

Page 26: ...tor Output Disable Data VSS Noise filter Normal Input Open drain Figure 1 4 Pin Circuit Type 2 Port 1 VDD Pull up Enable VDD P2 0 T0PWN Pull up Resistor Typical 21KΩ Open drain Port 2 0 Data VSS M U X P2 0 Input Output Disable Data T0_PWN P2CON 0 Figure 1 5 Pin Circuit Type 3 P2 0 ...

Page 27: ...en Drain Port 2 1 Data VSS P2 1 Input M U X P2CON 1 Data Output Disable Noise filter T0CK CAOF CACON 0 Carrier On Off P2 5 Figure 1 6 Pin Circuit Type 4 P2 1 VDD Pull up Enable VDD In Out Pull up Resistor Typical 21 kΩ Open drain VSS Normal Input Output Disable Data Figure 1 7 Pin Circuit Type 5 P2 2 ...

Page 28: ... external memory interface is not implemented The 256 byte physical RAM space is expanded into an addressable area of 320 bytes by the use of addressing modes There are 312 mapped registers in the internal register file Of these 272 are for general purpose use This number includes a 16 byte working register common area that is used as a scratch area for data operations a 256 prime register area th...

Page 29: ... of the ROM 0H 0FFH are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you do use the vector address area to store program code be careful to avoid overwriting vector addresses stored in these locations The ROM address at which program execution starts after a reset is 0100H 15 872 15 Kbyte ROM Interrupt Vector Area 255 0 3E00...

Page 30: ...ration The extension of register space into separately addressable sets is supported internally by addressing mode restrictions Specific register types and the area in bytes they occupy in the S3C80A5B internal register space are summarized in Table 2 1 Table 2 1 S3C80A5B Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common working register are...

Page 31: ...ect Register or Indexed addressing modes or stack operations FFH C0H 192 Bytes FFH C0H System and Peripheral Control Registers Register Addressing Mode System Registers Register Addressing Mode 64 Bytes 256 Bytes Working Registers Working Register Addressing Mode CFH D0H DFH E0H Figure 2 2 Internal Register File Organization ...

Page 32: ...value lower nibble and destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing These page pointer PP register settings as shown in Figure 2 3 should not be modified during normal operation Register Page Pointer PP DFH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Dectination register page selection bits 0 0 0 0 Destination page 0...

Page 33: ...a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using the Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Section 3 Addressing Modes REGISTER SET 2 The same 6...

Page 34: ...ess using any addressing mode In other words there is no addressing mode restriction for these registers as is the case for set 1 and set 2 registers All registers in prime area locations are addressable immediately following a reset FFH C0H 00H Set 2 Prime Register Space FFH D0H C0H Set 1 FCH E0H General purpose registers CPU and system registers Peripheral control registers Figure 2 4 Set 1 Set ...

Page 35: ...tions of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All of the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of...

Page 36: ...ted 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline we recommend that RP0 point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RP0 points to the upper slice and RP1 to the lower...

Page 37: ...R1 ADC R0 R2 R0 R0 R2 C ADC R0 R3 R0 R0 R3 C ADC R0 R4 R0 R0 R4 C ADC R0 R5 R0 R0 R5 C The sum of these six registers 6FH is located in the register R0 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be u...

Page 38: ... 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte ...

Page 39: ...working register area FFH C0H Set 2 CFH D7H D6H Set 1 FFH D0H Special Purpose Registers General Purpose Register Register Pointers Control Registers All Addressing Modes Page 0 Indirect Register Indexed Addressing Modes Page 0 Register Addressing Only Can be Pointed by Register Pointer Prime Registers System Registers NOTE Only page 0 is implemented Page 0 Contains all of the addressable registers...

Page 40: ...at is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Register a hardware reset register pointers RP0 and RP1 point to the commom working register area locations C0H CfH RP0 1 1 0 0 0 0 0 0 RP1 1 1 0 0 1 0 0 0 FFH ...

Page 41: ... the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure ...

Page 42: ...ts Address OPCODE Selects RP0 or RP1 RP1 RP0 4 bit Address Provides Three Low order Bits Figure 2 11 4 Bit Working Register Addressing Register Address 76H RP0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 R6 0 1 1 0 1 1 1 0 Selects RP0 Instruction INC R6 OPCODE RP1 0 1 1 1 1 0 0 0 Figure 2 12 4 Bit Working Register Addressing Example ...

Page 43: ... address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided...

Page 44: ...Address Form Instruction LD R11 R2 RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies Working Register Addressing Register Address 0ABH Figure 2 14 8 Bit Working Register Addressing Example ...

Page 45: ...he stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 Stack Contents After a Call Instruction Stack Contents After an Interrupt Top of Stack FLAGS PCH PCL PCL PCH Top of Stack Low Address High Address Figure 2 15 Stack Operation...

Page 46: ... register file using PUSH and POP instructions LD SPL 0FFH SPL FFH Normally the SPL is set to 0FFH by the initialization routine PUSH PP Stack address 0FEH PP PUSH RP0 Stack address 0FDH RP0 PUSH RP1 Stack address 0FCH RP1 PUSH R3 Stack address 0FBH R3 POP R3 R3 Stack address 0FBH POP RP1 RP1 Stack address 0FCH POP RP0 RP0 Stack address 0FDH POP PP PP Stack address 0FEH ...

Page 47: ... the method used to determine the location of the data operand The operands specified in instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction Register R Indirect Register IR Indexed X Direct Addr...

Page 48: ...PERAND 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Register File Program Memory Figure 3 1 Register Addressing 4 bit Working Register Points to the Working Register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers i...

Page 49: ... register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Remember however that locations C0H FFH in set 1 cannot be accessed using Indirect Register addressing mode dst Address of Operand used by Instruction OPCODE ADDRESS 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example Sam...

Page 50: ...ts to Register Pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in Instruction OPERAND Register Pair Program Memory 16 Bit Address Points to Program Memory Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 51: ...Register Address Point to the Working Register 1 of 8 Sample Instruction OR R3 R6 Program Memory Register File src 3 LSBs Selected RP Points to Start of Woking Register Block RP0 or RP1 MSB Points to RP0 or RP1 Value used in Instruction OPERAND Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 52: ...tion OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2 bit Point to Working Register Pair 1 of 4 LSB Selects Register Pair 16 Bit Address Points to Program Memory or Data Memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP Points to Start of Working Register Block NOTE LDE command is not available because an external interface is no...

Page 53: ...t offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructio...

Page 54: ...rogram Memory x OFFSET 4 Bit Working Register Address Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Next 2 Bits Register Pair Value used In Instruction 8 Bits 16 Bits 16 Bits NOTE LDE command is not available because an external interface is n...

Page 55: ...ns LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Next 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits dst src OPCODE Program Memory x OFFSET 4 Bit Working Register Address OFFSET NOTE LDE command is not available because an external in...

Page 56: ...Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address Byte LSB Selects Program Memory or Data Memory 0 Program Memory 1 Da...

Page 57: ...m Memory Lower Address Byte Program Memory Address Used Upper Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 58: ...ode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Current Instruction Program Memory Locations 0 255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Zero Sample Inst...

Page 59: ...rs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFFSET is a value in...

Page 60: ...plied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers The Operand value is in the instruction OPCODE Sample Instruction LD R0 0AAH Program Memory OPERAND Figure 3 14 Immediate Addressing ...

Page 61: ...ard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual Data and counter registers are not described in detail in this reference section More information about all of the regi...

Page 62: ...data register P0 224 E0H R W Port 1 data register P1 225 E1H R W Port 2 data register P2 226 E2H R W Location E3H E6H is not mapped Port 0 pull up resistor enable register P0PUR 231 E7H R W Port 0 control register high byte P0CONH 232 E8H R W Port 0 control register low byte P0CONL 233 E9H R W Port 1 control register high byte P1CONH 234 EAH R W Port 1 control register low byte P1CONL 235 EBH R W ...

Page 63: ...9 F9H R W Timer 1 control register T1CON 250 FAH R W STOP Control register STOPCON 251 FBH W Locations FCH is not mapped Basic timer counter BTCNT 253 FDH R note External memory timing register EMT 254 FEH R W Interrupt priority register IPR 255 FFH R W NOTE You cannot use a read only register as a destination for the instructions OR AND LD or LDB ...

Page 64: ...t or related bits Register name Register ID Sign Flag S 0 Operation does not generate a carry or borrow condition 0 Operation generates carry out or borrow into high order bit 7 0 Operation result is a non zero value 0 Operation result is zero 0 Operation generates positive number MSB 0 0 Operation generates negative number MSB 1 Description of the effect of specific bit settings Set 1 Register lo...

Page 65: ...96 0 1 fOSC 1024 1 0 fOSC 128 1 1 Invalid setting not used for S3C80A5B 1 Basic Timer Counter Clear Bit 1 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 2 0 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation ...

Page 66: ... Counter A Interrupt Timing Selection Bits 0 0 Elapsed time for Low data value 0 1 Elapsed time for High data value 1 0 Elapsed time for combined Low and High data values 1 1 Invalid setting not used for S3C80A5B 3 Counter A Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 2 Counter A Start Bit 0 Stop counter A 1 Start counter A 1 Counter A Mode Selection Bit 0 One shot mode 1 Repeating...

Page 67: ...ck System Clock Selection Bits 1 0 0 fOSC 16 0 1 fOSC 8 1 0 fOSC 2 1 1 fOSC non divided 2 0 Subsystem Clock Selection Bit 2 1 0 1 Invalid setting for S3C80A5B Other value Select main system clock MCLK NOTES 1 After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 2 These selection bits are req...

Page 68: ...n for external device 5 4 Program Memory Automatic Wait Control Bits 0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles 3 2 Data Memory Automatic Wait Control Bits 0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles 1 Stack Area Selection Bit 0 Select internal register file area 1 Select external data memory area 0 Not used for S3C80A5B NOTE The EMT regis...

Page 69: ...ositive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 Decimal Adjust Flag D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H 0 No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of bit 3 or subtraction generated borro...

Page 70: ...P0 0 0 Disable mask 1 Enable un mask 5 Not used for S3C80A5B 4 Interrupt Level 4 IRQ4 Enable Bit Counter A Interrupt 0 Disable mask 1 Enable un mask 3 2 Not used for S3C80A5B 1 Interrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow 0 Disable mask 1 Enable un mask 0 Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or Overflow 0 Disable mask 1 Enable un mask NOTES 1 When an interrupt level is ma...

Page 71: ...of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the low...

Page 72: ...0 1 B C A 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 IRQ7 1 IRQ7 IRQ6 5 3 Not used for S3C80A5B 2 Input Group B Priority Control Bit 0 IRQ4 1 IRQ4 0 Interrupt Group A Priority Control Bit 0 IRQ0 IRQ1 1 IRQ1 IRQ0 NOTE The S3C80A5B interrupt structure uses only five levels IRQ0 IRQ1 IRQ4 IRQ6 IRQ7 Beca...

Page 73: ...1 Pending 6 Level 6 IRQ6 Request Pending Bit External Interrupts P0 3 P0 0 0 Not pending 1 Pending 5 Not used for S3C80A5B 4 Level 4 IRQ4 Request Pending Bit Counter A Interrupt 0 Not pending 1 Pending 3 2 Not used for S3C80A5B 1 Level 1 IRQ1 Request Pending Bit Timer 1 Match or Overflow 0 Not pending 1 Pending 0 Level 0 IRQ0 Request Pending Bit Timer 0 Match or Overflow 0 Not pending 1 Pending NO...

Page 74: ...ng and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 3 2 P0 5 INT4 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 0 P0 4 INT4 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS ...

Page 75: ...ing and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 3 2 P0 1 INT1 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 0 P0 0 INT0 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS...

Page 76: ...Enable Bit 0 Disable interrupt 1 Enable interrupt 5 P0 5 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 P0 4 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 3 P0 3 External Interrupt INT3 Enable Bit 0 Disable interrupt 1 Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit 0 Disable interrupt 1 Enable interrupt 1 P0 1 External Interrupt ...

Page 77: ...when read 4 P0 4 External Interrupt INT4 Pending Flag 0 No P0 4 external interrupt pending when read 1 P0 4 external interrupt is pending when read 3 P0 3 External Interrupt INT3 Pending Flag 0 No P0 3 external interrupt pending when read 1 P0 3 external interrupt is pending when read 2 P0 2 External Interrupt INT2 Pending Flag 0 No P0 2 external interrupt pending when read 1 P0 2 external interru...

Page 78: ...pull up resistor 1 Enable pull up resistor 5 P0 5 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P0 4 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P0 3 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P0 2 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P0 ...

Page 79: ...0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Invalid setting 5 4 P1 6 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Invalid setting 3 2 P1 5 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Invalid setting 1 0 P1 4 Mode Selection Bits 0 0 C MOS input mode 0 1 Open d...

Page 80: ... 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Invalid setting 5 4 P1 2 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Invalid setting 3 2 P1 1 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Invalid setting 1 0 P1 0 Mode Selection Bits 0 0 C MOS input mode 0 1 Open dr...

Page 81: ...pull up resistor 1 Enable pull up resistor 5 P1 5 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P1 4 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P1 3 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P1 2 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P1 ...

Page 82: ... 0 Push pull output mode 1 1 C MOS input with pull up mode 5 4 P2 1 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 2 P2 0 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 1 P2 1 Alternative Function Selection Bits 0 Normal I O function 0 ...

Page 83: ...on Bits 0 0 0 0 Destination page 0 note 3 0 Source Register Page Selection Bits Bits 0 0 0 0 Source page 0 note NOTE In the S3C80A5B microcontroller a paged expansion of the internal register file is not implemented For this reason only page 0 settings are valid Register page pointer values for the source and destination register page are automatically set to 0000B following a hardware reset These...

Page 84: ...P0 points to address C0H in register set 1 selecting the 8 byte working register slice C0H C7H 2 0 Not used for S3C80A5B RP1 Register Pointer 1 D7H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 24 8 byte working regi...

Page 85: ...a reset STOPCON Stop Control Register FBH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Addressing Mode Register addressing mode only 7 0 Stop Control Register enable bits 1 0 1 0 0 1 0 1 Enable STOPCON NOTES 1 To get into STOP mode stop control register must be enabled just before STOP instruction 2 When STOP mode is released stop control register STO...

Page 86: ... for 0 1 1 S3C80A5B 1 0 0 1 0 1 1 1 0 IRQ6 1 1 1 IRQ7 1 Fast Interrupt Enable Bit 3 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit 4 0 Disable global interrupt processing 1 Enable global interrupt processing NOTES 1 Because an external interface is not implemented for the S3C80A5B SYM 7 must always be 0 2 You can select only one interrupt level...

Page 87: ... 1 1 PWM mode OVF interrupt can occur 3 Timer 0 Counter Clear Bit 0 No effect when write 1 Clear T0 counter T0CNT when write 2 Timer 0 Overflow Interrupt Enable Bit note 0 Disable T0 overflow interrupt 1 Enable T0 overflow interrupt 1 Timer 0 Match Interrupt Enable Bit 0 Disable T0 match interrupt 1 Enable T0 match interrupt 0 Timer 0 Match Interrupt Pending Flag 0 No T0 match interrupt pending wh...

Page 88: ... mode OVF interrupt can occur 3 Timer 1 Counter Clear Bit 0 No effect when write 1 Clear T1 counter T1CNT when write 2 Timer 1 Overflow Interrupt Enable Bit note 0 Disable T1 overflow interrupt 1 Enable T1 overflow interrupt 1 Timer 1 Match Capture Interrupt Enable Bit 0 Disable T1 match interrupt 1 Enable T1 match interrupt 0 Timer 1 Match Capture Interrupt Pending Flag 0 No T1 match interrupt pe...

Page 89: ... the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vecto...

Page 90: ... of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn m In the S3C80A5B microcontroller all three interrupt types are implemented Vectors Sources Levels S1 V1 S2 Type 2 IRQn S3 Sn V1 S1 V2 S2 Type ...

Page 91: ... and state flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed The S3C80A5B microcontroller supports non vectored interrupt Interrupt with Reset INTR to occur interrupt with system reset The Interrupt with Reset INTR has nothing to do...

Page 92: ...r RESET 100H Basic timer overflow INTR POR H W Timer 0 match S W IRQ0 Timer 0 overflow H W Timer 1 match S W IRQ1 Timer 1 overflow H W Counter A H W P0 3 external interrupt S W P0 2 external interrupt S W P0 1 external interrupt S W P0 0 external interrupt S W P0 7 external interrupt S W P0 6 external interrupt S W IRQ7 P0 5 external interrupt S W P0 4 external interrupt S W FCH FAH F6H F4H E8H E6...

Page 93: ...m memory ROM 00H FFH You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 2 lists all vector addresses The program reset address in the ROM is 0100H 15 872 15 Kbyte ROM Interrupt Vector Area 255 0 3E00H 0FFH 0H Decimal HEX S3C80A5B Figure 5 3 ROM Vector Address Area ...

Page 94: ...terrupt IRQ7 232 E8H P0 6 external interrupt 232 E8H P0 5 external interrupt 232 E8H P0 4 external interrupt 230 E6H P0 3 external interrupt IRQ6 3 228 E4H P0 2 external interrupt 2 226 E2H P0 1 external interrupt 1 224 E0H P0 0 external interrupt 0 NOTES 1 Interrupt priorities are identified in inverse order 0 is highest priority 1 is the next highest and so on 2 If two or more interrupts within ...

Page 95: ... priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Inter...

Page 96: ...MR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing the part of your application program that handles interrupt processing be sure to include the necessary register file address register pointer information IRQ0 IRQ1 IRQ4 and IRQ6 IRQ7 Interrupts EI Interrupt Request Register Read on...

Page 97: ...TAL F3H F4H F5H P0 7 external interrupt P0 6 external interrupt P0 5 external interrupt P0 4 external interrupt IRQ7 P0CONH P0INT P0PND E8H F1H F2H P0 3 external interrupt P0 2 external interrupt P0 1 external interrupt P0 0 external interrupt IRQ6 P0CONL P0INT P0PND E9H F1H F2H NOTES 1 Because the timer 0 and timer 1 overflow interrupts are cleared by hardware the T0CON and T1CON registers contro...

Page 98: ... a reset operation in order to enable interrupt processing Although you can manipulate SYM 0 directly to enable and disable interrupts during normal operation we recommend using the EI and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Global interrupt enable bit 0 Disable all interrupts 1 Enable all interrupts Not used for the S3C80A5B External interface tri state enable ...

Page 99: ...ed to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruct...

Page 100: ...he IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ4 Group C IRQ6 IRQ7 IPR Group B IPR Group C IRQ4 IRQ6 C1 C2 IRQ7 IPR Group A IRQ1 A2 IRQ0 A1 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group rel...

Page 101: ...RQ6 IRQ7 1 IRQ7 IRQ6 Group B note 0 IRQ4 1 IRQ4 Group priority 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Undefined B C A A B C B A C C A B C B A A C B Undefined D7 D4 D1 NOTE In this device interrupt structure only levels IRQ0 IRQ1 IRQ4 IRQ6 IRQ7 are used Settings for group subgroup B which control relative priorities for levels IRQ2 IRQ3 and IRQ5 are therefore not evaluated Figure 5 8 Inter...

Page 102: ...ing bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still d...

Page 103: ...ng bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C80A5B interrupt structure the timer 0 and timer 1 overflow interrupts IRQ0 and IRQ1 and the counter A interrupt IRQ4 belong to this category of interrupts whose pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type...

Page 104: ...SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register If all of the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt mach...

Page 105: ...the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt 3 Execute an EI instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an I...

Page 106: ...2 The FLAG register values are written to the FLAGS FLAGS prime register 3 The fast interrupt status bit in the FLAGS register is set 4 The interrupt is serviced 5 Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back 6 The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register...

Page 107: ...nd shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working regi...

Page 108: ...oad external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POP...

Page 109: ...ry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ...

Page 110: ...c Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset ...

Page 111: ...ht RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter St...

Page 112: ...or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously t...

Page 113: ...ons D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subt...

Page 114: ...logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffi...

Page 115: ...n number only Ir Indirect working register only Rn n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr r...

Page 116: ... r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM BAND r0 Rb I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM BIT r1 b B 8 DECW RR1 DECW IR1 PUSHUD IR1 R2 PUSHUI IR1 R2 MULT R2 RR1 MULT IR2 RR1 MULT IM RR1 LD r1 x r2 B 9 RL R1 RL IR1 POPUD IR2 R1 POPUI IR2 R1 DIV R2 RR1 DIV IR2 RR1 DIV IM RR1 LD r2 x r1 L A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC r1 Irr2 xL E B...

Page 117: ...OWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 118: ...10 note NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 note UGE Unsigned greater than or equal C 0 0111 note ULT Unsigned less than C 1 1011 UGT Unsi...

Page 119: ...ng The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressin...

Page 120: ...f both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H C...

Page 121: ... sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H ADD R1 R2 R1 1CH R2 ...

Page 122: ...se V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register 01H 00H registe...

Page 123: ...rmat Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 67 r0 Rb opc src b 1 dst 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 R1 06H register 01H 05H BAND 01H 1 R1 Register 01H 05H...

Page 124: ...ycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register...

Page 125: ...Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the va...

Page 126: ...Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leavin...

Page 127: ... Bytes Cycles Opcode Hex Addr Mode dst opc dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 R1 0FH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leav...

Page 128: ...the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B Th...

Page 129: ...d Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 te...

Page 130: ...Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source re...

Page 131: ...src opc dst b 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 R1 06H register 01H 03H BXOR 01H 2 R1 Register 01H 07H R1 07H In the first ex...

Page 132: ...nstruction CALL RR0 SP 0000H 0000H 1AH 0001H 49H CALL 40H SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address of the first instru...

Page 133: ...lag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 134: ...dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ...

Page 135: ...ormat Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F8H 11111000B In the second...

Page 136: ...rc dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1...

Page 137: ...rmat Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJ...

Page 138: ... Opcode Hex Addr Mode dst src opc src dst RA 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 04H CPIJNE R1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R...

Page 139: ...ore DA Bits 4 7 Value Hex H Flag Before DA Bits 0 3 Value Hex Number Added to Byte Carry After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 F 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry from the most signif...

Page 140: ... 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0 0 0 1 0 1 0 1 15 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 42 Assuming the same values given above the ...

Page 141: ...cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements t...

Page 142: ...s Opcode Hex Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples Given R0 12H R1 34H R2 30H register 30H 0FH and register 31H 21H DECW RR0 R0 12H R1 33H DECW R2 Register 30H 0FH register 31H 20H In the first example destination register R0 contains the value 12H and register R1 the value 34H The statement DECW RR0 addresses R0 and the following operand R1 as a 16 bit word and decrements the value of ...

Page 143: ...ive interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt so...

Page 144: ...nt 1 cleared otherwise V Set if quotient is 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given R0 10H R1 03H R2 40H register 40H 80H DIV RR0 R2 R0 03H R1 40H DIV RR0 R2 R0...

Page 145: ...ing used as a counter should be set at the one of location 0C0H to 0CFH with SRP SRP0 or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst r opc dst 2 8 jump taken rA RA 8 no jump r 0 to F Example Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is us...

Page 146: ...nding bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM...

Page 147: ...the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement 0050 IP 0022 SP 22 Data Address Data 0040 PC 40 41 42 43 Enter Address H Address L Address H Address Data 1F 01 10 Memory 0043 IP 0020 SP 20 21 22 IPH IPL D...

Page 148: ... is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement 0050 IP 0022 SP Address Data 0040 PC Address Data Memory 0052 IP 0022 SP Address Data 0060 PC Address Data Memory Stack Stack Bef...

Page 149: ...lock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock ...

Page 150: ...e dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INC R0 R0 1CH INC 00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register 0...

Page 151: ...gister 02H 0FH and register 03H 0FFH INCW RR0 R0 1AH R1 03H INCW R1 Register 02H 10H register 03H 00H In the first example the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode...

Page 152: ...ast Bytes Cycles Opcode Hex opc 1 6 BF Example In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to I...

Page 153: ... byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP Assuming that the ...

Page 154: ...riginal value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format 1 Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Example Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL_X...

Page 155: ...ntents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r ...

Page 156: ...r 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register 31H 0AH R0 01H R1...

Page 157: ...s the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R0 06H and general register 00H 05H LDB R0 00H 2 R0 07H register 00H 05H LDB 00H 0 R0 R0 06H register 00H 04H In the first example destination working register R0 contains the value 06H and the source general register 00H the value 05H The statement LD R0 0...

Page 158: ... E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the destinat...

Page 159: ...ion 0105H 01H RR2 R0 6DH R2 01H R3 04H LDE R0 01H RR2 R0 contents of external data memory location 0105H 01H RR2 R0 7DH R2 01H R3 04H LDC note 01H RR2 R0 11H contents of R0 is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of R0 is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 R0 contents of program memory location 1104H 1000H 0104H R0 ...

Page 160: ...ted LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH LDCD R8 RR6 0...

Page 161: ...ffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH and 1034H 0D5H LDC...

Page 162: ...tion The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F2 Irr r Examples Given R0 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 RR6 1 77H contents o...

Page 163: ...ocation The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F3 Irr r Examples Given R0 7FH R6 21H and R7 0FFH LDCPI RR6 R0 RR6 RR6 1 7FH contents of R0 ...

Page 164: ... and register 03H 0FH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H Register 00H 03H register 01H 0FH register 02H 03H register 03H 0FH LDW RR2 R7 R2 03H R3 0FH LDW 04H 01H Register 04H 03H register 05H 0FH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H 0FH register 03H 0EDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H...

Page 165: ...esult is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H Register 00H 00H register 01H 0C0H MULT 00H 30H Register 00H 06H register 0...

Page 166: ...ram counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 0F Example The following diagram shows one example of how to use the NEXT instruction Data 01 10 Before After 0045 IP Address Data 0130 PC 43 44 45 Address H Address L Address H Address Data Memory 130 Routine 0043 IP Address Data 0120 PC 43 44 45 Address H Address L A...

Page 167: ...ction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ...

Page 168: ...rmat Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH OR 00H 02H Registe...

Page 169: ...c dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H Register 00H 55H SP 00FCH POP 00H Register 00H 01H register 01H 55H SP 00FCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register 00H and then increments the stack ...

Page 170: ...cremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 92 R IR Example Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents of...

Page 171: ...inter is then incremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 00H Register 00H 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general r...

Page 172: ...ternal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SPH 00H and SPL 00H PUSH 40H Register 40H 4FH stack register 0FFH 4FH SPH 0FFH SPL 0FFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0FFH 0AAH SPH 0FFH SPL 0FFH In the first example if the stack pointer contains the value 0000H and general register 40H the valu...

Page 173: ...pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 82 IR R Example Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the ...

Page 174: ...stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 83 IR R Example Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leavin...

Page 175: ... Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 176: ...cuted is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Example Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The statement RET pops the contents of stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the value in location...

Page 177: ... cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first example if general re...

Page 178: ...etic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has t...

Page 179: ...urred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 001100...

Page 180: ...ic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if general register 00H contains...

Page 181: ...s the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting bank 0 register addressing ...

Page 182: ...gister FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented ...

Page 183: ...at is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc d...

Page 184: ...rry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to logic one ...

Page 185: ...et if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the value 9AH 10011010B the st...

Page 186: ... write one or both of the register pointers RP0 and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode src opc src 2 4 31 IM Examples The statement SRP 40H sets register pointer 0 RP0 at location 0D6H to 40H and reg...

Page 187: ...peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 7F Example The statement STO...

Page 188: ...wise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R1 R2 R1 0FH R2 03H...

Page 189: ...7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 F0 R 4 F1 IR Examples Given Register 00H 3EH register 02H 03H and register 03H 0A4H SWAP 00H Register 00H 0E3H SWAP 02H Register 02H 03H register 03H 4AH In the first example if general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upp...

Page 190: ...ed to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H 02H Z 1 TCM 00H 01...

Page 191: ...Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H re...

Page 192: ...eased by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement EI WFI Next instruction Main program Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed Enable global interrupt...

Page 193: ...fected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Register 00H 08H registe...

Page 194: ...l oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fOSC divided by 1 2 8 or 16 Clock circuit control register CLKCON XIN XOUT C1 C2 Figure 7 1 Main Oscil...

Page 195: ...OPCON register is automatically cleared In Idle mode the internal clock signal is gated away from the CPU but continues to be supplied to the interrupt structure timer 0 and counter A Idle mode is released by a reset or by an interrupt external or internally generated Main OSC STOP Instruction Noise filter Oscillator Stop Oscillator Wake up INT Pin 1 1 16 1 2 1 8 M U X CLKCON 3 4 STOPCON CPU Clock...

Page 196: ...ion The IRQ wake up enable bit is CLKCON 7 In S3C80A5B this bit is not valid any more Actually bit 7 6 5 2 1 and 0 are no meaning in S3C80A5B After a reset the main oscillator is activated and the fOSC 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fOSC fOSC 2 or fOSC 8 System Clock Control Register CLKCON D4H Set 1 R W 7 6 5 4 3 2...

Page 197: ... RESET The Low Voltage detect circuit is built on the S3C80A5B product for system reset not in stop mode When the operating status is not stop mode it detects a slope of VDD by comparing the voltage at VDD with VLVD Low level Detect Voltage The reset pulse is generated by the rising slope of VDD While the voltage at VDD is rising up and passing VLVD the reset pulse is occurred at the moment VDD VL...

Page 198: ...op mode INTR function can be discarded WATCHDOG TIMER RESET The S3C80A5B build a watch dog timer that can recover to normal operation from abnormal function Watchdog timer generates a system reset signal if not clearing a BT Basic Counter within a specific time by program System reset can return to the proper operation of chip POWER ON RESET POR The power on Reset circuit is built on the S3C80A5B ...

Page 199: ...inimum time interval after the power supply comes within tolerance The minimum required reset operation for a oscillation stabilization time is 16 oscillation clocks All system and peripheral control registers are then reset to their default hardware values see Tables 5 1 In summary the following sequence of events occurs during a reset operation All interrupts are disabled The watchdog function b...

Page 200: ...0 D2H 0 0 0 0 0 0 0 0 Basic timer control register BTCON 211 D3H 0 0 0 0 0 0 0 0 Clock control register CLKCON 212 D4H 0 0 0 0 0 0 0 0 System flags register FLAGS 213 D5H 0 0 Register pointer 0 RP0 214 D6H 1 1 0 0 0 Register pointer 1 RP1 215 D7H 1 1 0 0 1 Location D8H SPH is not mapped Stack pointer low byte SPL 217 D9H Instruction pointer high byte IPH 218 DAH Instruction pointer low byte IPL 21...

Page 201: ...register high byte T1CNTH 246 F6H 0 0 0 0 0 0 0 0 Timer 1 counter register low byte T1CNTL 247 F7H 0 0 0 0 0 0 0 0 Timer 1 data register high byte T1DATAH 248 F8H 1 1 1 1 1 1 1 1 Timer 1 data register low byte T1DATAL 249 F9H 1 1 1 1 1 1 1 1 Timer 1 control register T1CON 250 FAH 0 0 0 0 0 0 0 0 Stop control register STOPCON 251 FBH 0 0 0 0 0 0 0 0 Locations FCH is not mapped Basic timer counter B...

Page 202: ...rval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H USING AN INTR TO RELEASE STOP MODE Stop mode is released when INTR Interrupt with Reset occurs INTR occurs when falling rising edge is detected at P0 during stop mode and it make system reset NOTES 1 Do not use stop mode if you are using an external clock source becaus...

Page 203: ...ster CLR SYM CLR PP CLR EMT CLR IPR LD P0CONH 00H Initialize the control register LD P0CONL 00H LD P0PUR 0FFH CHECK_RAM Check the RAM data whether it is stop mode releasing or Power On RESET LD R0 0BFH If Power On Reset go to POR_RESET CHK_R CP R0 R0 JR NE POR_RESET DEC R0 CP R0 0B0H JR UGE CHK_R STOP_RESET STOP mode releasing JR MAIN POR_RESET LD R0 0FFH Power On Reset CHECK RAM data are failed s...

Page 204: ...A5B 8 8 F PROGRAMMING TIP To Divide STOP Mode Releasing and POR Continued CHK_W LD R0 R0 DEC R0 CP R0 0B0H JR UGE CHK_W MAIN CP P0 0FFH JR EQ ENT_STOP JP T MAIN ENT_STOP LD STOPCON 0A5H Enter the STOP mode STOP NOP NOP JP RESET ...

Page 205: ...registers are retained The reset automatically selects the slowest clock because of the hardware reset value for the CLKCON register If all external interrupts are masked in the IMR register a reset is the only way you can release Idle mode 2 Activate any enabled interrupt internal or external When you use an interrupt to release Idle mode the 2 bit CLKCON 4 CLKCON 3 value remains unchanged and th...

Page 206: ... Summary of Each Mode Item Mode IDLE STOP Approach Condition VDD is higher than VLVD VLVD VDD IDLE instruction VDD is higher than VLVD VLVD VDD STOPCON A5H STOP instruction Release Source Interrupt T0 T1 interrupt Counter A interrupt Ext interrupt Port0 RESET POR LVD WDT RESET INTR POR ...

Page 207: ...3C80A5B Port Configuration Overview Port Configuration Options 0 8 bit general purpose I O port Input or push pull output external interrupt input on falling edges rising edges or both edges all P0 pin circuits have noise filters and interrupt enable disable P0INT and pending control P0PND Pull up resistors can be assigned to individual P0 pins using P0PUR register settings Specially Interrupt wit...

Page 208: ... port 2 is a 3 bit I O port the port 2 data register only contains values for P2 0 P2 1 and P2 2 The P2 register also contains values for P2 0 P2 1 and P2 2 The P2 register also contains a special carrier on off bit P2 5 See the port 2 description for details All other S3C80A5B I O ports are 8 bit PULL UP RESISTOR ENABLE REGISTERS Pull up Resistor Enable Register PnPUR where n 0 1 E7H ECH R W 7 6 ...

Page 209: ... interrupt control register P0INT set 1 F1H is used to enable and disable external interrupt input You can poll the port 0 interrupt pending register P0PND to detect and clear pending conditions for these interrupts The lower nibble pins P0 3 P0 0 are used for INT3 INT0 input IRQ6 respectively The upper nibble pins P0 7 P0 4 are all used for INT4 input IRQ7 Interrupts that are detected at any of t...

Page 210: ...e a specific external interrupt you set its P0INT n bit to 1 You must also be sure to make the correct settings in the corresponding port 0 control register P0CONH P0CONL PORT 0 INTERRUPT PENDING REGISTER P0PND The port 0 interrupt pending register P0PND contains pending bits flags for each port 0 interrupt see Figure 10 6 When a P0 external interrupt is acknowledged by the CPU the service routine...

Page 211: ...T1 P0 0 INT0 Figure 9 4 Port 0 External Interrupt Control Register P0INT Port 0 Interrup Pending Register P0PND F2H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Port 0 Interrupt Pending Bits 0 0 1 1 Interrupt not pending Clear P0 n pending condition when write P0 n interrupt is pending No effect when write P0 7 INT4 P0 6 INT4 P0 5 INT4 P0 4 INT4 P0 3 INT3 P0 2 INT2 P0 1 INT1 P0 0 INT0 Figure 9 5 Port 0 Exter...

Page 212: ... register contains four bit pairs and each 2 bit value configures one port pin see Figures 9 6 and 9 7 Following a hardware reset the port 1 control registers are cleared to 00H configuring port 0 initially to Input mode To assign pull up resistors to P1 pins you make the appropriate settings to the port 1 pull up resistor enable register P1PUR Port 1 Control Register High Byte P1CONH EAH Set 1 R ...

Page 213: ...er Low Byte P1CONL EBH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB P1 3 P1 0 P1 2 P1 1 P1CONL Pin Configureation Settings 00 01 10 11 Input mode Open drain output mode Push pull output mode Invalid setting Figure 9 7 Port 1 Low Byte Control Register P1CONL ...

Page 214: ...ithout pull up for T0CK or output functions push pull or open drain output mode for REM and timer 0 PWM Port 2 pins have high current drive capability to support LED applications A reset operation clears P2CON to 00H selecting Input mode as the initial port 2 function Port 2 Control Register P2CON F0H R W 7 6 5 4 3 2 1 0 MSB LSB P2 2 P2 2 P2 1 P1 0 P2 1 Alternative Function Enable 0 1 Normal I O F...

Page 215: ...O PORTS 9 9 Port 2 Data Register P2 E2H R W 7 6 5 4 3 2 1 0 MSB LSB Not used for S3C80A5 P2 0 T0_PWM Carrier on off for Remote Controller P2 2 P2 1 REM TOCK Not used for S3C80A5 Figure 9 9 Port 2 Data Register P2 ...

Page 216: ...e BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A system reset clears BTCON This enables the watchdog function and selects ...

Page 217: ... Disable watchdog timer Other value Enable watchdog timer Divider clear bit for basic timer and timer 0 0 No effect 1 Clear both dividers Basic timer input clock selection bits 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 01 10 11 fOSC 4096 fOSC 1024 fOSC 128 Invalid selection Figure 10 1 Basic Timer Control Register BTCON ...

Page 218: ...ed automatically TIMER 0 CONTROL REGISTER T0CON You use the timer 0 control register T0CON to Select the timer 0 operating mode interval timer Select the timer 0 input clock frequency Clear the timer 0 counter T0CNT Enable the timer 0 overflow interrupt or timer 0 match interrupt Clear timer 0 match interrupt pending conditions T0CON is located in set 1 at address D2H and is read write addressable...

Page 219: ...r 0 operating mode selection bits 00 Interval mode 01 Overflow mode OVF interrupt can occur 10 Overflow mode OVF interrupt can occur 11 PWM mode OVF interrupt can occur Timer 0 overflow interrupt enable bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 0 match interrupt enable bit 0 Disable interrupt 1 Enable interrupt Timer 0 match interrupt pending bit 0 No interrupt pending 0 C...

Page 220: ...nding bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the T0 reference data register T0DATA The match signal generates a timer 0 match interrupt T0INT vector FCH and clears the counter If for example you write the value 10H to T0DATA and 0BH to T0CON the counter will increment until it reaches 10H At this point ...

Page 221: ...rrupt interrupts are not typically used in PWM type applications Instead the pulse at the T0PWM pin is held to Low level as long as the reference data value is less than or equal to the counter value and then the pulse is held to High level for as long as the data value is greater than the counter value One pulse width is equal to tCLK 256 see Figure 11 4 Interrupt Enable Disable T0CON 1 CTL P2 0 ...

Page 222: ...a Bus Bit 1 Data Bus Match Signal T0CON 3 T0OVF 8 Bit Basic Counter Read Only OVF Bit 2 Bit 3 OVF DIV R 1 4096 1 1024 1 128 P2 1 T0CK Bit 1 PND T0CON 0 Match 2 P2 0 Bits 5 4 T0PWM T0INT RESET Data Bus Basic Timer Control Register Timer 0 Control Register MUX MUX DIV 1 4096 1 1024 1 128 R Basic Timer Control Register Write 1010xxxxB to disable 8 Bit Up Counter Read Only R 8 Bit Comparator Timer 0 B...

Page 223: ...SET DI Disable all interrupts LD BTCON 03H Enable the watchdog timer LD CLKCON 18H Non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte 0 Stack area starts at 0FFH SRP 0C0H Set register pointer 0C0H EI Enable interrupts MAIN LD BTCON 02H Enable the watchdog timer Basic timer clock fOSC 4096 Clear basic timer counter NOP NOP JP T MAIN ...

Page 224: ...e 0 is executed after a timer 0 interrupt ORG 0FAH Timer 0 overflow interrupt VECTOR T0OVER ORG 0FCH Timer 0 match capture interrupt VECTOR T0INT ORG 0100H RESET DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Select non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte 0 Stack area starts at 0FFH LD T0CON 4BH Write 01001011B I...

Page 225: ...o stack SRP0 60H RP0 60H INC R0 R0 R0 1 ADD R2 R0 R2 R2 R0 ADC R3 R2 R3 R3 R2 Carry ADC R4 R0 R4 R4 R0 Carry CP R0 32H 50 4 200 ms JR ULT NO_200MS_SET BITS R1 2 Bit setting 61 2H NO_200MS_SET LD T0CON 42H Clear pending bit POP RP0 Restore register pointer 0 value T0OVER IRET Return from interrupt service routine ...

Page 226: ...DATAL set 1 F8H and F9H R W A 16 bit comparator You can select one of the following clock sources as the timer 1 clock Oscillator frequency fOSC divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 1 in two ways As a normal free run counter generating a timer 1 overflow interrupt IRQ1 vector F4H at programmed time intervals To generate a ...

Page 227: ...at is written to the timer 1 reference data registers T1DATAH and T1DATAL When a match condition is detected by the 16 bit comparator the match interrupt is generated the counter value is cleared and up counting resumes from 00H In match mode program software can poll the timer 1 match interrupt pending bit T1CON 0 to detect when a timer 1 match interrupt pending condition exists T1CON 0 1 When th...

Page 228: ...3 Match Signal T1OVF OVF M U X Match note IRQ1 Data Bus MUX 16 Bit Up Counter Read Only R 16 Bit Comparator Timer 1 High Low Buffer Register Timer 1 Data High Low Register CAOF T F F fOSC 4 fOSC 8 fOSC 16 Clear T1CON 3 T1CON 2 IRQ1 T1CON 5 4 T1CON 1 T1CON 0 Figure 11 2 Timer 1 Block Diagram ...

Page 229: ... timer and disabling the timer 1 interrupts Timer 1 Control Register T1CON FAH R W 7 6 5 4 3 2 1 0 MSB LSB Timer 1 counter clear bit 0 No effect 1 Clear the timer 1 counter when write Timer 1 input clock selection bits 00 fOSC 4 01 fOSC 8 10 fOSC 16 11 Internal clock T F F Timer 1 operating mode selection bits 00 Interval mode 01 Overflow mode OVF interrupt can occur 01 Overflow mode OVF interrupt...

Page 230: ...0H Timer 1 Counter High Byte Register T1CNTH F6H Set 1 R 7 6 5 4 3 2 1 0 MSB LSB Reset Value 00H Timer 1 Data High Byte Register T1DATAH F8H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFh Timer 1 Data Low Byte Register T1DATAL F9H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFh Figure 11 4 Timer 1 Registers ...

Page 231: ...ents see Figure 12 1 Counter A control register CACON 8 bit down counter with auto reload function Two 8 bit reference data registers CADATAH and CADATAL Counter A has two functions As a normal interval timer generating a counter A interrupt IRQ4 vector ECH at programmed time intervals To supply a clock source to the 16 bit timer counter module timer 1 for generating the timer 1 overflow interrupt...

Page 232: ...nto the 8 bit counter However if the next borrow ovvurs the value of the CADATAL register is loaded into the 8 bit counter CACON 6 7 MUX DIV 1 DIV 2 DIV 4 DIV 8 CLK CACON 0 CAOF To Other Block P3 1 REM Repeat Control Interrupt Control CACON 4 5 CACON 2 fOSC Counter A Data High Byte Register INT GEN MUX 8 Bit Down Counter Counter A Data Low Byte Register CACON 3 IRQ4 CAINT Data Bus Figure 12 1 Coun...

Page 233: ... Control Register CACON F3H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Counter A input clock selection bits 00 fOSC 01 fOSC 2 10 fOSC 4 11 fOSC 8 Counter A output flip flop control bit 0 T FF is Low 1 T FF is High Counter A mode selection bit 0 One shot mode 1 Repeating mode Counter A interrupt selection bits 00 Elapsed time for Low data value 01 Elapsed time for High data value 10 Elapsed time for Low and...

Page 234: ...H When CAOF 0 tLOW CADATAL 2 x 1 fxx 0H CADATAL 100H where fx The selected clock tHIGH CADATAH 2 x 1 fxx 0H CADATAH 100H where fx The selected clock When CAOF 1 tLOW CADATAH 2 x 1 fxx 0H CADATAH 100H where fx The selected clock tHIGH CADATAL 2 x 1 fxx 0H CADATAL 100H where fx The selected clock To make tLOW 24 us and tHIGH 15 us fOSC 4 MHz fx 4 MHz 4 1 MHz Method 1 When CAOF 0 tLOW 24 us CADATAL 2...

Page 235: ... CADATAH 01 FFH CAOF 0 CADATAL 00H CADATAH 00H CAOF 1 CADATAL 00H CADATAH 00H E0H 0H Counter A Clock CAOF 0 CADATAL DEH CADATAH 1EH CAOF 0 CADATAL DEH CADATAH 1EH CAOF 1 CADATAL 7EH CADATAH 7EH CAOF 0 CADATAL 7EH CADATAH 7EH E0H 20H 20H 80H 80H 80H 80H Figure 12 4 Counter A Output flip flop Waveforms in Repeat Mode ...

Page 236: ...on frequency is 4 MHz 0 25 µs CADATAH 8 795 µs 0 25 µs 35 18 CADATAL 17 59 µs 0 25 µs 70 36 Set P2 1 C MOS push pull output and CAOF mode ORG 0100H Reset address START DI LD CADATAL 70 2 Set 17 5 µs LD CADATAH 35 2 Set 8 75 µs LD P2CON 10101010B Set P2 to C MOS push pull output Set P2 1 to REM output LD CACON 00000110B Clock Source fOSC Disable Counter A interrupt Select repeat mode for Counter A ...

Page 237: ...2 1 C MOS push pull output and CAOF mode ORG 0100H Reset address START DI LD CADATAH 160 2 Set 40 µs LD CADATAL 1 Set any value except 00H LD P2CON 10101010B Set P2 to C MOS push pull output Set P2 1 to REM output LD CACON 00000001B Clock Source fOSC Disable Counter A interrupt Select one shot mode for Counter A Stop Counter A operation Set Counter A Output flip flop CAOF high LD P2 20H Set P2 5 C...

Page 238: ...e information is arranged in the following order Absolute maximum ratings D C electrical characteristics Data retention supply voltage in Stop mode Stop mode release timing when initiated by a Reset I O capacitance A C electrical characteristics Input timing for external interrupts port 0 Oscillation characteristics Oscillation stabilization time ...

Page 239: ...or port 3 40 Operating temperature TA 25 to 85 C Storage temperature TSTG 65 to 150 C Table 13 2 D C Electrical Characteristics TA 25 C to 85 C VDD 2 0 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Operating voltage VDD fOSC 8 MHz Instruction clock 1 33 MHz 2 0 5 5 V Input high voltage VIH1 All input pins except VIH2 0 8 VDD VDD V VIH2 XIN VDD 0 3 VDD Input Low voltage VIL1 All input pin...

Page 240: ...A ILIH2 VIN VDD XIN and XOUT 20 Input low leakage current ILIL1 VIN 0 V All input pins except XIN XOUT 1 µA ILIL2 VIN 0 V XIN and XOUT 20 Output high leakage current ILOH VOUT VDD All output pins 1 µA Output low leakage current ILOL VOUT 0 V All output pins 1 µA Pull up resistors RL1 VDD 2 4V VIN 0 V TA 25 C Ports 0 2 44 55 95 kΩ Supply current note IDD1 VDD 5 5V 8 MHz crystal 5 9 mA IDD2 Idle mod...

Page 241: ... Conditions Min Typ Max Unit Data retention supply voltage VDDDR 1 0 5 5 V Data retention supply current IDDDR VDDDR 1 0 V Stop mode 1 µA Table 13 5 Input output Capacitance TA 25 C to 85 C VDD 0 V Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f 1 MHz unmeasured pins are connected to VSS 10 pF Output capacitance COUT I O capacitance CIO Table 13 6 A C Electrical Characteristic...

Page 242: ...External Interrupts Port 0 Table 13 7 Oscillation Characteristics TA 25 C 85 C Oscillator Clock Circuit Conditions Min Typ Max Unit Crystal XOUT XIN C2 C1 CPU clock oscillation frequency 1 8 MHz Ceramic XTOUT XTIN C2 C1 CPU clock oscillation frequency 1 8 MHz External clock XOUT XIN External Clock Open Pin XIN input frequency 1 8 MHz ...

Page 243: ...stabilization wait time tWAIT when released by a reset 1 216 fOSC ms tWAIT when released by an interrupt 2 ms NOTES 1 fOSC is the oscillator frequency 2 The duration of the oscillation stabilization time tWAIT when it is released by an interrupt is determined by the setting in the basic timer control register BTCON 1 33 MHz 250 kHz 8 32 kHz 1 2 3 4 5 6 7 Supply Voltage V Instruction Clock 1 6n x o...

Page 244: ...urrently available in a 24 pin SOP and SDIP package NOTE Dimensions are in millimeters 24 SOP 375 10 30 0 30 13 24 1 12 15 74 MAX 15 34 0 20 0 69 0 8 0 15 0 10 0 05 9 53 7 50 0 20 0 85 0 20 0 05 MIN 2 30 0 10 2 50 MAX 0 38 0 10 MAX 0 10 0 05 1 27 Figure 14 1 24 Pin SOP Package Mechanical Data ...

Page 245: ...OTE Dimensions are in millimeters 23 35 MAX 22 95 0 20 1 70 24 SDIP 300 6 40 0 20 24 1 0 46 0 10 0 89 0 10 13 12 0 15 0 2 5 0 1 0 0 0 5 7 62 3 25 0 20 5 08 MAX 1 778 0 51 MIN 3 30 0 30 Figure 14 2 24 Pin SDIP Package Mechanical Data ...

Page 246: ...y Date Quantity Comments ROM code Not applicable See ROM Selection Form Customer sample Risk order See Risk Order Sheet Please answer the following questions F For what kind of product will you be using this order New product Upgrade of an existing product Replacement of an existing product Other If you are replacing an existing product please indicate the former product name F What are the main r...

Page 247: ..._______ write down the ROM code number note Package Number of Pins ____________ Package Type _____________________ Intended Application ________________________________________________________________ Product Model Number ________________________________________________________________ Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated bel...

Page 248: ...down the ROM code number note Attachment Check one Diskette PROM Customer Checksum ________________________________________________________________ Company Name ________________________________________________________________ Signature Engineer ________________________________________________________________ Please answer the following questions F Application Product Model ID _____________________...

Page 249: ...ice Name SEC Device Name YWW YWW Delivery Dates and Quantity ROM Code Release Date Required Delivery Date of Device Quantity Please answer the following questions F What is the purpose of this order New product development Upgrade of an existing product Replacement of an existing microcontroller Other If you are replacing an existing microcontroller please indicate the former microcontroller name ...

Page 250: ...____________________________________ Read Protection 1 Yes No Please answer the following questions F Are you going to continue ordering this device Yes No If so how much will you be ordering _________________pcs F Application Product Model ID _______________________ Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe in de...

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