Circuit Operating Descriptions
7-18
(2) Capstan Speed Error Detector
The capstan speed control operates so as to hold the capstan at a constant rotational speed, by measuring the peri-
od of the CFG signal. A digital counter detects the speed deviation from a preset value. The speed error data is
added to phase error data in a digital filter. this filter controls a pulse-width modulate (PWM) output, which con-
trols the rotational speed and phase the captain.
When the error is zero, the PWM circuit outputs a waveform with a 50% duty cycle.
The CFG input signal from the capstan motor is a square wave the CFG input signal is compared by a comparator
and than sent to speed error detector as the CFG signal.
The speed error detector uses the system clock to measure the period of the CFG signal, and detects the deviation
from a preset data value. The preset data is the value that would result from measuring the CFG signal period
with the clock signal if the capstan motor were running at the correct speed.
The error detector operates by latching a counter value when it detects an edge of the CFG signal.
the latched counter provides 16 bits of speed error data for the digital filter to operate on.
The digital filter adds the speed error data to phase error data from the capstan phase control system,then sends
the result to the pulse-width modulator as capstan error data.
(3) Capstan Phase Error Detector
The capstan phase error detector consists of a 16-bit counter, a capstan phase preset data register pair, a latch sig-
nal circuit driven by a feedback signal, and a captan phase error data register pair.
The capstan phase control in rec mode is executed by comparing HD S/W, which is synchronized with V-sync,
with divided CFG signal. And than it does in playback mode by comparing HD S/W, which is synchronized with
DFG and DPG, with PB CTL signal.
The latch signal for the phase error data in record mode is the divided CFG signal, which is divided from the CFG
signal in the CFG frequency divider to a frequency of 25Hz.
In playback, the latch signal is the divided CFG signal obtained by frequency division from the rising edge of
PB-CTL signal (playback control pulse signal).
The error data is a signed binary value centered on a phase error of zero (corresponding to the correct rotational
phase). If the phase legs the correct phase ,the error is positive (+).
If the phase leads the correct phase, the error is negative (-).
(4) Drum Speed Error Detector
Drum speed control operates so as to hold the drum at a constant rotational speed , by measuring the period of
the DFG signal . A digital counter detects the speed deviation from a preset value. The speed error data is added
to phase error data in a digital filter. The filter controls a pulsewidth modulated (PWM) output,which controls the
rotational speed and phase of the drum.
The DFG input signal from the drum motor is a square wave. The DFG input signal is compared by a comparator
and than sent to the speed error detector as the DFG signal.
The speed error detector uses the system clock to measure the period of the DFG signal, and detects the deviation
from a preset data value. The preset data is the value that would result from measuring the DFG signal period
with the clock signal if the drum motor were running at the correct speed.
The error detector operates by latching a counter value when it detects an edge of the DFG signal. The latched
count provides 16 bits of speed error data for the digital to operate on.
The digital filter adds the speed error data to phase error data from the drum phase control system, then sends
the result to the pulse-width modulator as drum error data.
