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© 2022 ROHM Co., Ltd.
No. 64UG118E Rev.002
Feb.2022
User’s Guide
Register Set File Structure Convention:
The register set definition follows the following scheme:
<Set Name>:Reg1,Reg2,Reg3
NOTE
: the set name can contain a space. The set name should be then followed by a colon “:”-sign and HEX addresses of the registers each
preceding by “0x” in front of it. The registers should be separated by commas “,”, and spaces are not allowed. Any register preceded by a space
will not be shown in the register view. The registers can be listed in any order and will be sorted automatically in the register viewer from lowest to
highest regardless of the order in the register set file. An example of the Data Stream register set is shown in (
).
Figure 60. KX132-1211 Data Stream Register Set
NOTE:
The ROHM EVK GUI SW loads all the register sets on startup. If changes were made to the content of the register set files or new register
set files were created, the changes will be visible the next time the program is loaded.
1.4.3.3
Register polling function
Register polling (i.e., reads) is a simple way to monitor the values of the registers defined in the Register sets (
). The Polling
feature is enabled with the Start button (
). A delay between successive register reads can be set as well (the default delay is 10 ms). The
polling can be stopped with the Stop button (
). Also, the polling feature has an “auto stop” – checkbox, which stops the register polling as
soon as the value of any of the registers in the register set changes. The register polling continues when the Start button is pressed again. The
below example shows how to monitor Wake-Up / Back-to-Sleep detection:
•
Select sensor KX132-1211 from "Device Name" pull down menu.
•
Select set “WU BTS Settings” register set from the “Select set” pull down menu.
•
Press the “Read all” button.
•
Uncheck the PC1 and DRDYE bit checkboxes in the register CNTL1 (0x1B) and press Write.
•
Set WUFE and BTSE bit values to ENABLED in CNTL4 (0x1E) register and press Write.
•
Check MAN_SLEEP bit box in CNTL5 (0x1F) register and press Write.
•
Write 5 to the BTSC (0x4C) register to set the back-to-sleep counter to 100 msec.
•
Write 5 to the WUFC (0x4D) register to set the wake-up counter to 100 msec.
•
Check the Power Control bit (PC1) in CNTL1 (0x1B) register to enable the sensor and press Write.
•
Select “Interrupts” register set from the “Select set” pull down menu
•
Press the “Start” button from “Polling”
Shake the device and monitor the status of the Wake-Up Function Status (WUFS) and Back-to-Sleep Status (BTS) bits in INS3 (0x18) register as
well as the WAKE bit in the STATUS_REG (0x19) register. When the device is shaken above the 0.5g threshold, the “Wake” bit is asserted to
indicate the wake state. Once the device is left in place and acceleration drops below 0.5g, the WAKE bit will be de-asserted to indicate the Sleep
mode (
NOTE
, if “Auto stop” was enabled, the polling will stop on the WAKE event and needs to be restarted to see the back-to-sleep event). The