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The Constant Fraction Discriminators CFD8c, CFD7x, CFD4c, CFD1c and CFD1x (11.0.1701.1)
3b.5
Performance limitations
Although greatest care was taken to optimize the performance and the error tolerance of the CFD units there are
circumstances where a CFD circuit in general produces inferior output results. A few common problems are described in the
next sub-sections.
3b.5.1
Temperature drift
For timing precisions < 100 ps it is recommended to care for a constant room temperature since the CFD circuits show a
slight temperature dependence of the CFD output signal timing. The power switch of the CFD unit should be turned on at
least one our prior to a measurement.
3b.5.2
Pre-trigger problem
Under certain conditions it can happen that noise accompanying the input signal produces an “early” CFD output signal
(“Pre-trigger”) shortly before the correctly timed signal should come (which is then lost due to internal dead-time). Proper
CFD setting usually ensures that only the bipolar signal’s cross-over can trigger the walk comparator after the leading edge
comparator has opened the AND gate (see Figure 3.4b). Otherwise it may happen that a noise transition before the cross-over
moment triggers the AND gate and produces a wrongly timed (early) CFD timing output. Such a situation can be recognized
by carefully verifying the output signals on the oscilloscope (see Figure 3.21b). If a CFD is used for operating a
RoentDek
delay-line detector or similar device, these pre-trigger events result in a distinct structure in the time (sum) spectrum (see
Figure 3.21b and Figure 3.22b left).
Figure 3.21b: Oscilloscope traces (as in Figure 3.8b left) with less-than-optimal CFD settings which lead to pre-
triggering for some input signals. As the oscilloscope is triggered by the CFD timing output signal here, the monitor
output traces for these pre-trigger events (marked read arrow) appear delayed compared to the properly timed
traces. Right picture: Time sum spectra (linear and log scale) in presence of pre-trigger
events in at least one of the delay-line’s timing electronic channels. Similar “side peaks” can appear
right of the time sum peak (at larger time) if the CFD for the MCP signal produces pre-triggers.
These pre-trigger events are primarily caused by large signals and it usually helps to slightly raise the
Threshold level
for
preventing them. They lead to poorly-timed signals and produce image artefacts on delay-line detectors (see Figure 3.22b). It is
not recommended to simply remove these events by software gates (e.g. a narrow “condition” around the time sum peak)
because this may cause non-uniform imaging properties in case of delay-line read-out.
If pre-trigger events prevail in spite of best effort-setting of the CFD parameters careful it is best to increase the
Threshold level
further and/or the
CFD delay
. Other actions are increasing the
Walk level
, which may slightly reduce resolution) and/or the
CFD fraction
.
