RoentDek CFD1c, Manual

Page: 21 / 25

The Constant Fraction Discriminators CFD8c, CFD7x, CFD4c, CFD1c and CFD1x (11.0.1701.1) Page 21 of 25
Figure 3.25b: Signal traces triggered on CFD timing signal. Upper trace: input signal (as in Figure 3.24b),
lower trace: ramp monitor outputs with
Ramp
switch turned on. Left picture: “pure”
ramp
signal
(obtained without signal input to on A
in
socket), right: with signal connected to A
in
(normal operation)
The ramp monitor output M
Ramp
allows observing the “pure” ramp signal when there is no input on A
in
and the switch labelled
Ramp on is set to on . If the ramp signal is turned off by the switch
*
one can observe the input signal connected to A
in
at the
monitor output M
Ramp
. During normal operation the input signal and the ramp signal are superimposed (“ ramp on”, see Figure
3.25b right). If the ramp starts from a higher level due to the overlaid (positive) input signal it takes longer until it reaches the
reset value.
The higher the input signal at the start moment of the ramp, the longer is the delay between the CFD timing and the stop signal
and the wider is the CFDx signal. This is indicated in Figure 3.26b.
The ramp slope is about -1 V per 12 ns, giving an almost linear correspondence between pulse height and time delay, with a
typically 10 to 20 ns offset for pulse height zero given by the minimum duration of the ramp signal.
If the cable length between A
in
and A
out
is optimally chosen, the start of the “pure” ramp signal will appear at the same time as
the signal maximum. To achieve this, one has to compare the relative timing of the input signal ( ramp off) and the start of the
ramp signal in absence of an input to A
in
which can be observed at the ramp monitor (see Figure 3.24b left and Figure 3.25b left
– the scope markers are set at the same position!). As a thumb rule, the cable length between A
in
and A
out
will be about the
same as the CFD delay cable length (for determining relative pulse height distributions it is not mandatory that the cable length
is exactly set).
Figure 3.26b: upper trace:
CFDx
output, middle trace:
stop
output (with a pulse width set by the
Stop
Width
potentiometer setting), lower trace:
ramp
monitor, all traces triggered on the
stop
signal.
The
stop
signal should be used if there is a spare TDC channel available
*
Note that the CFDx output is turned off while the ramp switch is turned off