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VC7 PCB Layout Guidelines Manual

R31UH0017EU0100 Rev.1.00
Aug 4, 2022

Page 6

Figure 6. 40-LGA Land Pattern Dimensions

Figure 7. Layout Land Pattern Recommendations for RC21008AQ

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Summary of Contents for VersaClock7 PCB

Page 1: ...s information and recommendations to aid in the design and layout of PCB circuitry using VersaClock7 VC7 devices It contains information for generic PCB layout and some particular considerations for VC7 devices Contents 1 Layer Stack Up 2 2 Placement 4 3 Crystal Placement and Handling 4 4 VC7 Device Electrical and Thermal Pad Handling 5 4 1 RC21008A RC31008A 40 LGA 3 5 4 2 RC21012A RC21012A QFN 48...

Page 2: ...l a microstrip Its impedance is determined by a number of factors in the PCB and its stack up arrangement Signal trace width Thickness of the trace thickness of copper layer Distance between the two traces if it is a differential pair Thickness of the dielectric layer between a microstrip and the ground plane under the dielectric layer Dielectric constant Er The following figure shows the calculat...

Page 3: ...n abundant number of copper planes Every signal layer must have an adjacent copper plane layer ground or power plane as return current paths for the signals on that layer Megtron 6 material of different thickness are chosen as the dielectric layers between copper layers Megtron 6 material demonstrates a very low loss at signal frequency 2GHz Given the clock frequencies in VC7 devices FR4 material ...

Page 4: ...citance and interference For the same reason avoid using vias in Xin Xout traces When using capacitors on each crystal pin to set the load capacitance value connect the ground side of the two capacitors close together and close to the IC ground connection The reason is to minimize noise coupling from the ground plane The VC7 devices have internal capacitors It is preferred to use internal capacita...

Page 5: ...ding are included in the following sections 4 1 RC21008A RC31008A 40 LGA 3 Device land pattern is shown below PCB pad width 0 20mm PCB pad length 0 45mm Toe extension beyond package edge 0 05mm Heel extension toward package center 0mm Stencil recommendations Unit mm Thickness 0 125 Aperture for thermal pads 0 84 0 84 x9 each aperture centered on corresponding land pattern of each pad Aperture for ...

Page 6: ...VC7 PCB Layout Guidelines Manual R31UH0017EU0100 Rev 1 00 Aug 4 2022 Page 6 Figure 6 40 LGA Land Pattern Dimensions Figure 7 Layout Land Pattern Recommendations for RC21008AQ ...

Page 7: ...e for thermal pads 2 3 2 3 x4 200um gap between apertures centered on land pad Note We recommend 4x 2 3 2 3 mm solder paste pads instead of a big single pad to avoid excessive copper Aperture for pins 0 20 0 58 x48 heel coincides with package pin heel Via placement and connections Place as many thermal ground vias as fit in each of the 4 split pads This implementation is called via in pad which is...

Page 8: ...ses to the aggregate center of the pattern Four apertures should be aligned with the corresponding vertex of the land pad Aperture for pins 0 22 0 68 x32 heel coincides with package pin heel Via placement and connections Place thermal ground via in space close to each thermal pad Connect each via with a thermal pattern with a trace for a low impedance connection Via size and trace width are per ea...

Page 9: ... changing layers Vias can cause impedance mismatch impairing signal integrity Always route clock signals and any signal in that matter on a layer that has an immediately adjacent ground layer as a return current path As a classic routing pitfall avoid routing a signal across a cut out slit on the reference plane If unavoidable use a stitching capacitor i e 0 1uF to provide a return current path as...

Page 10: ...shown below Figure 12 Adding Phase Compensation Bumps in a Differential Pair If ac coupling capacitors are used place the coupling capacitors in a way that the differential pair can be routed symmetrically as shown below Figure 13 Symmetrical Placement of Series Components in a Differential Pair To avoid a non related component on the board avoid encompassing the component within the differential ...

Page 11: ...tage In the following figure a differential pair changes layers from L1 to L2 leaving a via stub equivalent to the thickness from L2 to L6 assuming a 6 layer board Back drill is to drill off the copper barrel wall of the via from L2 to L6 which is illustrated in the figure There is a cost adder to back drilling Balance the performance requirement versus the cost added Figure 16 Back Drill When a d...

Page 12: ...ions can achieve a noise attenuation across the frequency spectrum as shown below For more information about power supply filtering recommendations see the application note titled VersaClock7 Power Supply Filtering Recommendations The following list contains layout recommendations for power supply traces and power supply filtering Do not overlay power traces from the two power players Do not run p...

Page 13: ...RC21008A RC31008A EVK Layout 3 REN_PSC 4864 01_20201208 4 REN_PSC 4212 05_20190510 5 REN_PSC 4889 02_20220114 6 AN 909 PCB Layout Considerations for Designing IDT VersaClock 3S 5 and 6 Clock Products 7 AN 376 LIU PCB Layout Guide 8 Revision History Revision Date Description 1 00 Aug 4 2022 Initial release ...

Page 14: ...re intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing your application and 3 ensuring your application meets applicable standards and any other safety security or other requirements These resources are subject to change without notice Renesas grants yo...

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