VC7 PCB Layout Guidelines Manual
R31UH0017EU0100 Rev.1.00
Aug 4, 2022
Page 12
6. Power Supply Trace and Power Filtering Layout
Power filtering is one of the most important measures to prevent power supply noises from coupling to the
device outputs, adversely affecting performance, especially when using switched power supplies. Usually we
recommend power supply filtering with a parallel combination of bulk, decoupling, and bypass capacitors as
displayed in the following figure.
Bulk capacitors are usually large size capacitors. They are used for limiting surge currents in the power supply.
In a power supply design, multiple types of regulators (linear and switching) are often used to shift voltage levels
and to reject power supply ripples. Power supply decoupling is achieved with a ferrite bead (and/or a small value
series resistor) and decoupling capacitors forming a pi-shape low pass filter topology.
Bypass capacitors are often small size capacitors and are recommended to place them close to the device to
shunt high-frequency noises to ground. They are used together with bulk decoupling capacitors to provide a
clean power to the device.
A pi-shape power filtering topology used in the VC7 Evaluation Board (see Figure 1 in the
VersaClock7 Power
Supply Filtering Recommendations
) can achieve a noise attenuation across the frequency spectrum as shown
below. For more information about power supply filtering recommendations, see the application note titled
VersaClock7 Power Supply Filtering Recommendations
.
The following list contains layout recommendations for power supply traces and power supply filtering:
■
Do not overlay power traces from the two power players.
■
Do not run power traces parallel/adjacent for long stretches, even if they are of different layers.
■
Cross power traces from different layers at 90 degrees if the crossing is necessary.
■
Keep power traces as thick as possible (while keeping a generous spacing to adjacent power traces) for lower
resistance and inductance.
■
Space power traces further apart where possible.
■
VDDA is most sensitive to noise. VDDD is digital domain supply, thus the noisiest. Use separate power
filtering for VDDA and VDDD, and space them apart in layout.
■
VDDO traces supply different output drivers. Use separate power filtering rail for each VDDO trace. VDDO
traces supplying the same output frequencies can share a single power filtering.
■
Place a bypass capacitor (0.1uF) as close as possible to a power pin. Place the decoupling capacitor on the
same layer as QFN/LGA device.
■
Place bypass capacitors on the same layer as the device.
■
Use a ground via for each bypass capacitor. Do not share a ground via for more than one bypass capacitor.
■
Use low-inductive pad designs
[7]
as shown below.
Figure 17. Decoupling Capacitor Pad Design
