Renesas RX100 Series User Manual Download Page 485

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R01UH0822EJ0100 Rev.1.00

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Jul 31, 2019

RX13T Group

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

19.6.6

Contention between TGR Write Operation and Compare Match

If a compare match occurs in a TGR write cycle, TGR write operation is executed and the compare match signal is also
generated.

Figure 19.125

shows the timing in this case.

Figure 19.125

Contention between TGR Write Operation and Compare Match

19.6.7

Contention between Buffer Register Write Operation and Compare Match

If a compare match occurs in the T2 state in a TGR write cycle, the data before write operation is transferred to TGR by
the buffer operation.

Figure 19.126

shows the timing in this case.

Figure 19.126

Contention between Buffer Register Write Operation and Compare Match

Compare match signal

TCNT

TGR write data

TGR

N + 1

Written by CPU

PCLKB

Compare match signal

Compare match buffer signal

Buffer register write data

Buffer register

TGR

Written by CPU

PCLKB

Summary of Contents for RX100 Series

Page 1: ...se materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Cover ...

Page 2: ...onics with respect to maximum ratings operating power supply voltage range heat dissipation characteristics installation etc Renesas Electronics disclaims any and all liability for any malfunctions failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Ele...

Page 3: ...put signal during power off state as described in your product documentation 4 Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of the ...

Page 4: ... contexts and at the final part of each section and in the section giving usage notes The list of revisions is a summary of major points of revision or addition for earlier versions It does not cover all revised items For details on the revised points see the actual locations in the manual Document Type Contents Document Title Document No Datasheet Overview of hardware and electrical characteristi...

Page 5: ... bit or field is readable Writing to this bit or field has no effect 2 Reserved Use the specified value when writing to this bit or field otherwise the correct operation is not guaranteed 3 Setting prohibited The correct operation is not guaranteed if such a setting is performed X X X Register Address es xxxx xxxxh b7 b6 b5 b4 b3 b2 b1 b0 1 0 4 0 Value after reset x 0 0 0 0 0 0 0 x Undefined Bit S...

Page 6: ...RC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi Z High Impedance IEBus Inter Equipment Bus I O Input Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NC Non Connect PLL Phase Locked Loop PWM Pulse Width Modulation SIM Subscriber Identity Module UART Universal Asynchronous...

Page 7: ...ting Point Status Word FPSW 50 2 2 3 Register Associated with DSP Instructions 53 2 2 3 1 Accumulator ACC 53 2 3 Processor Mode 54 2 3 1 Supervisor Mode 54 2 3 2 User Mode 54 2 3 3 Privileged Instruction 54 2 3 4 Switching between Processor Modes 54 2 4 Data Types 55 2 5 Endian 55 2 5 1 Switching the Endian 55 2 5 2 Access to I O Registers 59 2 5 3 Notes on Access to I O Registers 59 2 5 4 Data Ar...

Page 8: ... 2 1 Boot Mode SCI 77 3 4 Transitions of Operating Modes 78 3 4 1 Operating Mode Transitions Determined by the Mode Setting Pins 78 4 Address Space 79 4 1 Address Space 79 5 I O Registers 81 5 1 I O Register Addresses Address Order 83 6 Resets 94 6 1 Overview 94 6 2 Register Descriptions 96 6 2 1 Reset Status Register 0 RSTSR0 96 6 2 2 Reset Status Register 1 RSTSR1 97 6 2 3 Reset Status Register ...

Page 9: ... 123 8 4 Reset from Voltage Monitor 0 124 8 5 Interrupt and Reset from Voltage Monitoring 1 125 8 6 Interrupt and Reset from Voltage Monitoring 2 127 9 Clock Generation Circuit 129 9 1 Overview 129 9 2 Register Descriptions 131 9 2 1 System Clock Control Register SCKCR 131 9 2 2 System Clock Control Register 3 SCKCR3 133 9 2 3 PLL Control Register PLLCR 134 9 2 4 PLL Control Register 2 PLLCR2 135 ...

Page 10: ...d Design 154 9 7 4 Notes on Resonator Connection Pins 155 10 Clock Frequency Accuracy Measurement Circuit CAC 156 10 1 Overview 156 10 2 Register Descriptions 158 10 2 1 CAC Control Register 0 CACR0 158 10 2 2 CAC Control Register 1 CACR1 159 10 2 3 CAC Control Register 2 CACR2 160 10 2 4 CAC Interrupt Request Enable Register CAICR 161 10 2 5 CAC Status Register CASTR 162 10 2 6 CAC Upper Limit Va...

Page 11: ...de 183 11 6 3 2 Exit from Software Standby Mode 184 11 6 3 3 Example of Software Standby Mode Application 185 11 7 Usage Notes 186 11 7 1 I O Port States 186 11 7 2 Module Stop State of DTC 186 11 7 3 On Chip Peripheral Module Interrupts 186 11 7 4 Write Access to MSTPCRA MSTPCRB and MSTPCRC 186 11 7 5 Timing of WAIT Instructions 186 11 7 6 Rewrite the Register by DTC in Sleep Mode 186 12 Register...

Page 12: ...ster SWINTR 204 14 2 6 DTC Transfer Request Enable Register n DTCERn n interrupt vector number 205 14 2 7 IRQ Control Register i IRQCRi i 0 to 5 206 14 2 8 IRQ Pin Digital Filter Enable Register 0 IRQFLTE0 207 14 2 9 IRQ Pin Digital Filter Setting Register 0 IRQFLTC0 208 14 2 10 Non Maskable Interrupt Status Register NMISR 209 14 2 11 Non Maskable Interrupt Enable Register NMIER 211 14 2 12 Non Ma...

Page 13: ...nction Internal Peripheral Bus 236 15 2 6 Parallel Operation 237 15 2 7 Restrictions 237 15 3 Register Descriptions 238 15 3 1 Bus Error Status Clear Register BERCLR 238 15 3 2 Bus Error Monitoring Enable Register BEREN 238 15 3 3 Bus Error Status Register 1 BERSR1 239 15 3 4 Bus Error Status Register 2 BERSR2 239 15 3 5 Bus Priority Control Register BUSPRI 240 15 4 Bus Error Monitoring Section 24...

Page 14: ...er Information Read Skip Function 265 16 4 2 Transfer Information Write Back Skip Function 266 16 4 2 1 Write Back Skip by Fixing Addresses 266 16 4 2 2 Write Back Skip by the MRA WBDIS Bit 266 16 4 3 Normal Transfer Mode 267 16 4 4 Repeat Transfer Mode 268 16 4 5 Block Transfer Mode 269 16 4 6 Chain Transfer 270 16 4 7 Operation Timing 271 16 4 8 Execution Cycles of the DTC 274 16 4 9 DTC Bus Mas...

Page 15: ...2 to 4 312 18 2 4 P4n Pin Function Control Register P4nPFS n 0 to 7 313 18 2 5 P7n Pin Function Control Register P7nPFS n 0 to 6 314 18 2 6 P9n Pin Function Control Register P9nPFS n 3 4 315 18 2 7 PAn Pin Function Control Register PAnPFS n 2 3 316 18 2 8 PBn Pin Function Control Register PBnPFS n 0 to 7 317 18 2 9 PDn Pin Function Control Register PDnPFS n 3 to 6 318 18 2 10 PE2 Pin Function Cont...

Page 16: ...NTSA 370 19 2 26 Timer Period Data Register TCDRA 370 19 2 27 Timer Period Buffer Register TCBRA 371 19 2 28 Timer Dead Time Data Register TDDRA 371 19 2 29 Timer Dead Time Enable Register TDERA 372 19 2 30 Timer Buffer Transfer Set Register TBTERA 373 19 2 31 Timer Waveform Control Register TWCRA 374 19 2 32 Noise Filter Control Register n NFCRn n 0 to 4 C 375 19 2 33 Noise Filter Control Registe...

Page 17: ...ck Restrictions 483 19 6 3 Note on Period Setting 483 19 6 4 Contention between TCNT Write and Clear Operations 484 19 6 5 Contention between TCNT Write and Increment Operations 484 19 6 6 Contention between TGR Write Operation and Compare Match 485 19 6 7 Contention between Buffer Register Write Operation and Compare Match 485 19 6 8 Contention between Buffer Register Write and TCNT Clear Operati...

Page 18: ...riptions 530 20 2 1 Input Level Control Status Register 1 ICSR1 530 20 2 2 Input Level Control Status Register 3 ICSR3 531 20 2 3 Input Level Control Status Register 4 ICSR4 532 20 2 4 Input Level Control Status Register 6 ICSR6 533 20 2 5 Output Level Control Status Register 1 OCSR1 534 20 2 6 Active Level Setting Register 1 ALR1 535 20 2 7 Software Port Output Enable Register SPOER 537 20 2 8 Po...

Page 19: ...er Writing and Compare Match 562 21 5 3 Conflict between CMCNT Counter Writing and Incrementing 562 22 Independent Watchdog Timer IWDTa 563 22 1 Overview 563 22 2 Register Descriptions 565 22 2 1 IWDT Refresh Register IWDTRR 565 22 2 2 IWDT Control Register IWDTCR 566 22 2 3 IWDT Status Register IWDTSR 569 22 2 4 IWDT Reset Control Register IWDTRCR 570 22 2 5 IWDT Count Stop Control Register IWDTC...

Page 20: ... 15 I2C Mode Register 1 SIMR1 619 23 2 16 I2C Mode Register 2 SIMR2 620 23 2 17 I2C Mode Register 3 SIMR3 621 23 2 18 I2C Status Register SISR 623 23 2 19 SPI Mode Register SPMR 624 23 2 20 Extended Serial Module Enable Register ESMER 625 23 2 21 Control Register 0 CR0 626 23 2 22 Control Register 1 CR1 626 23 2 23 Control Register 2 CR2 627 23 2 24 Control Register 3 CR3 628 23 2 25 Port Control ...

Page 21: ...lock Synchronous Mode 659 23 5 5 Serial Data Reception Clock Synchronous Mode 663 23 5 6 Simultaneous Serial Data Transmission and Reception Clock Synchronous Mode 666 23 6 Operation in Smart Card Interface Mode 667 23 6 1 Sample Connection 667 23 6 2 Data Format Except in Block Transfer Mode 668 23 6 3 Block Transfer Mode 669 23 6 4 Receive Data Sampling Timing and Reception Margin 670 23 6 5 SCI...

Page 22: ...ode 711 23 12 3 Interrupts in Smart Card Interface Mode 712 23 12 4 Interrupts in Simple I2C Mode 713 23 12 5 Interrupt Requests from the Extended Serial Mode Control Section 714 23 13 Usage Notes 715 23 13 1 Setting the Module Stop Function 715 23 13 2 Break Detection and Processing 715 23 13 3 Mark State and Sending Breaks 715 23 13 4 Receive Error Flags and Transmit Operations Clock Synchronous...

Page 23: ...it Data Register ICDRT 755 24 2 16 I2C bus Receive Data Register ICDRR 755 24 2 17 I2C bus Shift Register ICDRS 755 24 3 Operation 756 24 3 1 Communication Data Format 756 24 3 2 Initial Settings 757 24 3 3 Master Transmit Operation 758 24 3 4 Master Receive Operation 761 24 3 5 Slave Transmit Operation 767 24 3 6 Slave Receive Operation 770 24 4 SCL Synchronization Circuit 772 24 5 SDA Output Del...

Page 24: ...unctions When a Reset is Issued or a Condition is Detected 798 24 15 Usage Notes 799 24 15 1 Setting Module Stop Function 799 24 15 2 Notes on Starting Transfer 799 25 CRC Calculator CRC 800 25 1 Overview 800 25 2 Register Descriptions 801 25 2 1 CRC Control Register CRCCR 801 25 2 2 CRC Data Input Register CRCDIR 801 25 2 3 CRC Data Output Register CRCDOR 802 25 3 Operation 803 25 4 Usage Notes 8...

Page 25: ... Channel Selection and Self Diagnosis Without Channel Dedicated Sample and Hold Circuits 841 26 3 2 4 Channel Selection and Self Diagnosis With Channel Dedicated Sample and Hold Circuits 842 26 3 2 5 A D Conversion of Internal Reference Voltage 843 26 3 2 6 A D Conversion in Double Trigger Mode 844 26 3 2 7 A D Conversion in Extended Double Trigger Mode 845 26 3 3 Continuous Scan Mode 847 26 3 3 1...

Page 26: ...rter for Generating Comparator C Reference Voltage DA 883 27 1 Overview 883 27 2 Register Descriptions 884 27 2 1 D A Data Register 0 DADR0 884 27 2 2 D A Control Register DACR 885 27 2 3 Data Register Format Select Register DADPR 885 27 3 Operation 886 27 4 Usage Notes 887 27 4 1 Module Stop Function Setting 887 27 4 2 Operation of the D A Converter in Module Stop State 887 27 4 3 Operation of th...

Page 27: ... Requests 905 29 5 Usage Note 905 29 5 1 Module Stop Function Setting 905 30 RAM 906 30 1 Overview 906 30 2 Operation 906 30 2 1 Low Power Consumption Function 906 31 Flash Memory FLASH 907 31 1 Overview 907 31 2 ROM Area and Block Configuration 908 31 3 E2 DataFlash Area and Block Configuration 909 31 4 Register Descriptions 910 31 4 1 E2 DataFlash Control Register DFLCTL 910 31 4 2 Flash P E Mod...

Page 28: ...1 6 Area Protection 931 31 7 Programming and Erasure 932 31 7 1 Sequencer Modes 932 31 7 1 1 E2 DataFlash Access Disabled Mode 932 31 7 1 2 Read Mode 933 31 7 1 3 P E Modes 933 31 7 2 Mode Transitions 933 31 7 2 1 Transition from E2 DataFlash Access Disable Mode to Read Mode 933 31 7 2 2 Transition from Read Mode to P E Mode 934 31 7 2 3 Transition from P E Mode to Read Mode 936 31 7 3 Software Co...

Page 29: ...Authentication Command 964 31 10 7 1 ID Code Check 964 31 10 8 Program Erase Commands 965 31 10 8 1 User Data Area Program Preparation 965 31 10 8 2 Program 966 31 10 8 3 Data Area Program 967 31 10 8 4 Erase Preparation 968 31 10 8 5 Block Erase 968 31 10 9 Read Check Commands 969 31 10 9 1 Memory Read 969 31 10 9 2 User Area Checksum 970 31 10 9 3 Data Area Checksum 971 31 10 9 4 User Area Blank...

Page 30: ...lock Timing 998 32 4 2 Reset Timing 1002 32 4 3 Timing of Recovery from Low Power Consumption Modes 1003 32 4 4 Control Signal Timing 1005 32 4 5 Timing of On Chip Peripheral Modules 1006 32 5 A D Conversion Characteristics 1017 32 6 Programmable Gain Amplifier Characteristics 1021 32 7 Comparator Characteristics 1022 32 8 D A Conversion Characteristics 1023 32 9 Power On Reset Circuit and Voltage...

Page 31: ...ssistance functions for the A D converter clock frequency accuracy measurement circuit independent watchdog timer RAM test assistance functions using the DOC etc MPC Multiple locations are selectable for I O pins of peripheral functions Up to 4 communications channels SCI with many useful functions 3 channels Asynchronous mode clock synchronous mode smart card interface mode simplified SPI simplif...

Page 32: ...DataFlash Capacity 4 Kbytes Number of erase write cycles 1 000 000 typ MCU operating mode Single chip mode Clock Clock generation circuit Main clock oscillator low speed and high speed on chip oscillator PLL frequency synthesizer and IWDT dedicated on chip oscillator Oscillation stop detection Available Clock frequency accuracy measurement circuit CAC Available Independent settings for the system ...

Page 33: ... compare match or input capture sourced simultaneous counter clear capability Simultaneous writing to multiple timer counters TCNT Simultaneous register input output by synchronous counter operation Buffer operation Cascaded operation 28 interrupt sources Automatic transfer of register data Pulse output modes Toggle PWM complementary PWM reset synchronized PWM Complementary PWM output mode 3 phase...

Page 34: ... data duplicated Assist on analog input disconnection detection A D conversion start conditions A software trigger a trigger from a timer MTU or an external trigger signal Sample and hold function Sample and hold circuit included 3 channels Amplification of input signals by a programmable gain amplifier 3 channels Amplification rate 2 000 times 2 500 times 3 077 times 5 000 times 8 000 times 10 00...

Page 35: ... 6 channels Port output enable 3 POE0 POE8 POE10 POE8 POE10 Compare match timer 2 channels 1 units Independent watchdog timer Available Communication functions Serial communications interfaces SCIg 2 channels SCI1 SCI5 Serial communications interfaces SCIh 1 channel SCI12 I2C bus interface 1 channel 12 bit A D converter 8 channels 5 channels Comparator C 3 channels CRC calculator Available Data op...

Page 36: ...ytes 4 Kbytes 32 MHz 40 to 85 C R5F513T5ADFJ PLQP0032GB A R5F513T3ADFL PLQP0048KB B 64 Kbytes R5F513T3ADFJ PLQP0032GB A R5F513T5AGFL PLQP0048KB B 128 Kbytes 40 to 105 C R5F513T5AGFJ PLQP0032GB A R5F513T3AGFL PLQP0048KB B 64 Kbytes R5F513T3AGFJ PLQP0032GB A R 5 F 5 1 3 T 5 A D F M Package type number of pins and pin pitch FL LFQFP 48 0 5 FJ LQFP 32 0 8 D Operating ambient temperature 40 to 85 C G O...

Page 37: ...s Instruction bus Internal main bus 1 Internal main bus 2 Port D Port E Port A Port B Port 9 Port 7 Port 1 Port 3 Port 4 Port 2 Programmable gain amplifier 3 channels Sample and hold circuit 3 channels E2 DataFlash Internal peripheral buses 1 to 6 ICUb Interrupt controller DTCb Data transfer controller IWDTa Independent watchdog timer CRC CRC cyclic redundancy check calculator SCIg SCIh Serial com...

Page 38: ...RB1 input capture input output compare output PWM output pins MTIOC2A MTIOC2B I O The TGRA2 and TGRB2 input capture input output compare output PWM output pins MTIOC3A MTIOC3B MTIOC3C MTIOC3D I O The TGRA3 to TGRD3 input capture input output compare output PWM output pins MTIOC4A MTIOC4B MTIOC4C MTIOC4D I O The TGRA4 to TGRD4 input capture input output compare output PWM output pins MTIC5U MTIC5V ...

Page 39: ...erter AN000 to AN007 Input Input pins for the analog signals to be processed by the A D converter ADTRG0 Input Input pin for the external trigger signals that start the A D conversion ADST0 Output Output pin for A D conversion status Comparator C CMPC00 CMPC02 CMPC03 Input Analog input pin for CMPC0 CMPC10 CMPC12 CMPC13 Input Analog input pin for CMPC1 CMPC20 CMPC22 Input Analog input pin for CMPC...

Page 40: ...d I O port pins For the pin configuration see the table List of Pins and Pin Functions 48 Pin LFQFP 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 RX13T Group PLQP0048KB B 48 pin LFQFP Upper perspective view P47 P46 P45 P44 P43 P42 P41 P40 AVCC0 AVSS0 P11 P10 P22 P23 P24 VSS VCC P70 P71 P72 P73 P74 P75 P76 P93 P94 PA2 PA3 PB0 PB...

Page 41: ...ew P36 EXTAL P37 XTAL VSS RES VCC PE2 MD PB7 PB6 PB3 VCL P71 P76 P73 P75 VCC P72 P74 P40 AVCC0 AVSS0 P11 P44 P43 P42 P93 P94 PB0 PB1 PB2 VSS P41 29 28 27 26 25 32 31 30 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 5 7 8 1 2 3 4 6 This figure indicates the power supply pins and I O port pins For the pin configuration see the table List of Pins and Pin Functions 32 Pin LQFP Note ...

Page 42: ...C0A CACREF SCK5 SCK12 18 PB2 MTIOC0B MTCLKC ADSM0 TXD5 SMOSI5 SSDA5 SDA0 19 PB1 MTIOC0C MTIC5W MTCLKA RXD5 SMISO5 SSCL5 SCL0 IRQ2 20 PB0 MTIOC0D MTIOC2A MTCLKB TXD12 TXDX12 SIOX12 SMOSI12 SSDA12 21 PA3 MTIOC1B MTIOC2A CTS12 RTS12 SS12 22 PA2 MTIOC1A MTIOC2B CTS5 RTS5 SS5 IRQ4 23 P94 MTIOC2B MTIC5U MTCLKA RXD12 RXDX12 SMISO12 SSCL12 IRQ1 24 P93 MTIOC1A MTIC5V SCK5 SCK12 IRQ0 ADTRG0 25 P76 MTIOC4D 2...

Page 43: ...PB6 MTIOC1B MTIOC3A TXD1 SMOSI1 SSDA1 TXD5 SMOSI5 SSDA5 11 PB3 MTIOC0A CACREF SCK5 SCK12 12 PB2 MTIOC0B MTCLKC ADSM0 TXD5 SMOSI5 SSDA5 SDA0 13 PB1 MTIOC0C MTIC5W MTCLKA RXD5 SMISO5 SSCL5 SCL0 IRQ2 14 PB0 MTIOC0D MTIOC2A MTCLKB TXD12 TXDX12 SIOX12 SMOSI12 SSDA12 15 P94 MTIOC2B MTIC5U MTCLKA RXD12 RXDX12 SMISO12 SSCL12 IRQ1 16 P93 MTIOC1A MTIC5V SCK5 SCK12 IRQ0 ADTRG0 17 P76 MTIOC4D 18 P75 MTIOC4C 1...

Page 44: ...s drawn out by memory access subsequent operations may in fact be executed earlier By adopting an out of order completion of this kind instruction execution is controlled to optimize the number of clock cycles 2 1 Features Minimum instruction execution rate One instruction per clock cycle Address space 4 Gbyte linear Register set of the CPU General purpose Sixteen 32 bit registers Control Nine 32 ...

Page 45: ...upt stack pointer ISP or user stack pointer USP according to the value of the U bit in the PSW register USP User stack pointer ISP Interrupt stack pointer INTB Interrupt table register PC Program counter PSW Processor status word BPC Backup PC BPSW Backup PSW FINTV Fast interrupt vector register R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 SP 1 General purpose registers Control registers ...

Page 46: ...nter SP The stack pointer is switched to operate as the interrupt stack pointer ISP or user stack pointer USP by the value of the stack pointer select bit U in the processor status word PSW 2 2 2 Control Registers This CPU has the following nine control registers Interrupt stack pointer ISP User stack pointer USP Interrupt table register INTB Program counter PC Processor status word PSW Backup PC ...

Page 47: ...e numbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation 2 2 2 2 Interrupt Table Register INTB The interrupt table register INTB specifies the address where the relocatable vector table starts 2 2 2 3 Program Counter PC The program counter PC indicates the address of the instruction being executed b31 b0 ISP Value after reset 0 0 0 0 0 0 0 0 0 0 0 0...

Page 48: ...esult is 0 R W b2 S Sign Flag 0 Result is a positive value or 0 1 Result is a negative value R W b3 O Overflow Flag 0 No overflow has occurred 1 An overflow has occurred R W b15 to b4 Reserved These bits are read as 0 The write value should be 0 R W b16 I 1 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled R W b17 U 1 Stack Pointer Select 0 Interrupt stack pointer ISP is selected 1 User st...

Page 49: ...is switched from supervisor mode to user mode this bit becomes 1 PM Bit Processor Mode Select This bit specifies the processor mode When an exception is accepted this bit becomes 0 IPL 3 0 Bits Processor Interrupt Priority Level The IPL 3 0 bits specify the processor interrupt priority level as one of 16 levels from zero to 15 wherein priority level zero is the lowest and priority level 15 the hig...

Page 50: ... 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 EX EU EZ EO EV DN CE CX CU CZ CO CV RM 1 0 Value after reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 RM 1 0 Floating Point Rounding Mode Setting b1 b0 0 0 Rounding towards the nearest value 0 1 Rounding towards 0 1 0 Rounding towards 1 1 Rounding towards R W b2 CV Invalid Operation Cause Flag 0 No invalid ...

Page 51: ...s to the even alternative Rounding towards 0 An inexact result is rounded to the smallest available absolute value i e in the direction of zero simple truncation Rounding towards An inexact result is rounded to the nearest available value in the direction of positive infinity b8 DN 0 Flush Bit of Denormalized Number 0 A denormalized number is handled as a denormalized number 1 A denormalized numbe...

Page 52: ...ritten by the instruction DN Bit 0 Flush Bit of Denormalized Number When this bit is set to 0 a denormalized number is handled as a denormalized number When this bit is set to 1 a denormalized number is handled as 0 EV Bit Invalid Operation Exception Enable EO Bit Overflow Exception Enable EZ Bit Division by Zero Exception Enable EU Bit Underflow Exception Enable and EX Bit Inexact Exception Enabl...

Page 53: ...ruction Use the MVTACHI and MVTACLO instructions for writing to the accumulator The MVTACHI and MVTACLO instructions write data to the higher order 32 bits bits 63 to 32 and the lower order 32 bits bits 31 to 0 respectively Use the MVFACHI and MVFACMI instructions for reading data from the accumulator The MVFACHI and MVFACMI instructions read data from the higher order 32 bits bits 63 to 32 and th...

Page 54: ...rupt vector register FINTV 2 3 3 Privileged Instruction Privileged instructions can only be executed in supervisor mode Executing a privileged instruction in user mode produces a privileged instruction exception Privileged instructions include the RTFI MVTIPL RTE and WAIT instructions 2 3 4 Switching between Processor Modes Manipulating the processor mode select bit PM in the processor status word...

Page 55: ...al purpose register Rm HH HL LH LL Table 2 1 32 Bit Read Operations when Little Endian has been Selected Operation Address of src Reading a 32 bit unit from address 0 Reading a 32 bit unit from address 1 Reading a 32 bit unit from address 2 Reading a 32 bit unit from address 3 Reading a 32 bit unit from address 4 Address 0 Transfer to LL Address 1 Transfer to LH Transfer to LL Address 2 Transfer t...

Page 56: ...t to address 2 Writing a 32 bit unit to address 3 Writing a 32 bit unit to address 4 Address 0 Transfer from HH Address 1 Transfer from HL Transfer from HH Address 2 Transfer from LH Transfer from HL Transfer from HH Address 3 Transfer from LL Transfer from LH Transfer from HL Transfer from HH Address 4 Transfer from LL Transfer from LH Transfer from HL Transfer from HH Address 5 Transfer from LL ...

Page 57: ...ress 1 Transfer from LH Transfer from LL Address 2 Transfer from LH Transfer from LL Address 3 Transfer from LH Transfer from LL Address 4 Transfer from LH Transfer from LL Address 5 Transfer from LH Transfer from LL Address 6 Transfer from LH Transfer from LL Address 7 Transfer from LH Table 2 8 16 Bit Write Operations when Big Endian has been Selected Operation Address of dest Writing a 16 bit u...

Page 58: ...n Little Endian has been Selected Operation Address of dest Writing an 8 bit unit to address 0 Writing an 8 bit unit to address 1 Writing an 8 bit unit to address 2 Writing an 8 bit unit to address 3 Address 0 Transfer from LL Address 1 Transfer from LL Address 2 Transfer from LL Address 3 Transfer from LL Table 2 12 8 Bit Write Operations when Big Endian has been Selected Operation Address of des...

Page 59: ...structions with B as the size specifier size or with B or UB as the size extension specifier memex With I O registers for which a bus width of 16 bits is indicated use instructions having operands of the same width 16 bits That is access these registers by using instructions with W as the size specifier size or with W or UW as the size extension specifier memex With I O registers for which a bus w...

Page 60: ...truction Codes The allocation of instruction codes to an external space where the endian differs from that of the chip is prohibited If the instruction codes are allocated to the external space they must be allocated to areas where the endian setting is the same as that for the chip 1 bit data Little endian Big endian Address L Address L Byte data Word data Address M Address M 1 Address N Address ...

Page 61: ...ileged instruction exception undefined instruction exception floating point exception non maskable interrupt and reset are allocated to addresses in the range from FFFFFF80h to FFFFFFFFh Figure 2 4 shows the fixed vector table Figure 2 4 Fixed Vector Table Reserved Reserved Privileged instruction exception Reserved Undefined instruction exception Reserved Floating point exception Reserved Reserved...

Page 62: ... table has a vector number from 0 to 255 Each of the INT instructions which act as the sources of unconditional traps is allocated to the vector that has the same number as is specified as the operand of the instruction itself from 0 to 255 The BRK instruction is allocated to the vector with number 0 Furthermore vector numbers from 0 to 255 are allocated to interrupt requests in a fixed way for ea...

Page 63: ...age instruction fetch stage In the IF stage the CPU fetches instructions from the memory As the RX CPU has four 4 byte instruction queues it fetches instructions until the instruction queue is full regardless of the completion of decoding in the D decoding stage 2 D stage decoding stage The CPU decodes instructions DEC in the D stage and converts them into micro operations The CPU reads the regist...

Page 64: ... stage The data read from memory and the other type of data such as the operation result can be written to the register in the same clock cycles Figure 2 6 shows the pipeline configuration and its operation Figure 2 6 Pipeline Configuration and its Operation IF DEC OP OA1 OA2 IF stage BYP RF Pipeline stage Execution processing D stage E stage M1 stage M2 stage One cycle WB stage RW M stage ...

Page 65: ...TR ABS NEG NOT Rd Rs Rd ADC MAX MIN ROTL ROTR XOR IMM Rd Rs Rd ADD IMM Rd Rs Rd IMM Rs Rd Rs Rs2 Rd AND MUL OR SUB IMM Rd Rs Rd Rs Rs2 Rd CMP TST IMM Rs Rs Rs2 NOP ROLC RORC SAT Rd SBB Rs Rd SHAR SHLL SHLR IMM Rd Rs Rd IMM Rs Rd Figure 2 7 1 Arithmetic logic instructions division DIV IMM Rd Rs Rd Figure 2 7 3 to 20 1 DIVU IMM Rd Rs Rd Figure 2 7 2 to 18 1 Data transfer instructions register regist...

Page 66: ...4 E Note Multi cycle instructions DIV DIVU are executed in multiple cycles in the E stage IF D E WB MOV R1 R2 M1 IF D E WB MOV R1 R2 M1 M1 5 stages M2 Note When the load operation is executed to the no wait memory the M1 stage is executed in one cycle In other cases the M stage M1 or M2 is executed in multiple cycles IF D E 4 stages M1 IF D E M1 M1 M1 MOV R2 R1 Note The M1 stage is executed until ...

Page 67: ...U Rs Rd dsp Rs Rd 4 Arithmetic logic instructions multiply and accumulate operation RMPA B 6 7 floor n 4 4 n 4 n Number of processing bytes 1 RMPA W 6 5 floor n 2 4 n 2 n Number of processing words 1 RMPA L 6 4n n Number of processing longwords 1 Arithmetic logic instruction 64 bit signed saturation processing for the RMPA instruction SATR 3 Data transfer instructions memory memory transfer MOV Rs...

Page 68: ...uctions 5 SCMPU 2 4 floor n 4 4 n 4 n Number of comparison bytes 1 SMOVB n 3 6 3 floor n 4 3 n 4 2 3n n Number of transfer bytes 1 SMOVF SMOVU 2 3 floor n 4 3 n 4 n Number of transfer bytes 1 SSTR B 2 floor n 4 n 4 n Number of transfer bytes 1 SSTR W 2 floor n 2 n 2 n Number of transfer words 1 SSTR L 2 n n Number of transfer longwords SUNTIL B SWHILE B 3 3 floor n 4 3 n 4 n Number of comparison b...

Page 69: ...2 13 XCHG Instruction Registers Figure 2 14 XCHG Instruction Memory Source Operand Figure 2 15 Floating Point Operation Instruction Register Register Immediate Register IF D E ADD R1 R2 M1 stall E WB D mop1 load mop2 add Bypass process IF D E MOV R1 R2 M1 Load data Bit manipulation store operation mop1 load mop2 bit manipulation store D E M1 M1 IF D E EMUL R2 R4 WB D mop1 emul 1 mop2 emul 2 WB Wri...

Page 70: ... Cycles is Executed in the E Stage Figure 2 17 When an Instruction which Requires more than One Cycle for its Operand Access is Executed Figure 2 18 When a Branch Instruction is Executed an Unconditional Branch Instruction is Executed or the Condition is Satisfied for a Conditional Branch Instruction Figure 2 19 When the Subsequent Instruction Uses an Operand Read from the Memory IF DIV R1 R2 ADD ...

Page 71: ...t the same timing Figure 2 21 When WB Stages for the Memory Load and for the Operation are Overlapped c When subsequent instruction writes to the same register before the end of memory load Even when the subsequent instruction writes to the same register before the end of memory load the operation processing is pipelined in because the WB stage for the memory load is canceled Figure 2 22 When Subs...

Page 72: ...according to the pipeline processing the approximate time can be calculated in the following methods Count the number of cycles see Table 2 13 and Table 2 14 When the load data is used by the subsequent instruction the number of cycles described as latency is counted as the number of cycles for the memory load instruction For the cycles other than the memory load instruction the number of cycles d...

Page 73: ...ed by N in the table above see Table 2 13 Instructions that are Converted into a Single Micro Operation and Table 2 14 Instructions that are Converted into Multiple Micro Operations The timing of interrupt acceptance depends on the state of the pipelines For more information on this refer to section 13 3 1 Acceptance Timing and Saved PC Value Table 2 15 Numbers of Cycles for Response to Interrupts...

Page 74: ...m the reset state and the operating mode selected at that time For details on each of the operating modes see section 3 3 Details of Operating Modes Note 1 Do not change the level on the MD pin while the MCU is operating The endian is selectable in single chip mode Endian is set by the MDE MDE 2 0 bits in the option setting memory For the correspondence between the setting and endian see Table 3 2...

Page 75: ...6 b5 b4 b3 b2 b1 b0 MD Value after reset 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 1 1 Note 1 This affects the level on the MD pin at the time of release from the reset state Bit Symbol Bit Name Description R W b0 MD MD Pin Status Flag 0 The MD pin is low 1 The MD pin is high R b7 to b1 Reserved These bits are read as 0 R b8 Reserved The read value is undefined R b15 to b9 Reserved These bits are read as 0 ...

Page 76: ...his bit during access to the RAM When accessing the RAM immediately after changing the RAME bit from 0 RAM disabled to 1 RAM enabled make sure that the RAME bit is 1 before the access Address es 0008 0008h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RAME Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R W b0 RAME RAM Enable 0 The RAM is disabled 1 The RA...

Page 77: ...et state 3 3 2 Boot Mode In this mode the on chip flash memory modifying program boot program stored in a dedicated area within the MCU operates The on chip flash memory ROM can be modified from outside the MCU by using a universal asynchronous receiver transmitter SCI1 For details see section 31 Flash Memory FLASH When a reset is released while the MD pin is low boot mode is selected 3 3 2 1 Boot...

Page 78: ...rating Modes 3 4 1 Operating Mode Transitions Determined by the Mode Setting Pins Figure 3 1 shows operating mode transitions determined by the settings of the MD pin Figure 3 1 Mode Setting Pin Levels and Operating Modes MD High RES High RES Low RES Low MD Low RES High Single chip mode Reset Boot mode SCI ...

Page 79: ...ddress Space 4 1 Address Space This MCU has a 4 Gbyte address space consisting of the range of addresses from 0000 0000h to FFFF FFFFh That is linear access to an address space of up to 4 Gbytes is possible and this contains both program and data areas Figure 4 1 shows the memory maps ...

Page 80: ... registers 0000 0000h 0000 3000h 0008 0000h 0010 0000h 0010 1000h 007F C000h 007F C500h 007F FC00h 0080 0000h FFFE 0000h FFFF FFFFh Note 1 The address space in boot mode is the same as the address space in single chip mode Note 2 The capacity of ROM differs depending on the products Note See Table 1 3 List of Products for the product type name Note 3 Reserved areas should not be accessed ROM bytes...

Page 81: ...ent instruction to be executed before the post update I O register value is reflected on the operation As described in the following examples special care is required for the cases in which the subsequent instruction must be executed after the post update I O register value is actually reflected Examples of cases requiring special care The subsequent instruction must be executed while an interrupt...

Page 82: ...The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK or FCLK or bus access timing In the peripheral function unit when the frequency ratio of ICLK is equal to or greater than that of PCLK or FCLK the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of PCL...

Page 83: ...0A2h SYSTEM Main Clock Oscillator Wait Control Register MOSCWTCR 8 8 3 ICLK section 9 0008 00C0h SYSTEM Reset Status Register 2 RSTSR2 8 8 3 ICLK section 6 0008 00C2h SYSTEM Software Reset Register SWRR 16 16 3 ICLK section 6 0008 00E0h SYSTEM Voltage Monitoring 1 Circuit Control Register 1 LVD1CR1 8 8 3 ICLK section 8 0008 00E1h SYSTEM Voltage Monitoring 1 Circuit Status Register LVD1SR 8 8 3 ICL...

Page 84: ...ction 27 0008 80C5h DA Data Register Format Select Register DADPR 8 8 2 or 3 PCLKB section 27 0008 80C6h DA D A A D Synchronous Start Control Register DAADSCR 8 8 2 or 3 PCLKB section 27 0008 8280h CRC CRC Control Register CRCCR 8 8 2 or 3 PCLKB section 25 0008 8281h CRC CRC Data Input Register CRCDIR 8 8 2 or 3 PCLKB section 25 0008 8282h CRC CRC Data Output Register CRCDOR 16 16 2 or 3 PCLKB sec...

Page 85: ...PCLKB section 26 0008 90DFh S12AD A D Sampling State Register O ADSSTRO 8 8 2 or 3 PCLKB section 26 0008 90E0h S12AD A D Sampling State Register 0 ADSSTR0 8 8 2 or 3 PCLKB section 26 0008 90E1h S12AD A D Sampling State Register 1 ADSSTR1 8 8 2 or 3 PCLKB section 26 0008 90E2h S12AD A D Sampling State Register 2 ADSSTR2 8 8 2 or 3 PCLKB section 26 0008 90E3h S12AD A D Sampling State Register 3 ADSS...

Page 86: ...3 PCLKB section 23 0008 A0AEh SCI5 Transmit Data Register HL TDRHL 16 16 2 or 3 PCLKB section 23 0008 A0AEh SCI5 Transmit Data Register H TDRH 8 8 2 or 3 PCLKB section 23 0008 A0AFh SCI5 Transmit Data Register L TDRL 8 8 2 or 3 PCLKB section 23 0008 A0B0h SCI5 Receive Data Register HL RDRHL 16 16 2 or 3 PCLKB section 23 0008 A0B0h SCI5 Receive Data Register H RDRH 8 8 2 or 3 PCLKB section 23 0008 ...

Page 87: ...008 B329h SCI12 Control Field 0 Data Register CF0DR 8 8 2 or 3 PCLKB section 23 0008 B32Ah SCI12 Control Field 0 Compare Enable Register CF0CR 8 8 2 or 3 PCLKB section 23 0008 B32Bh SCI12 Control Field 0 Receive Data Register CF0RR 8 8 2 or 3 PCLKB section 23 0008 B32Ch SCI12 Primary Control Field 1 Data Register PCF1DR 8 8 2 or 3 PCLKB section 23 0008 B32Dh SCI12 Secondary Control Field 1 Data Re...

Page 88: ...LKB section 17 0008 C062h PORT2 Port Mode Register PMR 8 8 2 or 3 PCLKB section 17 0008 C063h PORT3 Port Mode Register PMR 8 8 2 or 3 PCLKB section 17 0008 C067h PORT7 Port Mode Register PMR 8 8 2 or 3 PCLKB section 17 0008 C069h PORT9 Port Mode Register PMR 8 8 2 or 3 PCLKB section 17 0008 C06Ah PORTA Port Mode Register PMR 8 8 2 or 3 PCLKB section 17 0008 C06Bh PORTB Port Mode Register PMR 8 8 2...

Page 89: ...8 0008 C165h MPC P45 Pin Function Control Register P45PFS 8 8 2 or 3 PCLKB section 18 0008 C166h MPC P46 Pin Function Control Register P46PFS 8 8 2 or 3 PCLKB section 18 0008 C167h MPC P47 Pin Function Control Register P47PFS 8 8 2 or 3 PCLKB section 18 0008 C178h MPC P70 Pin Function Control Register P70PFS 8 8 2 or 3 PCLKB section 18 0008 C179h MPC P71 Pin Function Control Register P71PFS 8 8 2 ...

Page 90: ... 1 TMDR1 8 8 16 4 or 5PCLKB section 19 0009 5203h MTU4 Timer Mode Register 1 TMDR1 8 8 4 or 5PCLKB section 19 0009 5204h MTU3 Timer I O Control Register H TIORH 8 8 16 32 4 or 5PCLKB section 19 0009 5205h MTU3 Timer I O Control Register L TIORL 8 8 4 or 5PCLKB section 19 0009 5206h MTU4 Timer I O Control Register H TIORH 8 8 16 4 or 5PCLKB section 19 0009 5207h MTU4 Timer I O Control Register L TI...

Page 91: ...or 5PCLKB section 19 0009 5284h MTU Timer Read Write Enable Register A TRWERA 8 8 4 or 5PCLKB section 19 0009 5290h MTU0 Noise Filter Control Register 0 NFCR0 8 8 4 or 5PCLKB section 19 0009 5291h MTU1 Noise Filter Control Register 1 NFCR1 8 8 4 or 5PCLKB section 19 0009 5292h MTU2 Noise Filter Control Register 2 NFCR2 8 8 4 or 5PCLKB section 19 0009 5293h MTU3 Noise Filter Control Register 3 NFCR...

Page 92: ...ection 19 0009 5496h MTU5 Timer I O Control Register V TIORV 8 8 4 or 5PCLKB section 19 0009 54A0h MTU5 Timer Counter W TCNTW 16 16 32 4 or 5PCLKB section 19 0009 54A2h MTU5 Timer General Register W TGRW 16 16 4 or 5PCLKB section 19 0009 54A4h MTU5 Timer Control Register W TCRW 8 8 4 or 5PCLKB section 19 0009 54A5h MTU5 Timer Control Register 2W TCR2W 8 8 4 or 5PCLKB section 19 0009 54A6h MTU5 Tim...

Page 93: ...ister H FRBH 16 16 2 or 3 FCLK section 31 007F FF80h FLASH Flash P E Mode Control Register FPMCR 8 8 2 or 3 FCLK section 31 007F FF81h FLASH Flash Area Select Register FASR 8 8 2 or 3 FCLK section 31 007F FF82h FLASH Flash Processing Start Address Register L FSARL 16 16 2 or 3 FCLK section 31 007F FF84h FLASH Flash Processing Start Address Register H FSARH 8 8 2 or 3 FCLK section 31 007F FF85h FLA...

Page 94: ...et0 Vdet1 and Vdet2 see section 8 Voltage Detection Circuit LVDAb and section 32 Electrical Characteristics Table 6 1 Reset Names and Sources Reset Name Source RES pin reset Voltage input to the RES pin is driven low Power on reset VCC rises voltage monitored VPOR 1 Voltage monitoring 0 reset VCC falls voltage monitored Vdet0 1 Voltage monitoring 1 reset VCC falls voltage monitored Vdet1 1 Voltage...

Page 95: ...ring 2 Reset Software Reset The power on reset detect flag RSTSR0 PORF Register related to the cold start warm start determination flag RSTSR1 CWSF 1 Voltage monitoring 0 reset detect flag RSTSR0 LVD0RF The independent watchdog timer reset detect flag RSTSR2 IWDTRF Registers related to the independent watchdog timer IWDTRR IWDTCR IWDTSR IWDTRCR IWDTCSTPR ILOCOCR The voltage monitoring 1 reset dete...

Page 96: ...e Monitoring 1 Reset Detect Flag The LVD1RF flag indicates that VCC voltage has fallen below Vdet1 Setting condition When Vdet1 level VCC voltage is detected Clearing conditions When a reset listed in Table 6 2 occurs When LVD1RF is read as 1 and then 0 is written to LVD1RF Address es 0008 C290h b7 b6 b5 b4 b3 b2 b1 b0 LVD2R F LVD1R F LVD0R F PORF Value after reset 0 0 0 0 0 1 0 1 0 1 0 1 Bit Symb...

Page 97: ...wer on reset has caused the reset processing cold start or a reset signal input during operation has caused the reset processing warm start CWSF Flag Cold Warm Start Determination Flag The CWSF flag indicates the type of reset processing cold start or warm start The CWSF flag is initialized at a power on Setting condition When 1 is written through programming it is not set to 0 even when 0 is writ...

Page 98: ...set Detect Flag The SWRF flag indicates that a software reset has occurred Setting condition When a software reset occurs Clearing conditions When a reset listed in Table 6 2 occurs When SWRF is read as 1 and then 0 is written to SWRF Address es 0008 00C0h b7 b6 b5 b4 b3 b2 b1 b0 SWRF IWDTR F Value after reset 0 0 0 0 0 0 1 0 0 1 Bit Symbol Bit Name Description R W b0 IWDTRF Independent Watchdog T...

Page 99: ... PRC1 bit to 1 write enabled before rewriting this register Address es 0008 00C2h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SWRR 15 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b15 to b0 SWRR 15 0 Software Reset Writing A501h resets the LSI These bits are read as 0000h R W ...

Page 100: ...2 Electrical Characteristics After VCC has exceeded VPOR and the specified period power on reset time has elapsed the internal reset is canceled and the CPU starts the reset exception handling The power on reset time is a stabilization period for the external power supply and the MCU circuit After a power on reset has been generated the PORF flag in RSTSR0 is set to 1 The PORF flag is initialized ...

Page 101: ... Set by OFS1 LVDAS Power on reset state Voltage monitoring 0 reset state Note For details on the electrical characteristics see the Electrical Characteristics section Note 1 Vdet0 indicates the detection level for a voltage monitoring 0 reset and VPOR indicates the detection level for a power on reset Note 2 Ensure that the voltage on the RES pin is always at least VIH Note 3 tPOR indicates the pe...

Page 102: ...2 circuit control register 0 LVD2CR0 the RSTSR0 LVD2RF flag is set to 1 and the voltage detection circuit generates a voltage monitoring 2 reset if VCC falls to or below Vdet2 Timing for release from the voltage monitoring 1 reset state is selectable with the voltage monitoring 1 reset negation select bit LVD1RN in the LVD1CR0 register When the LVD1CR0 LVD1RN bit is 0 and VCC has fallen to or belo...

Page 103: ... the CPU starts the reset exception handling For details on the independent watchdog timer reset see section 22 Independent Watchdog Timer IWDTa 6 3 5 Software Reset The software reset is an internal reset generated by the software reset circuit When A501h is written to SWRR a software reset is generated When the internal reset time tRESW2 has elapsed after the software reset is generated the inte...

Page 104: ...rocessing warm start The CWSF flag in RSTSR1 is set to 0 when a power on reset occurs cold start otherwise the flag is not set to 0 The flag is set to 1 when 1 is written to it through programming it is not set to 0 even when 0 is written Figure 6 3 shows an example of cold warm start determination operation Figure 6 3 Example of Cold Warm Start Determination Operation VPOR External voltage VCC RE...

Page 105: ... example of the flow to identify a reset generation source Figure 6 4 Example of Reset Generation Source Determination Flow Software reset RES pin reset Reset exception handling Voltage monitoring 0 reset Power on reset Voltage monitoring 1 reset Voltage monitoring 2 reset Independent watchdog timer reset RSTSR2 IWDTRF 1 No Yes Yes No RSTSR2 SWRF 1 RSTSR0 LVD0RF 1 Yes No RSTSR0 LVD2RF 1 Yes No RST...

Page 106: ...provided for selecting the state of the microcontroller after a reset The option setting memory is allocated in the ROM Figure 7 1 shows the option setting memory area Figure 7 1 Option Setting Memory Area Addresses 4 bytes Option function select register 0 OFS0 FFFF FF80h to FFFF FF83h Endian select register MDE FFFF FF8Ch to FFFF FF8Fh Option function select register 1 OFS1 FFFF FF88h to FFFF FF...

Page 107: ...atically activated in auto start mode after a reset 1 IWDT is halted after a reset R b3 b2 IWDTTOPS 1 0 IWDT Timeout Period Select b3 b2 0 0 128 cycles 007Fh 0 1 512 cycles 01FFh 1 0 1024 cycles 03FFh 1 1 2048 cycles 07FFh R b7 to b4 IWDTCKS 3 0 IWDT Clock Frequency Division Ratio Select b7 b4 0 0 0 0 No division 0 0 1 0 Divide by 16 0 0 1 1 Divide by 32 0 1 0 0 Divide by 64 1 1 1 1 Divide by 128 ...

Page 108: ... select the position of the end of the window for the down counter as 0 25 50 or 75 of the value being counted by the counter The value of the window end position must be smaller than the value of the window start position window start position window end position If the value for the window end position is greater than the value for the window start position only the value for the window start po...

Page 109: ...illation stabilization Note that even if the HOCOEN bit is set to 0 the system clock source is not switched to HOCO The system clock source is switched to HOCO only by modifying the clock source select bits SCKCR3 CKSEL 2 0 from the CPU Also when the HOCOEN bit is set to 0 the HOCO oscillation stabilization time tHOCO is secured by hardware so the clock with the accuracy of the HOCO oscillation fr...

Page 110: ...rasing the block including the MDE register the MDE register value becomes FFFF FFFFh MDE 2 0 Bits Endian Select These bits select little endian or big endian for the CPU Address es OFSM MDE FFFF FF80h b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Value after reset The value set by the user 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MDE 2 0 Value after reset The valu...

Page 111: ...e the option setting memory is allocated in the ROM values cannot be written by executing instructions Write appropriate values when writing the program An example of the settings is shown below To set FFFF FFF8h in the OFS0 register ORG 0FFFFFF8CH LWORD 0FFFFFFF8H Note Programming formats vary depending on the compiler Refer to the compiler manual for details ...

Page 112: ...ltage Vdet0 Vdet1 Vdet2 Detection target Voltage drops past Vdet0 When voltage rises above or drops below Vdet1 When voltage rises above or drops below Vdet2 Detection voltage Voltage selectable from 3 levels using OFS1 Voltage selectable from 9 levels using the LVDLVLR LVD1LVL 3 0 bits Voltage selectable from 4 levels using the LVDLVLR LVD2LVL 1 0 bits Monitoring flag Not available LVD1SR LVD1MON...

Page 113: ... Bits in OFS1 Voltage detection 1 signal Internal reference voltage for detecting Vdet1 Level selection circuit 9 levels LVD1CMPE LVD2E Vdet2 Voltage detection 2 signal Internal reference voltage for detecting Vdet2 Level selection circuit 4 levels LVD2CMPE Analog noise filter Analog noise filter LVDAS VCC Vdet0 Voltage detection 0 reset signal Internal reference voltage for detecting Vdet0 Level ...

Page 114: ...negation LVD1RN 0 LVD1RN 1 LVD1RI LVD1RIE b1 LVD1SR register LVD1MON bit Voltage monitoring 1 non maskable interrupt signal Voltage monitoring 1 reset signal low is valid LVD1E Voltage detection 1 signal Analog noise filter Voltage detection 2 circuit Voltage detection 2 signal will be high when the LVD2E bit is 0 disabled The setting of the LVD2DET bit will be 0 if 0 undetected is written by the ...

Page 115: ... b1 b0 LVD1IR QSEL LVD1IDTSEL 1 0 Value after reset 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R W b1 b0 LVD1IDTSEL 1 0 Voltage Monitoring 1 Interrupt Generation Condition Select b1 b0 0 0 When VCC Vdet1 rise is detected 0 1 When VCC Vdet1 drop is detected 1 0 When drop and rise are detected 1 1 Setting prohibited R W b2 LVD1IRQSEL Voltage Monitoring 1 Interrupt Type Select 0 Non maskable int...

Page 116: ...RIE can be set to 1 enabled again after a period of two or more cycles of PCLKB has elapsed With read access to an I O register which access cycle number is defined by PCLKB two or more cycles of PCLKB may have to be secured as waiting time LVD1MON Flag Voltage Monitoring 1 Signal Monitor Flag The LVD1MON flag is enabled when the LVCMPCR LVD1E bit is 1 voltage detection 1 circuit enabled and the L...

Page 117: ... QSEL LVD2IDTSEL 1 0 Value after reset 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R W b1 b0 LVD2IDTSEL 1 0 Voltage Monitoring 2 Interrupt Generation Condition Select b1 b0 0 0 When VCC Vdet2 rise is detected 0 1 When VCC Vdet2 drop is detected 1 0 When drop and rise are detected 1 1 Setting prohibited R W b2 LVD2IRQSEL Voltage Monitoring 2 Interrupt Type Select 0 Non maskable interrupt 1 Mask...

Page 118: ...LVD2RIE can be set to 1 enabled again after a period of two or more cycles of PCLKB has elapsed With read access to an I O register which access cycle number is defined by PCLKB two or more cycles of PCLKB may have to be secured as waiting time LVD2MON Flag Voltage Monitoring 2 Signal Monitor Flag The LVD2MON flag is enabled when the LVCMPCR LVD2E bit is 1 voltage detection 2 circuit enabled and t...

Page 119: ...ble When using voltage detection 2 interrupt reset or the LVD2SR LVD2MON flag set the LVD2E bit to 1 The voltage detection 2 circuit starts once Td E A passes after the LVD2E bit value is changed from 0 to 1 Address es 0008 C297h b7 b6 b5 b4 b3 b2 b1 b0 LVD2E LVD1E Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b4 to b0 Reserved These bits are read as 0 The write value shoul...

Page 120: ...ed for voltage detection For details on the voltage detection level range refer to section 32 Electrical Characteristics Address es 0008 C298h b7 b6 b5 b4 b3 b2 b1 b0 LVD2LVL 1 0 LVD1LVL 3 0 Value after reset 0 0 0 0 0 1 1 1 Bit Symbol Bit Name Description R W b3 to b0 LVD1LVL 3 0 Voltage Detection 1 Level Select Standard voltage during drop in voltage b3 b0 0 0 0 0 4 29 V 0 0 0 1 4 14 V 0 0 1 0 4...

Page 121: ...r VCC Vdet1 is detected Do not set the LVD1RN bit to 1 negation follows a stabilization time after assertion of the voltage monitoring 1 reset Address es 0008 C29Ah b7 b6 b5 b4 b3 b2 b1 b0 LVD1R N LVD1RI LVD1C MPE LVD1RI E Value after reset 1 0 0 0 X 0 0 0 x Undefined Bit Symbol Bit Name Description R W b0 LVD1RIE Voltage Monitoring 1 Interrupt Reset Enable 0 Disabled 1 Enabled R W b1 Reserved Thi...

Page 122: ...after VCC Vdet2 is detected Do not set the LVD2RN bit to 1 negation follows a stabilization time after assertion of the voltage monitoring 2 reset Address es 0008 C29Bh b7 b6 b5 b4 b3 b2 b1 b0 LVD2R N LVD2RI LVD2C MPE LVD2RI E Value after reset 1 0 0 0 X 0 0 0 x Undefined Bit Symbol Bit Name Description R W b0 LVD2RIE Voltage Monitoring 2 Interrupt Reset Enable 0 Disabled 1 Enabled R W b1 Reserved...

Page 123: ... 2 Set the LVCMPCR LVD1E bit to 1 voltage detection 1 circuit enabled 3 After waiting for Td E A set the LVD1CR0 LVD1CMPE bit to 1 voltage monitoring 1 circuit comparison results output enabled 8 3 3 Monitoring Vdet2 After making the following settings the LVD2SR LVD2MON flag can be used to monitor the results of comparison by voltage monitor 2 1 Specify the detection voltage by setting the LVDLVL...

Page 124: ...ES pin reset RSTSR0 PORF Voltage detection 0 signal Low is valid RSTSR0 LVD0RF Vdet0 1 LVD0 enable disable signal Low is valid 3 Power on reset state Voltage monitoring 0 reset state Set by OFS1 LVDAS VCC 0 VCC 0 VCC 0 VCC 0 VCC 0 VCC 0 VCC 0 Note For details on the electrical characteristics see the Electrical Characteristics section Note 1 Vdet0 indicates the detection level for a voltage monito...

Page 125: ... is with the setting to select the voltage monitoring 1 reset LVD1CR0 LVD1RI 1 proceed through all steps from 1 to 5 Table 8 2 Procedures for Setting Bits Related to the Voltage Monitoring 1 Interrupt and Voltage Monitoring 1 Reset Step Voltage Monitoring 1 Interrupt Voltage Monitoring 1 Reset 1 1 Select the detection voltage by setting the LVDLVLR LVD1LVL 3 0 bits 2 1 Set the LVD1CR0 LVD1RI bit t...

Page 126: ...Cmin LVD1DET bit Voltage monitoring 1 interrupt request LVD1DET bit LVD1DET bit Voltage monitoring 1 interrupt request Set to 0 by a program Set to 0 by a program Set to 0 by a program Voltage monitoring 1 interrupt request LVD1IDTSEL 1 0 bits are set to 10b when drop and rise are detected LVD1IDTSEL 1 0 bits are set to 00b when rise is detected LVD1IDTSEL 1 0 bits are set to 01b when drop is dete...

Page 127: ...is with the setting to select the voltage monitoring 2 reset LVD2CR0 LVD2RI 1 proceed through all steps from 1 to 5 Table 8 4 Procedures for Setting Bits Related to the Voltage Monitoring 2 Interrupt and Voltage Monitoring 2 Reset Step Voltage Monitoring 2 Interrupt Voltage Monitoring 2 Reset 1 1 Select the detection voltage by setting the LVDLVLR LVD2LVL 1 0 bits 2 1 Set the LVD2CR0 LVD2RI bit to...

Page 128: ...Cmin LVD2DET bit Voltage monitoring 2 interrupt request LVD2DET bit LVD2DET bit Voltage monitoring 2 interrupt request Set to 0 by a program Set to 0 by a program Set to 0 by a program Voltage monitoring 2 interrupt request LVD2IDTSEL 1 0 bits are set to 10b when drop and rise are detected LVD2IDTSEL 1 0 bits are set to 00b when rise is detected LVD2IDTSEL 1 0 bits are set to 01b when drop is dete...

Page 129: ...ock FCLK to be supplied to the FlashIF Generates the CAC clock CACCLK to be supplied to the CAC Generates the IWDT dedicated low speed clock IWDTCLK to be supplied to the IWDT Operating frequencies 1 ICLK 32 MHz max 2 PCLKB 32 MHz max PCLKD 32 MHz max FCLK 1 to 32 MHz for programming and erasing the ROM and E2 DataFlash 32 MHz max for reading from the E2 DataFlash CACCLK Same frequency as each osc...

Page 130: ...nput EXTAL XTAL SCKCR ICK 3 0 System clock ICLK To CPU DTC ROM and RAM Peripheral module clock PCLKB PCLKD To peripheral module SCKCR IWDT dedicated low speed clock IWDT dedicated clock IWDTCLK To IWDT Main clock oscillator PLL circuit Frequency divider FCK 3 0 FlashIF clock FCLK To FlashIF SCKCR Selector CKSEL 2 0 SCKCR3 HOCO clock LOCO clock Main clock Frequency divider PLIDIV 1 0 PLLCR STC 5 0 ...

Page 131: ... b0 PCKD 3 0 Peripheral Module Clock D PCLKD Select b3 b0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 4 0 0 1 1 1 8 0 1 0 0 1 16 0 1 0 1 1 32 0 1 1 0 1 64 Settings other than above are prohibited R W b7 to b4 Reserved These bits are read as 0 The write value should be 0 R W b11 to b8 PCKB 3 0 Peripheral Module Clock B PCLKB Select b11 b8 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 4 0 0 1 1 1 8 0 1 0 0 1 16 0 1 0 1 1 32 ...

Page 132: ...D 3 0 Bits Peripheral Module Clock D PCLKD Select These bits select the frequency of peripheral module clock D PCLKD PCKB 3 0 Bits Peripheral Module Clock B PCLKB Select These bits select the frequency of peripheral module clock B PCLKB ICK 3 0 Bits System Clock ICLK Select These bits select the frequency of the system clock ICLK FCK 3 0 Bits FlashIF Clock FCLK Select These bits select the frequen...

Page 133: ...eed on chip oscillator LOCO high speed on chip oscillator HOCO the main clock oscillator and the PLL circuit Transitions to clock sources which are not in operation are prohibited Address es 0008 0026h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CKSEL 2 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b7 to b0 Reserved These bits are read as 0 The w...

Page 134: ...on factor of the PLL circuit Set these bits so that the PLL oscillation frequency is within the range of 24 MHz to 32 MHz Address es 0008 0028h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 STC 5 0 PLIDIV 1 0 Value after reset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 PLIDIV 1 0 PLL Input Frequency Division Ratio Select b1 b0 0 0 1 0 1 1 2 1 0 1 4 1 1 Settin...

Page 135: ...operation After stopping the PLL confirm that the OSCOVFSR PLOVF bit is 0 before restarting the PLL Confirm that the PLL is operating and that the OSCOVFSR PLOVF bit is 1 before stopping the PLL Regardless of whether or not it is selected as the system clock confirm that the OSCOVFSR PLOVF bit is 1 before executing a WAIT instruction to place the MCU in software standby mode After stopping the PLL...

Page 136: ...estarting the main clock oscillator Confirm that the main clock oscillator is operating and that the OSCOVFSR MOOVF bit is 1 before stopping the main clock oscillator Regardless of whether or not it is selected as the system clock confirm that the OSCOVFSR MOOVF bit is 1 and execute a WAIT instruction in order to operate the main clock oscillator and place the MCU in software standby mode After st...

Page 137: ...arting the LOCO after it has been stopped allow at least five cycles of the LOCO as an interval over which it is still stopped Ensure that oscillation by the LOCO is stable when making the setting to stop the LOCO Regardless of whether or not it is selected as the system clock ensure that oscillation by the LOCO is stable before executing a WAIT instruction to place the chip on software standby Wh...

Page 138: ...dicated on chip oscillator After the setting of the ILCSTP bit has been changed so that the IWDT dedicated on chip oscillator operates supply of the clock is started the MCU internally after a fixed time corresponding to the IWDT dedicated clock oscillation stabilization time tILOCO has elapsed If the IWDT dedicated clock is to be used only start using the oscillator after this wait time has elaps...

Page 139: ... fixed time is also required for oscillation to stop after the setting to stop the oscillator Accordingly take note of the following limitations when starting and stopping the oscillator After stopping the HOCO confirm that the OSCOVFSR HCOVF flag is 0 before restarting the HOCO Confirm that the HOCO is operating and that the OSCOVFSR HCOVF flag is 1 before stopping the HOCO Regardless of whether ...

Page 140: ...ck oscillator is completed PLOVF Flag PLL Clock Oscillation Stabilization Flag This flag indicates whether oscillation of the PLL clock is stable Setting condition After the PLLCR2 PLLEN is set to 0 PLL is operating when the PLLEN bit is 1 PLL is stopped the MOOVF flag becomes 1 the PLL clock oscillation stabilization time tPLL has elapsed and supply of the PLL clock is started to the MCU internal...

Page 141: ...f 1041 Jul 31 2019 RX13T Group 9 Clock Generation Circuit supply of the HOCO clock is started to the MCU internally Clearing condition After the HOCOCR HCSTP bit is set to 1 the processing to stop the oscillation of the HOCO is completed ...

Page 142: ... cannot be stopped while the oscillation stop detection function is enabled writing 1 LOCO is stopped to the LOCOCR LCSTP bit is invalid When the oscillation stop detection flag in the oscillation stop detection status register OSTDSR OSTDF is 1 main clock oscillation stop has been detected writing 0 to the OSTDE bit is invalid When the OSTDE bit is 1 a transition cannot be made to software standb...

Page 143: ...s set to 0 while the main clock oscillation is stopped the OSTDF flag becomes 0 and then returns to 1 When the main clock oscillator 010b or PLL 100b is selected by the clock source select bits in system clock control register 3 SCKCR3 CKSEL 2 0 the OSTDF flag cannot be modified to 0 The OSTDF flag should be set to 0 after switching the clock source to a source other than the main clock oscillator...

Page 144: ...elapsed supply of the main clock is started to the MCU internally and the OSCOVFSR MOOVF flag becomes 1 If the set wait time is short supply of the main clock is started before oscillation of the clock becomes stable Only rewrite the MOSCWTCR register when the MOSCCR MOSTP bit is 1 and the OSCOVFSR MOOVF flag is 0 Do not rewrite this register under any other conditions Address es 0008 00A2h b7 b6 ...

Page 145: ...Bit Main Clock Oscillator Switch This bit selects the oscillation source of the main clock oscillator Address es 0008 C293h b7 b6 b5 b4 b3 b2 b1 b0 MOSEL MODR V21 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b4 to b0 Reserved These bits are read as 0 The write value should be 0 R W b5 MODRV21 Main Clock Oscillator Drive Capability Switch 0 1 MHz or higher and lower than 10...

Page 146: ...ency Adjustment Set the frequency adjustment value for the IWDT dedicated on chip oscillator The setting range is from 0 00h to 31 1Fh by binary numbers The greater the set value is the higher the frequency is The frequency is adjusted under certain conditions before shipment so the value after reset varies with the chip After a reset the oscillation frequency returns to the factory default Addres...

Page 147: ...s from 0 00h to 63 3Fh by binary numbers The greater the set value is the higher the frequency is The frequency is adjusted under certain conditions before shipment so the value after reset varies with the chip After a reset the oscillation frequency returns to the factory default Address es HOCOTRR0 0008 0068h b7 b6 b5 b4 b3 b2 b1 b0 HOCOTRD 5 0 Value after reset 0 0 1 1 1 1 1 1 Bit Symbol Bit Na...

Page 148: ... Rf is directed by the resonator manufacturer insert an Rf between EXTAL and XTAL by following the instruction When connecting a resonator to supply the clock the frequency of the resonator should be in the frequency range of the resonator for the main clock oscillator described in Table 9 1 Figure 9 2 Example of Crystal Connection Figure 9 3 shows an equivalent circuit of the crystal Use a crysta...

Page 149: ...illator by inputting an external clock signal Figure 9 4 Connection Example of External Clock 9 3 3 Notes on the External Clock Input The frequency of the external clock input can only be changed while the main clock oscillator is stopped Do not change the frequency of the external clock input while the setting of the main clock oscillator stop bit MOSCCR MOSTP is 0 main clock oscillator is operat...

Page 150: ...lock is controlled by the oscillation stop detection flag OSTDSR OSTDF The clock source is switched to the LOCO clock when the OSTDF flag is 1 and is switched to the main clock again when the OSTDF flag is set to 0 At this time if the main clock or PLL clock is selected with the CKSEL 2 0 bits the OSTDF flag cannot be set to 0 To switch the clock source to the main clock or PLL clock again after t...

Page 151: ... Wait for at least two cycles of PCLKB clock before again setting the OSTDCR OSTDIE bit to 1 According to the number of cycles for access to read a given I O register wait time longer than two cycles of PCLKB may have to be secured The oscillation stop detection interrupt is a non maskable interrupt Since non maskable interrupts are disabled in the initial state after a reset release enable the no...

Page 152: ... by the new value 9 6 1 System Clock The system clock ICLK is used as the operating clock of the CPU DTC ROM and RAM The ICLK frequency is set by using the SCKCR ICK 3 0 bits the SCKCR3 CKSEL 2 0 bits the STC 5 0 and PLIDIV 1 0 bits in the PLLCR register 9 6 2 Peripheral Module Clock The peripheral module clocks PCLKB and PCLKD are the operating clocks for use by peripheral modules The frequencies...

Page 153: ...R01UH0822EJ0100 Rev 1 00 Page 153 of 1041 Jul 31 2019 RX13T Group 9 Clock Generation Circuit IWDTCLK is internally generated by the IWDT dedicated on chip oscillator ...

Page 154: ...he processing after the clock frequency is changed modify the pertinent clock control register to change the frequency and then read the value from the register and then perform the subsequent processing 9 7 2 Notes on Resonator Since various resonator characteristics relate closely to the user s board design adequate evaluation is required on the user side before use referencing the resonator con...

Page 155: ... main clock is not used the EXTAL and XTAL pins can be used as general ports P36 and P37 When using these pins as general ports be sure to stop the main clock MOSCCR MOSTP 1 However do not use the EXTAL and XTAL pins as general ports P36 and P37 in a system that uses the main clock When the main clock is used do not set P36 and P37 to output ...

Page 156: ...nerated by the measurement reference clock is not within the allowable range an interrupt request is generated Table 10 1 lists the specifications of the CAC and Figure 10 1 shows a block diagram of the CAC Table 10 1 CAC Specifications Item Description Measurement target clocks The frequency of the following clocks can be measured Main clock HOCO clock LOCO clock IWDT dedicated clock IWDTCLK Peri...

Page 157: ...er Comparator CAULVR 1 128 1 1024 1 8192 Edge detection circuit CACREF CACREFE RSCS 2 0 RCDS 1 0 FMCS 2 0 TCSS 1 0 EDGES 1 0 CFME Count source clock Valid edge signal Frequency error interrupt request Internal peripheral bus RPS 1 32 CACNTBR CALLVR Measurement end interrupt request Overflow interrupt request CAICR CASTR Interrupt control circuit Digital filter DFS 1 0 Measurement target clock DFS ...

Page 158: ...bits for the new value to be reflected in the register Further write access to this bit are ignored until the current write access is reflected in the register Read the bit to confirm that the rewrite has been reflected in the register Address es 0008 B000h b7 b6 b5 b4 b3 b2 b1 b0 CFME Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 CFME Clock Frequency Measurement Enable ...

Page 159: ...alid Edge Select These bits select the valid edge for the reference signal Address es 0008 B001h b7 b6 b5 b4 b3 b2 b1 b0 EDGES 1 0 TCSS 1 0 FMCS 2 0 CACRE FE Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 CACREFE CACREF Pin Input Enable 0 CACREF pin input is disabled 1 CACREF pin input is enabled R W b3 to b1 FMCS 2 0 Measurement Target Clock Select b3 b1 0 0 0 Main clock...

Page 160: ...mpling clock Address es 0008 B002h b7 b6 b5 b4 b3 b2 b1 b0 DFS 1 0 RCDS 1 0 RSCS 2 0 RPS Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 RPS Reference Signal Select 0 CACREF pin input 1 Internal clock internally generated signal R W b3 to b1 RSCS 2 0 Measurement Reference Clock Select b3 b1 0 0 0 Main clock 0 1 0 HOCO clock 0 1 1 LOCO clock 1 0 0 IWDT dedicated clock IWDTC...

Page 161: ...5 b4 b3 b2 b1 b0 OVFFC L MENDF CL FERRF CL OVFIE MENDI E FERRI E Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 FERRIE Frequency Error Interrupt Request Enable 0 Frequency error interrupt request is disabled 1 Frequency error interrupt request is enabled R W b1 MENDIE Measurement End Interrupt Request Enable 0 Measurement end interrupt request is disabled 1 Measurement en...

Page 162: ...DFCL bit OVFF Flag Overflow Flag This flag indicates that the counter has overflowed Setting condition The counter has overflowed Clearing condition 1 is written to the CAICR OVFFCL bit Address es 0008 B004h b7 b6 b5 b4 b3 b2 b1 b0 OVFF MENDF FERRF Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 FERRF Frequency Error Flag 0 The clock frequency is within the range correspon...

Page 163: ...es the lower limit value of the counter used for measuring the frequency When the frequency falls below the value specified in this register a frequency error is detected Write to this register when the CACR0 CFME bit is 0 The counter value held in CACNTBR can vary with the difference between the phases of the digital filter and edge detection circuit on the one hand and the signal on the CACREF p...

Page 164: ...ts is input based on the clock source selected by the CACR2 RSCS 2 0 bits after 1 is written to the CFME bit The valid edge is a rising edge CACR1 EDGES 1 0 00b in Figure 10 2 3 When the next valid edge is input the counter value is transferred in CACNTBR and compared with the values of CAULVR and CALLVR If both CACNTBR CAULVR and CACNTBR CALLVR are satisfied only the MENDF flag in CASTR is set to...

Page 165: ...nternally until the level on the pin again matches three consecutive times Enabling and disabling of the digital filter and its sampling clock are selectable The counter value transferred in CACNTBR may be in error by up to one cycle of the sampling clock due to the difference between the phases of the digital filter and the signal input to the CACREF pin When a frequency dividing clock is selecte...

Page 166: ...cuit CAC 10 5 Usage Notes 10 5 1 Module Stop Function Setting CAC operation can be disabled or enabled using module stop control register C MSTPCRC The initial setting is for the CAC to be halted Register access is enabled by releasing the module stop state For details refer to section 11 Low Power Consumption ...

Page 167: ...Specifications of Low Power Consumption Functions Item Specification Clock divider functions The frequency division ratio can be set independently for the system clock ICLK peripheral module clock PCLKB S12AD clock PCLKD and FlashIF clock FCLK 1 Module stop function Each peripheral module can be stopped independently by the module stop control register Function for transition to low power consumpt...

Page 168: ...n for outputting the comparison result to the COMPn pin is possible Table 11 2 Operating Conditions of Each Power Consumption Mode Sleep Mode Deep Sleep Mode Software Standby Mode Entry trigger Control register instruction Control register instruction Control register instruction Exit trigger Interrupt Interrupt Interrupt 1 After exiting from each mode CPU begins from 2 Interrupt handling Interrup...

Page 169: ...ion mode the transition to the program stop state is exited and the interrupt exception handling is executed Note 2 Interrupts here indicates an external pin interrupt the NMI or IRQ0 to IRQ5 or any of peripheral interrupts the IWDT and voltage monitoring interrupts Note 3 The LOCO is the clock source following a transition from the reset state to normal mode Note 4 Makes a transition from sleep m...

Page 170: ...previous operating state used before entering sleep mode After exiting the reset state operation starts in middle speed operating mode Set the OPCCR register Deep sleep mode Sleep mode Deep sleep mode Sleep mode Software standby mode Software standby mode High speed operating mode Middle speed operating mode Reset state Exit the reset state WAIT instruction Interrupt ...

Page 171: ...mains 1 The SSBY bit can be cleared by writing 0 to the SSBY bit When the oscillation stop detection function enable bit OSTDCR OSTDE in the oscillation stop detection control register is 1 the set value of the SSBY bit is invalid Even if the SSBY bit is 1 the MCU will enter sleep mode or deep sleep mode after execution of the WAIT instruction Address es 0008 000Ch b15 b14 b13 b12 b11 b10 b9 b8 b7...

Page 172: ...d R W b14 to b10 Reserved These bits are read as 1 The write value should be 1 R W b15 MSTPA15 Compare Match Timer Unit 0 Module Stop Target module CMT unit 0 CMT0 CMT1 0 This module clock is enabled 1 This module clock is disabled R W b16 Reserved This bit is read as 1 The write value should be 1 R W b17 MSTPA17 12 Bit A D Converter Module Stop Target module S12AD 0 This module clock is enabled 1...

Page 173: ... clock is disabled R W b9 to b7 Reserved These bits are read as 1 The write value should be 1 R W b10 MSTPB10 Comparator C Module Stop Target module Comparator C 0 This module clock is enabled 1 This module clock is disabled R W b20 to b11 Reserved These bits are read as 1 The write value should be 1 R W b21 MSTPB21 I2C Bus Interface 0 Module Stop Target module RIIC0 0 This module clock is enabled...

Page 174: ...t to 1 and the SBYCR SSBY and MSTPCRA MSTPA28 bits meet specified conditions the MCU enters deep sleep mode For details refer to section 11 6 2 Deep Sleep Mode Address es 0008 0018h b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 DSLPE MSTPC 19 Value after reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MSTPC 0 Value after reset 0 0 0 0 0...

Page 175: ...icated by SYSTEM in the Module Symbol column in Table 5 1 List of I O Registers Address Order OPCM 2 0 Bits Operating Power Control Mode Select The OPCM 2 0 bits select operating power control mode in normal operating mode sleep mode and deep sleep mode Table 11 3 shows the relationship between operating power control modes the OPCM 2 0 bit settings and the operating frequency and voltage ranges O...

Page 176: ...um operating frequency during FLASH read is 12 MHz for ICLK FCLK PCLKB and PCLKD During FLASH programming erasure the operating frequency range is 1 to 12 MHz The power consumption of this mode is lower than that of high speed mode under the same conditions After a reset is canceled operation is started from this mode Note When using the FCLK at lower than 4 MHz during programming or erasing the f...

Page 177: ...Pmi bit m A to C i 0 to 31 in MSTPCRA to MSTPCRC is set to 1 the specified module stops operating and enters the module stop state but the CPU continues to operate independently When the corresponding MSTPmi bit is set to 0 the module exits the module state and restarts operating at the end of the bus cycle The internal states of modules are retained in the module stop state After a reset is cance...

Page 178: ...uency of each clock to lower than the maximum operating frequency for middle speed operating mode Confirm that the OPCCR OPCMTSF flag is 0 transition completed Set the OPCCR OPCM 2 0 bits to 010b middle speed operating mode Confirm that the OPCCR OPCMTSF flag is 0 transition completed Middle speed operation in middle speed operating mode 2 Switching from Low Power Consumption Mode to Normal Power ...

Page 179: ...S0 IWDTSLCSTP bit is 0 counting by the IWDT continues through transitions to low power consumption modes In the same way counting by the IWDT continues if a transition to sleep mode is made while the IWDT is being used in register start mode and the IWDTCSTPR SLCSTP bit is 0 To use sleep mode make the following settings and then execute a WAIT instruction 1 Set the PSW I bit 1 of the CPU to 0 2 Se...

Page 180: ...edetermined time period the CPU starts the reset exception handling Initiated by a power on reset A power on reset asserts a reset to the MCU When a power on reset is negated by a rise in the supply voltage the CPU starts the reset exception handling Initiated by a voltage monitoring reset A voltage monitoring reset asserts a reset to the MCU When a voltage monitoring reset is negated by a rise in...

Page 181: ...the same way counting by the IWDT continues if a transition to deep sleep mode is made while the IWDT is being used in register start mode and the IWDTCSTPR SLCSTP bit is 0 To use deep sleep mode make the following settings and then execute a WAIT instruction 1 Set the PSW I bit 2 of the CPU to 0 2 Set the interrupt request destination 3 to be used for exit from deep sleep mode 3 Set the priority ...

Page 182: ...r a predetermined time period the CPU starts the reset exception handling Initiated by a power on reset A power on reset asserts a reset to the MCU When a power on reset is negated by a rise in the supply voltage the CPU starts the reset exception handling Initiated by a voltage monitoring reset A voltage monitoring reset asserts a reset to the MCU When a voltage monitoring reset is negated by a r...

Page 183: ...ansition to software standby mode is made while the IWDT is being used in auto start mode and the OFS0 IWDTSLCSTP bit is 0 counting by the IWDT continues through transitions to low power consumption modes In the same way counting by the IWDT continues if a transition to software standby mode is made while the IWDT is being used in register start mode and the IWDTCSTPR SLCSTP bit is 0 To use softwa...

Page 184: ...U exits software standby mode and interrupt exception processing starts Initiated by a RES pin reset Clock oscillation starts when the low level is applied to the RES pin Clock supply for the MCU starts at the same time Keep the level on the RES pin low over the time required for oscillation of the clocks to become stable Reset exception processing starts when the high level is applied to the RES ...

Page 185: ...ts are set to 10b rising edge After that the SBYCR SSBY bit is set to 1 and the WAIT instruction is executed Thus entry to software standby mode is completed After that exit from software standby mode is initiated by the rising edge of the IRQn pin To exit software standby mode settings of the interrupt controller ICU are also necessary For details refer to section 14 Interrupt Controller ICUb Fig...

Page 186: ...U interrupt source or a DTC startup source cannot be cleared For this reason disable interrupts before entering the module stop state 11 7 4 Write Access to MSTPCRA MSTPCRB and MSTPCRC Write accesses to MSTPCRA MSTPCRB and MSTPCRC should be made only by the CPU 11 7 5 Timing of WAIT Instructions The WAIT instruction is executed before completion of the preceding register write The WAIT instruction...

Page 187: ...egisters to be protected Table 12 1 Association between PRCR Bits and Registers to be Protected PRCR Bit Register to be Protected PRC0 Registers related to the clock generation circuit SCKCR SCKCR3 PLLCR PLLCR2 MOSCCR LOCOCR ILOCOCR HOCOCR OSTDCR OSTDSR LOCOTRR ILOCOTRR HOCOTRR0 PRC1 Register related to the operating modes SYSCR1 Registers related to low power consumption functions SBYCR MSTPCRA M...

Page 188: ...C0 Protect Bit 0 Enables writing to the registers related to the clock generation circuit 0 Write disabled 1 Write enabled R W b1 PRC1 Protect Bit 1 Enables writing to the registers related to operating modes low power consumption functions the clock generation circuit and software reset 0 Write disabled 1 Write enabled R W b2 Reserved This bit is read as 0 The write value should be 0 R W b3 PRC3 ...

Page 189: ...n of another program to be started Such kinds of events are called exception events The RX CPU supports seven types of exceptions The types of exception events are shown in Figure 13 1 The occurrence of an exception causes the processor mode to switch to supervisor mode Figure 13 1 Types of Exception Events Exception events Undefined instruction exception Privileged instruction exception Floating ...

Page 190: ...bit in FPSW is 0 13 1 4 Reset A reset is generated by input of a reset signal to the CPU This has the highest priority of any exception and is always accepted 13 1 5 Non Maskable Interrupt A non maskable interrupt is generated by input of a non maskable interrupt signal to the CPU and is only used when a fatal fault is considered to have occurred in the system Never use the non maskable interrupt ...

Page 191: ... processing Exception request Instruction A Instruction B Instruction C Instruction D Instruction C Restarting of program execution User written processing program Branch to the vector read handling routine Generation of exception event General purpose registers saved on the stack Handling routine Restoration of general purpose registers For the fast interrupt RTFI instruction For exceptions other...

Page 192: ...General purpose registers and control registers other than the PC and PSW that are to be used within the exception handling routine must be saved on the stack by a user program at the start of the exception handling routine On completion of processing by an exception handling routine execution is restored from the exception handling routine to the original program by saving the registers saved on ...

Page 193: ...erated the exception Reset Instruction abandonment type Any machine cycle None Non maskable interrupt During execution of the RMPA SCMPU SMOVB SMOVF SMOVU SSTR SUNTIL and SWHILE instructions Instruction suspending type During instruction execution PC value of the instruction being executed Other than above Instruction completion type At the next break between instructions PC value of the next inst...

Page 194: ...exception handling routine the user must save these values on the stack within the exception handling routine b Updating PM U and I Bits in PSW I Set to 0 U Set to 0 PM Set to 0 c Saving PC For a fast interrupt PC BPC For exceptions other than a fast interrupt PC Stack d Setting Branch Destination Address of Exception Handling Routine in PC Processing is shifted to the exception handling routine b...

Page 195: ...exception handling routine 13 5 3 Floating Point Exception 1 The value in the processor status word PSW is saved on the stack ISP 2 The processor mode select bit PM the stack pointer select bit U and the interrupt enable bit I in PSW are cleared to 0 3 The value of the program counter PC is saved on the stack ISP 4 The vector is fetched from address FFFF FFE4h 5 The fetched vector is set to the PC...

Page 196: ...he interrupt 5 The vector for an interrupt source other than the fast interrupt is fetched from the relocatable vector table For the fast interrupt the address is fetched from the fast interrupt vector register FINTV 6 The fetched vector is set to the PC and processing branches to the exception handling routine 13 5 7 Unconditional Trap 1 The value in the processor status word PSW is saved on the ...

Page 197: ... is listed in Table 13 4 When multiple exceptions are generated at the same time the exception with the highest priority is accepted first Table 13 3 Return from Exception Handling Routine Exception Instruction for Return Undefined instruction exception RTE Privileged instruction exception RTE Floating point exception RTE Reset Return is impossible Non maskable interrupt Return is impossible Inter...

Page 198: ...s One of these detection methods can be set for each source Digital filter function Supported Software interrupt Interrupt generated by writing to a register One interrupt source Interrupt priority Specified by registers Fast interrupt function Faster interrupt processing of the CPU can be set only for a single interrupt source DTC control Interrupt sources can be used to start the DTC 1 Non maska...

Page 199: ...hover NM IFLTE IER DTCER Clear NMI ER NMI SR Detection Module data bus Non maskable interrupt request Clock restoration enable level Destination switchover to CPU IRQ5 IRQ0 Detection NMIER NMICR NMICLR NMISR IRQCR Non maskable interrupt enable register NMI pin interrupt control register Non maskable interrupt status clear register Non maskable interrupt status register IRQ control register IR IER ...

Page 200: ...to the generation of an interrupt request from the corresponding peripheral module or IRQi pin For interrupt generation by the various peripheral modules refer to the sections describing the modules Clearing conditions The flag is cleared to 0 when the interrupt request destination accepts the interrupt request The IR flag is cleared to 0 by writing 0 to it Note however that writing 0 to the IR fl...

Page 201: ...Request Register n IRn n interrupt vector number The IERm IENj bit is set for each request source vector number For the correspondence between interrupt sources and IERm IENj bits see Table 14 3 Interrupt Vector Table For the procedure for setting IERm IENj bits during the selection of destinations for interrupt requests refer to section 14 4 3 Selecting Interrupt Request Destinations Address es I...

Page 202: ...nd handles accepted interrupts If two or more interrupt requests are generated at the same time their priority levels are compared with the value of the IPR 3 0 bits If interrupt requests of the same priority level are generated at the same time an interrupt source with a smaller vector number takes precedence These bits should be written to while an interrupt request is disabled IERm IENj bit 0 m...

Page 203: ...tput to the CPU as a fast interrupt regardless of the setting of the IPRn register n interrupt vector number When using the fast interrupt for returning from the software standby mode see section 14 6 2 Return from Software Standby Mode If the setting of the IERm IENj bit has disabled interrupt requests from the interrupt source with the vector number in this register fast interrupt requests are n...

Page 204: ...nable register 027 DTCER027 is set to 0 an interrupt to the CPU is generated If 1 is written to the SWINT bit when the DTC transfer request enable register 027 DTCER027 is set to 1 a DTC transfer request is issued Address es ICU SWINTR 0008 72E0h b7 b6 b5 b4 b3 b2 b1 b0 SWINT Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 SWINT Software Interrupt Generation This bit is re...

Page 205: ...is written to the DTCE bit Clearing conditions When the specified number of transfers is completed for the chain transfer the number of transfers for the last chain transfer is completed When 0 is written to the DTCE bit Address es ICU DTCER027 0008 711Bh to ICU DTCER255 0008 71FFh b7 b6 b5 b4 b3 b2 b1 b0 DTCE Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 DTCE DTC Transf...

Page 206: ...does not require clearing IRQMD 1 0 Bits IRQ Detection Sense Select These bits select the interrupt detection sensing method of IRQi pin For the external pin interrupt detection setting see section 14 4 8 External Pin Interrupts Address es ICU IRQCR0 0008 7500h to ICU IRQCR5 0008 7505h b7 b6 b5 b4 b3 b2 b1 b0 IRQMD 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 Res...

Page 207: ...es three times the output level from the digital filter changes For details of the digital filter see section 14 4 7 Digital Filter Address es ICU IRQFLTE0 0008 7510h b7 b6 b5 b4 b3 b2 b1 b0 FLTEN 5 FLTEN 4 FLTEN 3 FLTEN 2 FLTEN 1 FLTEN 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 FLTEN0 IRQ0 Digital Filter Enable 0 Digital filter is disabled 1 Digital filter is enabl...

Page 208: ...lter Address es ICU IRQFLTC0 0008 7514h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FCLKSEL5 1 0 FCLKSEL4 1 0 FCLKSEL3 1 0 FCLKSEL2 1 0 FCLKSEL1 1 0 FCLKSEL0 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 FCLKSEL0 1 0 IRQ0 Digital Filter Sampling Clock 0 0 PCLK 0 1 PCLK 8 1 0 PCLK 32 1 1 PCLK 64 R W b3 b2 FCLKSEL1 1 0 IRQ1 Digital Filter S...

Page 209: ...p detection interrupt is generated Clearing condition When 1 is written to the NMICLR OSTCLR bit IWDTST Flag IWDT Underflow Refresh Error Status Flag This flag indicates the IWDT underflow refresh error interrupt request The IWDTST flag is read only and cleared by the NMICLR IWDTCLR bit Setting condition Address es ICU NMISR 0008 7580h b7 b6 b5 b4 b3 b2 b1 b0 LVD2S T LVD1S T IWDTS T OSTST NMIST Va...

Page 210: ...ag is read only and cleared by the NMICLR LVD1CLR bit Setting condition When the voltage monitoring 1 interrupt is generated while this interrupt is enabled at its source Clearing condition When 1 is written to the NMICLR LVD1CLR bit LVD2ST Flag Voltage Monitoring 2 Interrupt Status Flag This flag indicates the request for voltage monitoring 2 interrupt The LVD2ST flag is read only and cleared by ...

Page 211: ...es are no longer enabled Writing 0 to this bit is disabled LVD2EN Bit Voltage Monitoring 2 Interrupt Enable This bit enables the voltage monitoring 2 interrupt A 1 can be written to this bit only once and subsequent write accesses are no longer enabled Writing 0 to this bit is disabled Address es ICU NMIER 0008 7581h b7 b6 b5 b4 b3 b2 b1 b0 LVD2E N LVD1E N IWDTE N OSTEN NMIEN Value after reset 0 0...

Page 212: ... b4 b3 b2 b1 b0 LVD2C LR LVD1C LR IWDTC LR OSTCL R NMICL R Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 NMICLR NMI Clear This bit is read as 0 Writing 1 to this bit clears the NMISR NMIST flag Writing 0 to this bit has no effect R W 1 b1 OSTCLR OST Clear This bit is read as 0 Writing 1 to this bit clears the NMISR OSTST flag Writing 0 to this bit has no effect R W 1 b2 ...

Page 213: ...cycle specified with the NMIFLTC NFCLKSEL 1 0 bits When the sampled level matches three times the output level from the digital filter changes For details of the digital filter see section 14 4 7 Digital Filter Address es ICU NMICR 0008 7583h b7 b6 b5 b4 b3 b2 b1 b0 NMIMD Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b2 to b0 Reserved These bits are read as 0 The write valu...

Page 214: ...e selected from among the PCLK every cycle PCLK 8 once every eight cycles PCLK 32 once every 32 cycles and PCLK 64 once every 64 cycles For details of the digital filter see section 14 4 7 Digital Filter Address es ICU NMIFLTC 0008 7594h b7 b6 b5 b4 b3 b2 b1 b0 NFCLKSEL 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 NFCLKSEL 1 0 NMI Digital Filter Sampling Clock b1...

Page 215: ...onditional traps The vector for BRK instructions is vector 0 while the vector numbers for INT instructions are specifiable as numbers in the range from 0 to 255 Table 14 3 lists details of the interrupt vectors Details of the headings in Table 14 3 are listed below Item Description Source of interrupt request generation Name of the source for generation of the interrupt request Name Name of the in...

Page 216: ... N A N A N A BSC BUSERR 16 0040h Level N A N A IER02 IEN0 IPR000 Reserved 17 0044h N A N A N A Reserved 18 0048h N A N A N A Reserved 19 004Ch N A N A N A Reserved 20 0050h N A N A N A Reserved 21 0054h N A N A N A Reserved 22 0058h N A N A N A FCU FRDYI 23 005Ch Edge N A N A IER02 IEN7 IPR002 Reserved 24 0060h N A N A N A Reserved 25 0064h N A N A N A Reserved 26 0068h N A N A N A ICU SWINT 27 00...

Page 217: ...1 011Ch N A N A N A Reserved 72 0120h N A N A N A Reserved 73 0124h N A N A N A Reserved 74 0128h N A N A N A Reserved 75 012Ch N A N A N A Reserved 76 0130h N A N A N A Reserved 77 0134h N A N A N A Reserved 78 0138h N A N A N A Reserved 79 013Ch N A N A N A Reserved 80 0140h N A N A N A Reserved 81 0144h N A N A N A Reserved 82 0148h N A N A N A Reserved 83 014Ch N A N A N A Reserved 84 0150h N ...

Page 218: ...h Edge N A N A IER0F IEN4 MTU2 TGIA2 125 01F4h Edge N A IER0F IEN5 IPR125 DTCER125 TGIB2 126 01F8h Edge N A IER0F IEN6 DTCER126 TCIV2 127 01FCh Edge N A N A IER0F IEN7 IPR127 TCIU2 128 0200h Edge N A N A IER10 IEN0 MTU3 TGIA3 129 0204h Edge N A IER10 IEN1 IPR129 DTCER129 TGIB3 130 0208h Edge N A IER10 IEN2 DTCER130 TGIC3 131 020Ch Edge N A IER10 IEN3 DTCER131 TGID3 132 0210h Edge N A IER10 IEN4 DT...

Page 219: ... A N A Reserved 175 02BCh N A N A N A Reserved 176 02C0h N A N A N A Reserved 177 02C4h N A N A N A Reserved 178 02C8h N A N A N A Reserved 179 02CCh N A N A N A Reserved 180 02D0h N A N A N A Reserved 181 02D4h N A N A N A Reserved 182 02D8h N A N A N A Reserved 183 02DCh N A N A N A Reserved 184 02E0h N A N A N A Reserved 185 02E4h N A N A N A Reserved 186 02E8h N A N A N A Reserved 187 02ECh N ...

Page 220: ...erved 228 0390h N A N A N A Reserved 229 0394h N A N A N A Reserved 230 0398h N A N A N A Reserved 231 039Ch N A N A N A Reserved 232 03A0h N A N A N A Reserved 233 03A4h N A N A N A Reserved 234 03A8h N A N A N A Reserved 235 03ACh N A N A N A Reserved 236 03B0h N A N A N A Reserved 237 03B4h N A N A N A SCI12 ERI12 238 03B8h Level N A N A IER1D IEN6 IPR238 RXI12 239 03BCh Edge N A IER1D IEN7 DTC...

Page 221: ...at corresponds to the vector number of the fast interrupt is placed in the fast interrupt vector register FINTV of the CPU 14 3 3 Non maskable Interrupt Vector Table The non maskable interrupt vector table is at FFFF FFF8h Reserved 254 03F8h N A N A N A Reserved 255 03FCh N A N A N A Table 14 3 Interrupt Vector Table 6 6 Source of Interrupt Request Generation Name Vector No 1 Vector Address Offset...

Page 222: ...operation of the IR flag in IRn n interrupt vector number in the case of edge detection of an interrupt from a peripheral module or on an external pin The IR flag in IRn is set to 1 immediately after the transition of the interrupt signal due to generation of the interrupt If the CPU is the request destination for the interrupt the IR flag is automatically cleared to 0 on acceptance of the interru...

Page 223: ...ag re setting Note 1 When the transmission or reception interrupt of the SCI or RIIC is generated with the IRn IR flag being 1 the interrupt request is retained After the IRn IR flag is cleared to 0 the IRn IR flag is set to 1 again by the retained request For details see descriptions of the interrupts in section 23 Serial Communications Interface SCIg SCIh and section 24 I2C bus Interface RIICa F...

Page 224: ...erating the interrupt Confirm that the interrupt request flag in the source generating the interrupt has been cleared to 0 and that the IRn IR flag has been cleared to 0 and then complete the interrupt handling Figure 14 5 IRn IR Flag Operation for Level Detection Interrupts Figure 14 6 shows the procedure for handling level detection interrupts Figure 14 6 Procedure for Handling Level Detection I...

Page 225: ...st for which the corresponding IRn IR is 1 to be output to the interrupt request destination Setting the IERm IENj bit to disable an interrupt request suspends the output of the interrupt request for which the corresponding IRn IR is 1 The IRn IR flag is not affected by the IERm IENj bit Use the following procedure to disable interrupt requests 1 Set the IERm IENj bit to disable interrupt requests...

Page 226: ...IRn IR flag is 1 an interrupt request DTC transfer request that is generated again will be ignored Note 3 For chain transfer DTC transfer continues until the last chain transfer ends Whether a CPU interrupt is generated at the end of chain transfer the IRn IR flag clear timing and the interrupt request destination after transfer are determined by the state of DISEL and the remaining transfer count...

Page 227: ...fter processing branches to the interrupt handling routine are set to the same value as the interrupt priority level of the accepted interrupt request If an interrupt request which has an interrupt level higher than that of the PSW IPL 3 0 bits is generated at this time this interrupt request for multiple interrupts is accepted If the interrupt priority level of the accepted interrupt request is 1...

Page 228: ...eturn from software standby mode set the IRQFLTE0 FLTENi or NMIFLTE NFLTEN bit to 1 digital filter enabled 14 4 8 External Pin Interrupts The procedure for using the signal on an external pin as an interrupt is as follows 1 Clear the IERm IENj bit m 02h to 1Fh j 0 to 7 to 0 interrupt request disabled 2 Clear the IRQFLTE0 FLTENi bit i 0 to 5 to 0 digital filter disabled 1 3 Set the digital filter s...

Page 229: ...SP 2 To use the NMI pin clear the NMIFLTE NFLTEN bit to 0 digital filter disabled 1 3 To use the NMI pin set the digital filter sampling clock with the NMIFLTC NFCLKSEL 1 0 bits 1 4 To use the NMI pin set the NMI pin detection sense with the NMICR NMIMD bit 5 To use the NMI pin write 1 to the NMICLR NMICLR bit to clear the NMISR NMIST flag to 0 6 To use the NMI pin set the NMIFLTE NFLTEN bit to 1 ...

Page 230: ...rom a non maskable interrupt or an interrupt that enables the return from the software standby mode The conditions for the return are listed below Interrupts 1 Select the interrupt source that enables the return from the software standby mode 2 Select the CPU as the interrupt request destination 3 Use the IENj bit in IERm m 02h to 1Fh j 0 to 7 to enable the given interrupt request 4 Set a priority...

Page 231: ... of 1041 Jul 31 2019 RX13T Group 14 Interrupt Controller ICUb 14 7 Usage Note 14 7 1 Note on WAIT Instruction Used with Non Maskable Interrupt Before executing the WAIT instruction check to see that all the status flags in NMISR are 0 ...

Page 232: ...bus 2 Connected to ROM Internal main buses Internal main bus 1 Connected to the CPU Operates in synchronization with the system clock ICLK Internal main bus 2 Connected to the DTC Connected to on chip memory RAM ROM Operates in synchronization with the system clock ICLK Internal peripheral buses Internal peripheral bus 1 Connected to peripheral modules DTC interrupt controller and bus error monito...

Page 233: ...gramming erasure 8000 0000h to FEFF FFFFh Memory bus 2 ROM for reading only FF00 0000h to FFFF FFFFh Bus error monitoring section Internal main bus 1 Internal main bus 2 Instruction bus Operand bus ROM RAM Internal peripheral bus 1 Internal peripheral buses 2 and 3 DTC s ICLK synchronization CPU Peripheral module Peripheral module Peripheral module DTC m Memory bus 1 Memory bus 2 Internal peripher...

Page 234: ...in bus 2 can be set using the memory bus 1 RAM priority control bits BPRA 1 0 and memory bus 2 ROM priority control bits BPRO 1 0 in the bus priority control register BUSPRI for the corresponding memory buses When the priority order is fixed internal main bus 2 has priority over the CPU bus operand over instruction fetching When the priority order is toggled the bus for which a request has been ac...

Page 235: ...ternal main bus 1 When the priority order is toggled a bus has a lower priority when the request of that bus is accepted The order of accepting requests may change depending on the BUSPRI setting see Figure 15 2 Figure 15 2 Priority Order Between Internal Peripheral Bus Accesses Table 15 4 Connection of Peripheral Modules to the Internal Peripheral Buses Type of Bus Peripheral Modules Internal per...

Page 236: ...internal memory is scheduled after the write access to the internal peripheral bus from the CPU the following round of bus access can be started before the current bus operation is completed and thus the order of accesses may be changed see Figure 15 3 Figure 15 3 Write Buffer Function Internal peripheral bus 2 Internal peripheral bus 1 Memory bus 1 RAM RAM Write access to peripheral bus 1 Access ...

Page 237: ...a peripheral bus during access to RAM and ROM by the CPU Figure 15 4 Example of Parallel Operations 15 2 7 Restrictions 1 Prohibition of Access that Spans Multiple Areas of Address Space Single access that spans two areas of the address space is prohibited and operation of such an access is not guaranteed Ensure that a single word or longword access does not span across two areas by crossing addre...

Page 238: ...bled while timeout errors are being detected Address es 0008 1300h b7 b6 b5 b4 b3 b2 b1 b0 STSCL R Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 STSCLR Status Clear 0 Invalid 1 Bus error status register cleared W 1 b7 to b1 Reserved These bits are read as 0 The write value should be 0 R W Address es 0008 1304h b7 b6 b5 b4 b3 b2 b1 b0 TOEN IGAEN Value after reset 0 0 0 0 ...

Page 239: ...ated 1 Timeout generated R b3 b2 Reserved These bits are read as 0 Writing to these bits has no effect R b6 to b4 MST 2 0 Bus Master Code b6 b4 0 0 0 CPU 0 0 1 Reserved 0 1 0 Reserved 0 1 1 DTC 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved R b7 Reserved This bit is read as 0 Writing to this bit has no effect R Address es 0008 130Ah b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b...

Page 240: ... when the request of that bus is accepted Address es 0008 1310h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 BPFB 1 0 BPGB 1 0 BPIB 1 0 BPRO 1 0 BPRA 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 BPRA 1 0 Memory Bus 1 RAM Priority Control b1 b0 0 0 The order of priority is fixed 0 1 The order of priority is toggled 1 0 Setting prohibited 1...

Page 241: ...bus 2 has priority over internal main bus 1 When the priority order is toggled a bus has a lower priority when the request of that bus is accepted BPFB 1 0 Bits Internal Peripheral Bus 6 Priority Control These bits specify the priority order for internal peripheral bus 6 When the priority order is fixed internal main bus 2 has priority over internal main bus 1 When the priority order is toggled a ...

Page 242: ...address access errors are listed in Table 15 5 15 4 1 2 Timeout When the timeout detection enable bit in the bus error monitoring enable register is enabled BEREN TOEN 1 bus access that is not completed within 768 cycles leads to a timeout error Internal peripheral buses 2 and 3 Bus access is not completed within 768 peripheral module clock PCLKB cycles from the start of the access If a timeout er...

Page 243: ...occurs the status is retained until the BERSRn register is cleared A bus error does not result Δ A bus error may or may not result A bus error results Note The capacity of the RAM data flash and ROM differs depending on the product For details refer to section 30 RAM and section 31 Flash Memory FLASH Table 15 5 Type of Bus Errors Address Type of Area Type of Error Illegal Address Access Timeout 00...

Page 244: ...5 5 Interrupt 15 5 1 Interrupt Source An illegal address access error or detection of a timeout leads to a bus error signal for the interrupt controller Table 15 6 Interrupt Source Name Interrupt Source DTC Activation BUSERR Illegal address access error or timeout Not possible ...

Page 245: ...uentially be executed in response to a single request Either performed only when the transfer counter becomes 0 or every time can be selected Sequence transfer A series of complicated transfers can be registered as a sequence Any sequence can be selected by the transfer data and executed Only one trigger source can be set at a time Up to 256 sequences for a single trigger source The data that is i...

Page 246: ...ripheral bus 1 Internal main bus 2 ROM Internal peripheral bus Memory bus 2 RAM Transfer information Memory bus 1 MRA DTC mode register A MRB DTC mode register B MRC DTC mode register C CRA DTC transfer count register A CRB DTC transfer count register B SAR DTC transfer source register DAR DTC transfer destination register DTCCR DTC control register DTCVBR DTC vector base register DTCADMOD DTC add...

Page 247: ... transfer request The transfer information can be stored in ROM because the transfer information is not written back While the WBDIS bit is 1 operation for each transfer mode is as follows Address es inaccessible directly from the CPU b7 b6 b5 b4 b3 b2 b1 b0 MD 1 0 SZ 1 0 SM 1 0 WBDIS Value after reset x x x x x x x x x Undefined Bit Symbol Bit Name Description R W b0 WBDIS Write back Disable 0 Wr...

Page 248: ... response to the next transfer request 2 Block transfer mode 1 block of data is transferred on a single transfer request The transfer address and transfer count are not updated so that the same block transfer is repeated on each transfer request When the block transfer count is 1 the ICU DTCERn DTCE bit is not set to 0 and data transfer continues in response to the next transfer request When setti...

Page 249: ...INDX SQEND Value after reset x x x x x x x x x Undefined Bit Symbol Bit Name Description R W b0 SQEND Sequence Transfer End 0 Continue the sequence transfer 1 End the sequence transfer b1 INDX Index Table Reference 0 Does not refer to the index table 1 Refers the index table based on the transferred data 1 b3 b2 DM 1 0 Transfer Destination Address Addressing Mode b3 b2 0 0 The address in the DAR r...

Page 250: ... Enable The CHNE bit enables or disables chain transfer The chain transfer condition is selected by the CHNS bit For details of chain transfer refer to section 16 4 6 Chain Transfer Refer to Table 16 2 for the setting value to be used in the sequence transfer Table 16 2 Values of Bits CHNE SQEND and INDX in the Sequence Transfer and DTC Operation CHNE Bit SQEND Bit INDX Bit Operation Usage 0 0 1 S...

Page 251: ...ment Addition This bit specifies whether to use the SAR DTCDISP value as the transfer source address When setting the DISPE bit to 1 set the MRA WBDIS bit to 1 does not write back the transfer information and set the DTCCR RRS bit to 0 transfer information read is not skipped Address es inaccessible directly from the CPU b7 b6 b5 b4 b3 b2 b1 b0 DISPE Value after reset x x x x x x x x x Undefined B...

Page 252: ...de 32 bits are valid In short address mode lower 24 bits are valid and upper 8 bits b31 to b24 are ignored The address of this register is extended by the value specified by b23 DAR register cannot be accessed directly from the CPU Address es inaccessible directly from the CPU b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Value after reset x x x x x x x x x x x x x x x x b15 b14 ...

Page 253: ...nd 00h respectively The CRAL value is decremented 1 at each data transfer When it reaches 00h the CRAH value is reloaded to the CRAL register 3 Block transfer mode MRA MD 1 0 bits 10b The CRAH register retains the block size and the CRAL register functions as an 8 bit block size counter The transfer count is 1 255 and 256 when the set value is 01h FFh and 00h respectively The CRAL value is decreme...

Page 254: ...RRS bit Furthermore when the transfer counter CRA register became 0 during the previous normal transfer and when the transfer counter CRB register became 0 during the previous block transfer the transferred information is read regardless of the RRS bit value If the value of the MRA WBDIS bit in any transfer information is 1 set the RRS bit to 0 Note that the MRA WBDIS bit should be set to 1 when t...

Page 255: ...ADMOD register is used to specify the area accessible by the DTC SHORT Bit Short Address Mode Set This bit is used to select address mode of registers SAR and DAR Full address mode allows the DTC to access to a 4 Gbyte space 0000 0000h to FFFF FFFFh Short address mode allows the DTC to access to a 16 Mbyte space 0000 0000h to 007F FFFFh and FF80 0000h to FFFF FFFFh Address es DTC DTCVBR 0008 2404h...

Page 256: ...sition to the module stop state deep sleep mode or software standby mode Set the DTCST bit to 1 to resume the data transfer after returning from the module stop state deep sleep mode or software standby mode For details on transitions to the module stop state deep sleep mode and software standby mode refer to section 16 8 Low Power Consumption Function and section 11 Low Power Consumption Address ...

Page 257: ...C Active Flag This flag indicates the state of data transfer operation Setting condition When the data transfer is started by a transfer request When the sequence transfer is resumed Clearing condition When the data transfer is completed in response to a transfer request When the sequence transfer is suspended Address es DTC DTCSTS 0008 240Eh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 A...

Page 258: ...ress of this register is extended by the value specified by b27 The lower 10 bits b9 to b0 are reserved bits and fixed to 0 When writing this register set these bits to 0 It can be set in the range of 0000_0000h to 07FF_FC00h and F800_0000h to FFFF_FC00h in 1 Kbyte units Address es DTC DTCIBR 0008 2410h b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Value after reset 0 0 0 0 0 0 0...

Page 259: ...ave no effect Figure 16 2 Procedure to Terminate Sequence Transfer Address es DTC DTCOR 0008 2414h b7 b6 b5 b4 b3 b2 b1 b0 SQTFR L Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 SQTFRL Sequence Transfer Terminate Writing 1 to this bit terminates the sequence transfer in progress This bit is read as 0 R W b7 to b1 Reserved These bits are read as 0 The write value should be...

Page 260: ...placement Register DTCDISP The DTCDISP register is used to specify the displacement value to add to the DTC transfer source address If MRC DISPE bit is 1 the value SAR DTCDISP is used as the transfer source address Address es DTC DTCSQE 0008 2416h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ESPSE L VECN 7 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description...

Page 261: ...fied number of data transfer the ICU DTCERn DTCE bit is set to 0 and an interrupt is requested to the CPU If the MRB DISEL bit is 1 an interrupt is requested to the CPU on completion of data transfer For the other transfers the interrupt status flag of the request source is set to 0 at the start of data transfer 16 3 1 Allocating Transfer Information and DTC Vector Table The DTC reads the start ad...

Page 262: ...on n 4 bytes Transfer information per transfer 16 bytes Transfer information for the second transfer in chain transfer mode 16 bytes Transfer information for the second transfer in chain transfer mode 12 bytes Start address 1 2 0 3 MRA SAR MRB DAR CRA CRB MRA SAR MRB DAR CRA CRB MRA MRB Reserved 00h MRA MRB SAR DAR CRA CRB CRA CRB SAR DAR 3 0 2 1 Allocation of transfer information in short address...

Page 263: ... 3 lists transfer modes of the DTC Note 1 Set transfer source or transfer destination in the repeat area Note 2 Set transfer source or transfer destination in the block area Note 3 After data transfer of the specified count the initial state is restored and the operation is continued repeated Setting the MRB CHNE bit to 1 allows multiple transfers chain transfer on a single transfer request The se...

Page 264: ...PU is generated No Yes DISEL bit 1 No Yes Clear interrupt status flag Update start address of transfer information CHNE bit 1 No Yes CHNS bit 0 No Yes No Yes An interrupt to the CPU is generated Transfer data Write back transfer information 2 Transfer data Write back transfer information 2 Next transfer MD 1 0 bits 01b Repeat transfer mode No Yes Note 1 Counter value before starting data transfer ...

Page 265: ...ransfer information are read Furthermore when the transfer counter CRA register became 0 during the previous normal transfer and when the transfer counter CRB register became 0 during the previous block transfer transfer information is read regardless of the value of the RRS bit Figure 16 14 shows an example of transfer information read skip When updating the vector table and transfer information ...

Page 266: ...rthermore in full address mode write back of registers MRA MRB and MRC is skipped 16 4 2 2 Write Back Skip by the MRA WBDIS Bit When the MRA WBDIS bit is 1 the transfer information SAR DAR CRA and CRB is not written back regardless of the settings of the transfer information The transfer information on the memory is not updated data can be transferred by the DTC without copying the transfer inform...

Page 267: ...normal transfer mode and Figure 16 6 shows the memory map of normal transfer mode Note 1 Write back operation is skipped when the MRA WBDIS bit is 1 Note 2 Write back operation is skipped when address is fixed Figure 16 6 Memory Map of Normal Transfer Mode Table 16 6 Register Functions in Normal Transfer Mode Register Description Value Written Back by Writing Transfer Information 1 SAR Transfer so...

Page 268: ...generated on completion of the specified number of data transfers Table 16 7 lists the register functions in repeat transfer mode and Figure 16 7 shows the memory map of repeat transfer mode Note 1 Write back operation is skipped when the MRA WBDIS bit is 1 Note 2 Write back operation is skipped when address is fixed Figure 16 7 Memory Map of Repeat Transfer Mode Transfer Source Repeat Area Table ...

Page 269: ... an interrupt request to the CPU to be generated at the end of specified count block transfer Table 16 8 lists register functions in block transfer mode and Figure 16 8 shows the memory map of block transfer mode Note 1 Write back operation is skipped when the MRA WBDIS bit is 1 Note 2 Write back operation is skipped when address is fixed Figure 16 8 Memory Map of Block Transfer Mode Transfer Dest...

Page 270: ...R DAR CRA CRB MRA MRB and MRC that define a data transfer can be specified independently of each other Figure 16 9 shows chain transfer operation Figure 16 9 Chain Transfer Operation If the MRB CHNE bit is 1 and the CHNS bit is 1 chain transfer is performed only after completion of specified number of data transfers In repeat transfer mode chain transfer is performed after completion of specified ...

Page 271: ...ess Mode Normal Transfer Mode Repeat Transfer Mode Figure 16 11 Example 2 of DTC Operation Timing Short Address Mode Block Transfer Mode Block Size 4 System clock DTC access Vector read Transfer information read Data transfer Transfer information write R W ICU IRn DTC transfer request n Vector number System clock DTC access Vector read Transfer information read Data transfer Transfer information w...

Page 272: ...l Address Mode Normal Transfer Mode Repeat Transfer Mode System clock DTC access Vector read Transfer information read Data transfer Transfer information write Transfer information read Data transfer Transfer information write R W R W ICU IRn DTC transfer request n Vector number System clock DTC access Vector read Transfer information read Data transfer Transfer information write R W ICU IRn DTC t...

Page 273: ...n Data on the RAM and Transfer Source Data on the Peripheral Module System clock ICU IRn DTC transfer request DTC access Vector read Transfer information read Data transfer Transfer information write Read skip enable Data transfer Transfer information write 2 R 1 n Vector number Note When request sources vector numbers of 1 and 2 are the same and the DTCCR RRS bit is 1 the transfer information rea...

Page 274: ...cles for access to data read destination Cw Cycles for access to data write destination The unit is system clocks ICLK for 1 in the Vector Read Transfer Information Read and Data Transfer Read columns and 2 in the Internal Operation column Cv Ci Cr and Cw vary depending on the corresponding access destination For the number of cycles for respective access destinations refer to section 30 RAM secti...

Page 275: ...tions is performed by using the values of bits MRB CHNE and MRB SQEND A chain transfer is executed when the CHNE bit is 1 The next transfer information is read Go to 4 The sequence transfer is suspended when the CHNE bit is 0 and the SQEND bit is 0 Go to 5 The sequence transfer ends when the CHNE bit is 0 and the SQEND bit is 1 5 When a DTC transfer request from the source specified in the DTCSQE ...

Page 276: ... transfer the suspended sequence transfer is resumed Table 16 10 Sequence Transfer Process and Values of Bits CHNE SQEND and INDX DTC Operations CHNE Bit SQEND Bit INDX Bit Start sequence transfer 0 0 1 1 Continue sequence transfer 1 0 0 Suspend sequence transfer 2 0 0 0 End sequence transfer 0 1 0 End current sequence transfer and Obtain new sequence number 0 1 1 1 Some other transfer not sequenc...

Page 277: ...rting the sequence or output an interrupt request to the CPU without starting the sequence For a complicated sequence that the DTC cannot handle set the CPUSEL bit to 1 to allow the CPU to handle such a sequence Figure 16 17 DTC Index Table Start address of transfer information table 0 upper 30 bits Start address of transfer information table p upper 30 bits 4 bytes p 4 4 DTC index table base addr...

Page 278: ... Address es DTCIBR p 4 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 DTCIADDR 31 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DTCIADDR 15 2 CPUSE L Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 CPUSEL Sequence Transfer CPU Interrupt Select 0 Continues the sequence transfer sta...

Page 279: ...tion The lower 8 bits that have been transferred based on the transfer information become a sequence number selecting one sequence among possible 256 sequences Figure 16 18 Examples of Sequence Transfers 1 Execution of a Single Transfer INDX 1 SQEND 1 INDX 1 SQEND 1 CHNE 1 INDX 1 SQEND 1 CHNE 0 CHNE 1 CHNE 0 CHNE 1 INDX 1 SQEND 1 INDX 1 CHNE 1 CHNE 1 CHNE 1 INDX 1 2 Execution of a Single Transfer ...

Page 280: ...ce number p Since the values of the CHNE INDX and SQEND bits are 0 0 and 1 respectively the sequence ends after the specified transfer is executed Figure 16 19 Example of a Sequence of Single Transfer INDX 1 SQEND 1 Transfer request n Select sequence DTCVBR 0 4 DTCVBR 1 4 DTCVBR 2 4 DTCVBR n 4 DTCVBR 255 4 INDX 1 DTC vector table Transfer information Data Sequence number p DTCIBR 0 4 DTCIBR 1 4 DT...

Page 281: ...s executed When the transfer information in which the CHNE INDX and SQEND bits are 0 0 and 1 respectively is read the sequence ends after the specified transfer is executed Figure 16 20 Example of Sequence of a Single Chain Transfer INDX 1 Transfer request n Select sequence DTCVBR 0 4 DTCVBR 1 4 DTCVBR 2 4 DTCVBR n 4 DTCVBR 255 4 INDX 1 DTC vector table Transfer information Data Sequence number q ...

Page 282: ... the DTC vector table is not referred and the suspended sequence is resumed When the transfer information in which the CHNE INDX and SQEND bits are 0 0 and 1 respectively is read the sequence ends after the specified transfer is executed Figure 16 21 Example of Divided Sequence INDX 1 Transfer request n Select sequence DTCVBR 0 4 DTCVBR 1 4 DTCVBR 2 4 DTCVBR n 4 DTCVBR 255 4 INDX 1 DTC vector tabl...

Page 283: ... transfer information corresponding to the obtained sequence number k and then starts a new sequence When the transfer information in which the CHNE INDX and SQEND bits are 0 0 and 1 respectively is read the sequence ends after the specified transfer is executed Figure 16 22 Example When Starting a New Sequence on Completion of a Sequence INDX 1 Transfer request n Select sequence DTCVBR 0 4 DTCVBR...

Page 284: ... t When the CPUSEL bit of the obtained DTC index is 1 the DTC ends the sequence transfer without starting the sequence and then outputs an interrupt request to the CPU Figure 16 23 Example of Output of an Interrupt Request to the CPU INDX 1 Transfer request n Select sequence DTCVBR 0 4 DTCVBR 1 4 DTCVBR 2 4 DTCVBR n 4 DTCVBR 255 4 INDX 1 DTC vector table Transfer information Data Sequence number t...

Page 285: ...r information refer to section 16 3 1 Allocating Transfer Information and DTC Vector Table 3 Set the start address of the transfer information in the DTC vector table For how to set the DTC vector table refer to section 16 3 1 Allocating Transfer Information and DTC Vector Table When using sequence transfer set the DTCADMOD SHORT bit to 0 set registers DTCIBR DTCSQE and DTCDISP and allocate the DT...

Page 286: ...er The CRB register can be set to any value 2 DTC Vector Table Setting The start address of the transfer information for the RXI interrupt is set in the vector table for the DTC 3 ICU Setting and DTC Module Activation Set the corresponding ICU DTCERn DTCE bit to 1 and the ICU IERm IENj bit to 1 Set the DTCST DTCST bit to 1 4 SCI Setting Enable the RXI interrupt by setting the SCR RIE bit in the SC...

Page 287: ...e source is repeat area for rewriting the transfer destination address of the first data transfer The transfer destination is the address where the upper 8 bits of the DAR register in the first transfer information is allocated In this case set the MRB CHNE bit to 0 chain transfer is disabled and the MRB DISEL bit to 0 an interrupt request to the CPU is generated on completion of the specified num...

Page 288: ...continue the sequence transfer The MRB DTS bit can be set to any value Set the address of the SCIk RDR register in the SAR register and set the start address of the RAM area which stores the data in the DAR register When the MRA WBDIS bit is set to 1 Does not write back the transfer information the values of registers CRA and CRB are ignored 2 DTC Vector Table Setting Set the start address of the ...

Page 289: ... CPU and ends the sequence transfer 7 During Suspension of the Sequence Transfer Set the ICU DTCERn DTCE bit to 1 if the bit is 0 The DTC continues to transfer the data for every generation of the DTC transfer request in response to the corresponding RXI interrupt 8 End of the Sequence Transfer Set the MRB SQEND bit in the last transfer information of the sequence transfer to 1 After execution of ...

Page 290: ...truction is executed the transition to deep sleep mode follows the completion of the data transfer The DTC is released from the module stop state by writing 0 to the MSTPCRA MSTPA28 bit following recovery from deep sleep mode 3 Software Standby Mode Make settings according to the procedure under section 11 6 3 1 Entry to Software Standby Mode in section 11 Low Power Consumption If any data transfe...

Page 291: ...address plus 8h Ch and the CRA setting to the address plus Ah Eh When writing CRA and CRB settings in 32 bit units allocate the CRA setting at the MSB side of the 32 bits and the CRB setting at the LSB side and write the settings to the address plus 8h Ch regardless of endian Figure 16 26 Allocation of Transfer Information 1 0 MRA SAR MRB DAR CRA CRB 3 2 Allocation of transfer information to littl...

Page 292: ...transfer is to be used make sure that the DTCADMOD SHORT bit is 0 full address mode and the DTCCR RRS bit is also 0 transfer information read is not skipped In addition set the MRB CHNE bit to 0 chain transfer is disabled when setting the MRB INDX bit to 1 start sequence transfer and refer the index table or the MRB SQEND bit to 1 end the sequence transfer ...

Page 293: ...he pin states the open drain control register y ODRy y 0 1 that selects the output type of each pin the pull up control register PCR that controls on off of the input pull up MOS the drive capacity control register DSCR that selects the drive capacity and the port mode register PMR that specifies the pin function of each port For details on the PMR register see section 18 Multi Function Pin Contro...

Page 294: ...n as general I O pins Table 17 2 Port Functions Port Pin Input Pull up Open Drain Output Drive Capacity Switching High Current Pin 5 V Tolerant PORT1 P10 P11 PORT2 P22 P23 P24 PORT3 P36 P37 PORT4 P40 to P47 Fixed to normal output PORT7 P70 P71 to P76 Fixed to high drive output PORT9 P93 P94 PORTA PA2 PA3 PORTB PB0 PB3 PB1 PB2 Fixed to high drive output PB6 Fixed to high drive output PB4 PB5 PB7 PO...

Page 295: ...rt 2 P22 1 to P24 1 Port 4 P40 to P44 P45 1 to P47 1 Port 7 P70 1 P71 to P76 Port 9 P93 P94 Port A PA2 1 PA3 1 Port B PB0 to PB3 PB4 1 PB5 1 PB6 PB7 Port D PD3 1 to PD6 1 Analog input 6 Internal bus Note 1 Not provided on the 32 pin package Note 2 Control signal for N channel open drain output Note 3 An external interrupt function is multiplexed on this pin Note 4 A peripheral module output is mul...

Page 296: ...O Port Configuration 3 Port3 P36 EXTAL Reading the port PDR PODR 1 ON 0 OFF PCR ODR0 ODR1 1 Port3 P37 XTAL Reading the port PDR PODR 1 ON 0 OFF PCR ODR0 ODR1 1 0 ON 1 OFF Main clock MOSCCR MOSTP MOFCR MOSEL Internal bus Internal bus PMR PMR Note 1 Control signal for N channel open drain output ...

Page 297: ... m that does not exist is reserved Make settings according to the description in section 17 4 Initialization of the Port Direction Register PDR Address es PORT1 PDR 0008 C001h PORT2 PDR 0008 C002h PORT3 PDR 0008 C003h PORT4 PDR 0008 C004h PORT7 PDR 0008 C007h PORT9 PDR 0008 C009h PORTA PDR 0008 C00Ah PORTB PDR 0008 C00Bh PORTD PDR 0008 C00Dh b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 Value af...

Page 298: ...C024h PORT7 PODR 0008 C027h PORT9 PODR 0008 C029h PORTA PODR 0008 C02Ah PORTB PODR 0008 C02Bh PORTD PODR 0008 C02Dh b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 B0 Pm0 Output Data Store Holds output data R W b1 B1 Pm1 Output Data Store R W b2 B2 Pm2 Output Data Store R W b3 B3 Pm3 Output Data Store R W b4 B4 Pm4 Output Dat...

Page 299: ...as general I O ports set the MOSCCR MOSTP bit to 1 main clock oscillator is stopped and the P36 and P37 control bits in the PORT3 PMR register to 0 use pin as general I O port Address es PORT1 PIDR 0008 C041h PORT2 PIDR 0008 C042h PORT3 PIDR 0008 C043h PORT4 PIDR 0008 C044h PORT7 PIDR 0008 C047h PORT9 PIDR 0008 C049h PORTA PIDR 0008 C04Ah PORTB PIDR 0008 C04Bh PORTD PIDR 0008 C04Dh PORTE PIDR 0008...

Page 300: ...The write value should be 0 Address es PORT1 PMR 0008 C061h PORT2 PMR 0008 C062h PORT3 PMR 0008 C063h PORT7 PMR 0008 C067h PORT9 PMR 0008 C069h PORTA PMR 0008 C06Ah PORTB PMR 0008 C06Bh PORTD PMR 0008 C06Dh PORTE PMR 0008 C06Eh b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 B0 Pm0 Pin Mode Control 0 Use pin as general I O po...

Page 301: ...0 0008 C096h PORTD ODR0 0008 C09Ah b7 b6 b5 b4 b3 b2 b1 b0 B6 B4 B2 B1 B0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 B0 Pm0 Output Type Select P10 P70 b0 0 CMOS output 1 N channel open drain b1 This bit is read as 0 The write value should be 0 PB0 b1 b0 0 0 CMOS output 0 1 N channel open drain 1 0 P channel open drain 1 0 Hi Z R W b1 B1 R W b2 B2 Pm1 Output Type Selec...

Page 302: ...08Fh PORT9 ODR1 0008 C093h PORTB ODR1 0008 C097h PORTD ODR1 0008 C09Bh b7 b6 b5 b4 b3 b2 b1 b0 B6 B4 B2 B0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 B0 Pm4 Output Type Select 0 CMOS output 1 N channel open drain R W b1 Reserved This bit is read as 0 The write value should be 0 R W b2 B2 Pm5 Output Type Select 0 CMOS output 1 N channel open drain R W b3 Reserved This ...

Page 303: ... read as 0 The write value should be 0 Address es PORT1 PCR 0008 C0C1h PORT2 PCR 0008 C0C2h PORT3 PCR 0008 C0C3h PORT4 PCR 0008 C0C4h PORT7 PCR 0008 C0C7h PORT9 PCR 0008 C0C9h PORTA PCR 0008 C0CAh PORTB PCR 0008 C0CBh PORTD PCR 0008 C0CDh b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 B0 Pm0 Input Pull Up Resistor Control 0 ...

Page 304: ... a pin that does not exist is reserved A reserved bit is read as 0 The write value should be 0 Address es PORT1 DSCR 0008 C0E1h PORT2 DSCR 0008 C0E2h PORT7 DSCR 0008 C0E7h PORT9 DSCR 0008 C0E9h PORTA DSCR 0008 C0EAh PORTB DSCR 0008 C0EBh PORTD DSCR 0008 C0EDh b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 B0 Pm0 Drive Capaci...

Page 305: ...umns in Table 17 3 and Table 17 4 indicate reserved bits A reserved bit should be set to 0 input or 1 output according to Table 17 3 and Table 17 4 When setting a value to a reserved bit access in byte units Table 17 3 PDR Register Settings in 48 Pin Packages Table 17 4 PDR Register Settings in 32 Pin Packages Port Symbol PDR Register b7 b6 b5 b4 b3 b2 b1 b0 PORT1 0 0 0 0 0 0 PORT2 0 0 0 0 0 PORT3...

Page 306: ...the main clock is not used set the MOSCCR MOSTP bit to 1 general port P36 When this pin is not used as port P36 either it is configured in the same way as port 1 2 7 9 A B D P37 XTAL When the main clock is not used set the MOSCCR MOSTP bit to 1 general port P37 When this pin is not used as port P37 either it is configured in the same way as port 1 2 7 9 A B D When the external clock is input to th...

Page 307: ...package Allocating the same function to more than one pin is prohibited Table 18 1 Allocation of Pin Functions to Multiple Pins 1 3 Module Function Channel Pin Functions Allocation Port Package 48 pin 32 pin Interrupt NMI NMI input PE2 Interrupt IRQ0 IRQ0 input P10 P93 PE2 IRQ1 IRQ1 input P11 P94 IRQ2 IRQ2 input P22 PB1 PD4 IRQ3 IRQ3 input P24 PB4 PD5 IRQ4 IRQ4 input P23 PA2 IRQ5 IRQ5 input P70 PB...

Page 308: ...input PB2 MTCLKD input PB7 ADSM0 output PB2 Port output enable 3 POE0 POE0 input P70 POE8 POE8 input PB4 P11 POE10 POE10 input PE2 Serial communications interface SCI1 RXD1 input SMISO1 input output SSCL1 input output PD5 PB7 TXD1 output SMOSI1 input output SSDA1 input output PD3 PB6 SCK1 input output PD4 CTS1 input RTS1 output SS1 input PD6 SCI5 RXD5 input SMISO5 input output SSCL5 input output P...

Page 309: ...put output PB2 12 bit A D converter AN000 input P40 AN001 input P41 AN002 input P42 AN003 input P43 AN004 input P44 AN005 input P45 AN006 input P46 AN007 input P47 ADTRG0 input P93 PB5 ADST0 output PD6 Clock frequency accuracy measurement circuit CACREF input P23 PB3 Comparator CMPC00 input P40 CMPC02 input P43 CMPC03 input P46 CMPC10 input P41 CMPC12 input P44 CMPC13 input P47 CMPC20 input P42 CM...

Page 310: ...et to 1 To set the PFSWE bit to 1 write 1 to the PFSWE bit after writing 0 to the B0WI bit B0WI Bit PFSWE Bit Write Disable Writing to the PFSWE bit is enabled only when the B0WI bit is set to 0 Address es 0008 C11Fh b7 b6 b5 b4 b3 b2 b1 b0 B0WI PFSWE Value after reset 1 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b5 to b0 Reserved These bits are read as 0 The write value should be 0 R W b6 ...

Page 311: ...lue Address es P10PFS 0008 C148h P11PFS 0008 C149h b7 b6 b5 b4 b3 b2 b1 b0 ASEL ISEL PSEL 4 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b4 to b0 PSEL 4 0 Pin Function Select These bits select the peripheral function For individual pin functions see Table 18 2 R W b5 Reserved This bit is read as 0 The write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 ...

Page 312: ...he peripheral function For individual pin functions see Table 18 3 R W b5 Reserved This bit is read as 0 The write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 Not used as IRQn input pin 1 Used as IRQn input pin P22 IRQ2 48 pin P23 IRQ4 48 pin P24 IRQ3 48 pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W Table 18 3 Register Settings for Input Output Pin F...

Page 313: ...44PFS 0008 C164h P45PFS 0008 C165h P46PFS 0008 C166h P47PFS 0008 C167h b7 b6 b5 b4 b3 b2 b1 b0 ASEL Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b6 to b0 Reserved These bits are read as 0 The write value should be 0 R W b7 ASEL Analog Input Function Select 0 Not used as an analog pin 1 Used as an analog pin P40 AN000 CMPC00 48 32 pin P41 AN001 CMPC10 48 32 pin P42 AN002 CM...

Page 314: ...0 PSEL 4 0 Pin Function Select These bits select the peripheral function For individual pin functions see Table 18 4 R W b5 Reserved This bit is read as 0 The write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 Not used as IRQn input pin 1 Used as IRQn input pin P70 IRQ5 48 pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W Table 18 4 Register Settings for ...

Page 315: ...eral function For individual pin functions see Table 18 5 R W b5 Reserved This bit is read as 0 The write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 Not used as IRQn input pin 1 Used as IRQn input pin P93 IRQ0 48 32 pin P94 IRQ1 48 32 pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W Table 18 5 Register Settings for Input Output Pin Function in 48 32 pi...

Page 316: ... bits select the peripheral function For individual pin functions see Table 18 6 R W b5 Reserved This bit is read as 0 The write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 Not used as IRQn input pin 1 Used as IRQn input pin PA2 IRQ4 input switch 48 pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W Table 18 6 Register Settings for Input Output Pin Functi...

Page 317: ...e write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 Not used as IRQn input pin 1 Used as IRQn input pin PB1 IRQ2 48 32 pin PB4 IRQ3 48 pin PB7 IRQ5 48 32 pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W Table 18 7 Register Settings for Input Output Pin Function in 48 32 pin PSEL 4 0 Settings Register Pin PB0PFS PB1PFS PB2PFS PB3PFS PB4PFS PB5PFS PB6PFS ...

Page 318: ... the peripheral function For individual pin functions see Table 18 8 R W b5 Reserved This bit is read as 0 The write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 Not used as IRQn input pin 1 Used as IRQn input pin PD4 IRQ2 48 pin PD5 IRQ3 48 pin PD6 IRQ5 48 pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W Table 18 8 Register Settings for Input Output Pin...

Page 319: ...Name Description R W b4 to b0 PSEL 4 0 Pin Function Select These bits select the peripheral function For individual pin functions see Table 18 9 R W b5 Reserved This bit is read as 0 The write value should be 0 R W b6 ISEL Interrupt Input Function Select 0 Not used as IRQn input pin 1 Used as IRQn input pin PE2 IRQ0 48 32 pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W Ta...

Page 320: ... target pin is cleared to 0 If a Pmn pin function control register is set while the PMR register of corresponding pin is 1 unexpected edges may be input through the input pin or unexpected pulses are output through the output pin 2 Only the allowed values functions should be specified in the Pmn pin function control registers If a value that is not allowed for the register is specified correct ope...

Page 321: ...eral purpose input by setting the given bits of the port mode register PMR and of the port direction register PDR to 0 and then set the ASEL bit in the Pmn pin function control register PmnPFS to 1 18 3 4 Note on PB1 Pin Input Level PB1 input level is specified to TTL when SCL is selected in the PB1PFS PSEL bit and SMBus is selected in the ICMR3 SMBS bit in RIIC At this time input levels of the PB...

Page 322: ... interlocked operation of MTU1 and MTU2 when TMDR3 LWA 1 Cascade connection operation available MTU3 MTU4 Through interlocked operation of MTU3 4 the positive and negative signals in six phases can be output in complementary PWM and reset synchronized PWM operation In complementary PWM mode transfer of values from buffer registers to temporary registers on crests or troughs of the timer counter va...

Page 323: ... output Input capture function 1 Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset synchronized PWM mode AC synchronous motor drive mode Phase counting mode Buffer operation Dead time compensation counter function DTC trigger sources TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGRALW TGRBLW compare match or input c...

Page 324: ...event Note 2 Underflow is available only in complementary PWM mode Note 3 For details on the module stop function refer to section 11 Low Power Consumption A D converter start request delaying function A D converter start request at a match between TADCORA and TCNT or A D converter start request at a match between TADCORB and TCNT Interrupt skipping 1 Skips TGRA compare match interrupts Skips TCIV...

Page 325: ... 2V TCRW Timer control register W TCR2W Timer control register 2W TMDR1 Timer mode register 1 TMDR2A Timer mode register 2 TMDR3 Timer mode register 3 TIOR Timer I O control register TIORH Timer I O control register H TIORL Timer I O control register L TIORU Timer I O control register U TIORV Timer I O control register V TIORW Timer I O control register W TIER Timer interrupt enable register TIER2...

Page 326: ... MTU1 MTIOC1A I O MTU1 TGRA input capture input output compare output PWM output pin MTIOC1B I O MTU1 TGRB input capture input output compare output PWM output pin MTU2 MTIOC2A I O MTU2 TGRA input capture input output compare output PWM output pin MTIOC2B I O MTU2 TGRB input capture input output compare output PWM output pin MTU3 MTIOC3A I O MTU3 TGRA input capture input output compare output PWM ...

Page 327: ...h edges PCLKB 2 at rising edge If phase counting mode is used on MTU1 and MTU2 the setting of these bits is ignored and the phase counting mode setting has priority Internal clock edge selection is valid when the count clock source is PCLKB 2 or slower When PCLKB 1 or the overflow underflow in another channel is selected for the count clock source a value can be written to these bits but counter o...

Page 328: ...TGRB compare match input capture 0 1 1 TCNT cleared by counter clearing in another channel performing synchronous clearing synchronous operation 1 1 0 0 TCNT clearing disabled 1 0 1 TCNT cleared by TGRC compare match input capture 2 1 1 0 TCNT cleared by TGRD compare match input capture 2 1 1 1 TCNT cleared by counter clearing in another channel performing synchronous clearing synchronous operatio...

Page 329: ... Refer to Table 19 6 to Table 19 9 for details PCB 1 0 Bits Phase Counting Mode Function Expansion Control These bits control extended functions for phase counting mode 2 3 and 5 in MTU1 and MTU2 Refer to section 19 3 6 Phase Counting Mode Address es MTU0 TCR2 0009 5328h MTU3 TCR2 0009 524Ch MTU4 TCR2 0009 524Dh b7 b6 b5 b4 b3 b2 b1 b0 TPSC2 2 0 Value after reset 0 0 0 0 0 0 0 0 Address es MTU1 TC...

Page 330: ...t the falling edge 1 x Counts at both edges R W b7 to b5 Reserved These bits are read as 0 The write value should be 0 R W Channel TCR2 register TCR register Description Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 TPSC2 2 TPSC2 1 TPSC2 0 TPSC 2 TPSC 1 TPSC 0 MTU0 0 0 0 0 0 0 Internal clock counts on PCLKB 1 0 0 0 0 0 1 Internal clock counts on PCLKB 4 0 0 0 0 1 0 Internal clock counts on PCLKB 16 0 0 0 0 ...

Page 331: ...x x Internal clock counts on PCLKB 2 0 1 0 x x x Internal clock counts on PCLKB 8 0 1 1 x x x Internal clock counts on PCLKB 32 1 0 0 x x x Internal clock counts on PCLKB 1024 1 0 1 x x x Setting prohibited 1 1 0 x x x Setting prohibited 1 1 1 x x x Setting prohibited Channel TCR2 register TCR register Description Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 TPSC2 2 TPSC2 1 TPSC2 0 TPSC 2 TPSC 1 TPSC 0 MTU...

Page 332: ...ternal clock counts on MTCLKB pin input 0 0 1 x x x Internal clock counts on PCLKB 2 0 1 0 x x x Internal clock counts on PCLKB 8 0 1 1 x x x Internal clock counts on PCLKB 32 1 0 0 x x x Setting prohibited 1 0 1 x x x Setting prohibited 1 1 0 x x x Setting prohibited 1 1 1 x x x Setting prohibited Channel TCR2 register TCR register Description Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 TPSC2 2 TPSC2 1 TPSC2 0...

Page 333: ... 5401h b7 b6 b5 b4 b3 b2 b1 b0 MD 3 0 Value after reset 0 0 0 0 0 0 0 0 Address es MTU3 TMDR1 0009 5202h MTU4 TMDR1 0009 5203h b7 b6 b5 b4 b3 b2 b1 b0 BFB BFA MD 3 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b3 to b0 MD 3 0 Mode Select These bits specify the timer operating mode Refer to Table 19 11 for details R W b4 BFA Buffer Operation A 0 TGRA and TGRC operate norma...

Page 334: ... 0 Refer to Figure 19 47 for an illustration of the Tb interval in complementary PWM mode BFB Bit Buffer Operation B This bit specifies whether to operate TGRB in the normal way or to use TGRB and TGRD together for buffer operation When TGRD is used as a buffer register TGRD input capture output compare does not take place in modes other than complementary PWM mode but compare match with TGRD occu...

Page 335: ... Register 2 TMDR2A TMDR2A specifies the double buffer function in complementary PWM mode 3 transfer at the crest and trough of the counter value TMDR2A value should be specified only while TCNT operation is stopped DRS Bit Double Buffer Select This bit enables or disables the double buffer function in complementary PWM mode Address es MTU TMDR2A 0009 5270h b7 b6 b5 b4 b3 b2 b1 b0 DRS Value after r...

Page 336: ...e when setting the LWA bit to 1 Initialize the registers TCNT TGRA and TGRB in MTU1 and MTU2 in advance before setting the LWA bit to 1 PHCKSEL Bit External Input Phase Clock Select When the MTU1 and MTU2 registers are combined for 32 bit phase counting mode or MTU2 phase counting mode this bit selects either the A or B phase signal from the external clock Refer to Table 19 50 Clock Input Pins in ...

Page 337: ...2 b1 b0 IOB 3 0 IOA 3 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b3 to b0 IOA 3 0 I O Control A 1 Refer to the following tables MTU0 TIORH Table 19 21 MTU1 TIOR Table 19 23 MTU2 TIOR Table 19 24 MTU3 TIORH Table 19 25 MTU4 TIORH Table 19 27 R W b7 to b4 IOB 3 0 I O Control B 1 Refer to the following tables MTU0 TIORH Table 19 13 MTU1 TIOR Table 19 15 MTU2 TIOR Table 19...

Page 338: ...5 TIORU 0009 5486h MTU5 TIORV 0009 5496h MTU5 TIORW 0009 54A6h b7 b6 b5 b4 b3 b2 b1 b0 IOC 4 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b4 to b0 IOC 4 0 I O Control C Refer to the following table MTU5 TIORU MTU5 TIORV MTU5 TIORW Table 19 29 R W b7 to b5 Reserved These bits are read as 0 The write value should be 0 R W Table 19 13 TIORH MTU0 Bit 7 Bit 6 Bit 5 Bit 4 Desc...

Page 339: ... match 0 1 1 1 Initial output is high Toggle output at compare match 1 0 0 0 Input capture register 1 Input capture at rising edge 1 0 0 1 Input capture at falling edge 1 0 1 x Input capture at both edges 1 1 x x Capture input source is the clock source for counting in MTU1 Input capture on counting up or down by MTU1 TCNT LWA 0 or MTU1 TCNTLW LWA 1 2 Table 19 15 TIOR MTU1 Bit 7 Bit 6 Bit 5 Bit 4 ...

Page 340: ...gh Toggle output at compare match 1 x 0 0 Input capture register Input capture at rising edge 1 x 0 1 Input capture at falling edge 1 x 1 x Input capture at both edges Table 19 17 TIORH MTU3 Bit 7 Bit 6 Bit 5 Bit 4 Description IOB 3 IOB 2 IOB 1 IOB 0 TGRB Register Function MTIOC3B Pin Function 0 0 0 0 Output compare register Output prohibited 0 0 0 1 Initial output is low Low output at compare mat...

Page 341: ... 1 1 0 Initial output is high High output at compare match 0 1 1 1 Initial output is high Toggle output at compare match 1 x 0 0 Input capture register 1 Input capture at rising edge 1 x 0 1 Input capture at falling edge 1 x 1 x Input capture at both edges Table 19 19 TIORH MTU4 Bit 7 Bit 6 Bit 5 Bit 4 Description IOB 3 IOB 2 IOB 1 IOB 0 TGRB Register Function MTIOC4B Pin Function 0 0 0 0 Output c...

Page 342: ...1 1 0 Initial output is high High output at compare match 0 1 1 1 Initial output is high Toggle output at compare match 1 x 0 0 Input capture register 1 Input capture at rising edge 1 x 0 1 Input capture at falling edge 1 x 1 x Input capture at both edges Table 19 21 TIORH MTU0 Bit 3 Bit 2 Bit 1 Bit 0 Description IOA 3 IOA 2 IOA 1 IOA 0 TGRA Register Function MTIOC0A Pin Function 0 0 0 0 Output co...

Page 343: ...at compare match 0 1 1 1 Initial output is high Toggle output at compare match 1 0 0 0 Input capture register 1 Input capture at rising edge 1 0 0 1 Input capture at falling edge 1 0 1 x Input capture at both edges 1 1 x x Capture input source is the clock source for counting in MTU1 Input capture on counting up or down by MTU1 TCNT LWA 0 or MTU1 TCNTLW LWA 1 2 Table 19 23 TIOR MTU1 Bit 3 Bit 2 Bi...

Page 344: ...gh Toggle output at compare match 1 x 0 0 Input capture register Input capture at rising edge 1 x 0 1 Input capture at falling edge 1 x 1 x Input capture at both edges Table 19 25 TIORH MTU3 Bit 3 Bit 2 Bit 1 Bit 0 Description IOA 3 IOA 2 IOA 1 IOA 0 TGRA Register Function MTIOC3A Pin Function 0 0 0 0 Output compare register Output prohibited 0 0 0 1 Initial output is low Low output at compare mat...

Page 345: ... 1 1 0 Initial output is high High output at compare match 0 1 1 1 Initial output is high Toggle output at compare match 1 x 0 0 Input capture register 1 Input capture at rising edge 1 x 0 1 Input capture at falling edge 1 x 1 x Input capture at both edges Table 19 27 TIORH MTU4 Bit 3 Bit 2 Bit 1 Bit 0 Description IOA 3 IOA 2 IOA 1 IOA 0 TGRA Register Function MTIOC4A Pin Function 0 0 0 0 Output c...

Page 346: ...tion MTIOC4C Pin Function 0 0 0 0 Output compare register 1 Output prohibited 0 0 0 1 Initial output is low Low output at compare match 0 0 1 0 Initial output is low High output at compare match 0 0 1 1 Initial output is low Toggle output at compare match 0 1 0 0 Output prohibited 0 1 0 1 Initial output is high Low output at compare match 0 1 1 0 Initial output is high High output at compare match...

Page 347: ...ibited 1 0 0 0 0 Input capture register 1 Setting prohibited 1 0 0 0 1 Input capture at rising edge 1 0 0 1 0 Input capture at falling edge 1 0 0 1 1 Input capture at both edges 1 0 1 x x Setting prohibited 1 1 0 0 0 Setting prohibited 1 1 0 0 1 Measurement of low pulse width of external input signal Capture at trough in complementary PWM mode 1 1 0 1 0 Measurement of low pulse width of external i...

Page 348: ... TCNTW and MTU5 TGRW compare match or input capture 1 Enables MTU5 TCNTW to be cleared to 0000h at MTU5 TCNTW and MTU5 TGRW compare match or input capture R W b1 CMPCLR5V TCNT Compare Clear 5V 0 Disables MTU5 TCNTV to be cleared to 0000h at MTU5 TCNTV and MTU5 TGRV compare match or input capture 1 Enables MTU5 TCNTV to be cleared to 0000h at MTU5 TCNTV and MTU5 TGRV compare match or input capture ...

Page 349: ...Description R W b0 TGIEA TGR Interrupt Enable A 0 Interrupt requests TGIA disabled 1 Interrupt requests TGIA enabled R W b1 TGIEB TGR Interrupt Enable B 0 Interrupt requests TGIB disabled 1 Interrupt requests TGIB enabled R W b2 TGIEC TGR Interrupt Enable C 0 Interrupt requests TGIC disabled 1 Interrupt requests TGIC enabled R W b3 TGIED TGR Interrupt Enable D 0 Interrupt requests TGID disabled 1 ...

Page 350: ...TGE Bit A D Converter Start Request Enable This bit enables or disables generation of A D converter start requests by TGRA input capture compare match MTU0 TIER2 TGIEE and TGIEF Bits TGR Interrupt Enable E and F Each bit enables or disables interrupt requests by compare match between MTU0 TCNT and MTU0 TGRn n E F TTGE2 Bit A D Converter Start Request Enable 2 Each bit enables or disables A D conve...

Page 351: ...IE5V TGIE5 W Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 TGIE5W TGR Interrupt Enable 5W 0 Interrupt requests TGIW5 disabled 1 Interrupt requests TGIW5 enabled R W b1 TGIE5V TGR Interrupt Enable 5V 0 Interrupt requests TGIV5 disabled 1 Interrupt requests TGIV5 enabled R W b2 TGIE5U TGR Interrupt Enable 5U 0 Interrupt requests TGIU5 disabled 1 Interrupt requests TGIU5 en...

Page 352: ...t indicates the direction in which TCNT is counting in MTU1 to MTU4 Address es MTU1 TSR 0009 5385h MTU2 TSR 0009 5405h b7 b6 b5 b4 b3 b2 b1 b0 TCFD Value after reset 1 1 0 0 0 0 0 0 Address es MTU3 TSR 0009 522Ch MTU4 TSR 0009 522Dh b7 b6 b5 b4 b3 b2 b1 b0 TCFD Value after reset 1 1 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b5 to b0 Reserved The read value is undefined The write value should...

Page 353: ... from MTU0 TGRF to MTU0 TGRE when they are used together for buffer operation In MTU3 and MTU4 this bit is reserved It is read as 0 and the write value should be 0 When a channel is not set to PWM mode do not set the TTSE bit in the channel to 1 Address es MTU0 TBTM 0009 5326h b7 b6 b5 b4 b3 b2 b1 b0 TTSE TTSB TTSA Value after reset 0 0 0 0 0 0 0 0 Address es MTU3 TBTM 0009 5238h MTU4 TBTM 0009 52...

Page 354: ...ut capture conditions 1 Includes the MTIOC1A pin in the MTU2 TGRA input capture conditions R W b1 I1BE Input Capture Enable 0 Does not include the MTIOC1B pin in the MTU2 TGRB input capture conditions 1 Includes the MTIOC1B pin in the MTU2 TGRB input capture conditions R W b2 I2AE Input Capture Enable 0 Does not include the MTIOC2A pin in the MTU1 TGRA input capture conditions 1 Includes the MTIOC...

Page 355: ...d in 8 or 16 bits it should be accessed in 32 bits The TCNTLW counter is a 32 bit readable writable counter Only one counter of this type is provided and is formed by combining MTU1 TCNT and MTU2 TCNT Such operation is only effective when TMDR3 LWA is 1 The TCNTLW counter is initialized to 0000 0000h by a reset This counter is read as 0000 0000h when TMDR3 LWA is 0 Refer to section 19 2 5 Timer Mo...

Page 356: ...RALW and TGRBLW must not be accessed in 8 or 16 bits it should be accessed in 32 bits The TGRnLW register n A B is a 32 bit readable writable register Two general registers of this type are provided and are formed by combining MTU1 TGRn and MTU2 TGRn Such operation is only effective when TMDR3 LWA is 1 The TGRnLW register is initialized to FFFF FFFFh by a reset but it is read as 0000 0000h when TM...

Page 357: ...pin in complementary PWM mode or reset synchronized PWM mode In any mode other than complementary PWM mode and reset synchronous PWM mode the output compare signal level from the MTIOC pin is retained If TIOR is written to while the CSTn bit is 0 the pin output level will be changed to the specified initial output value Address es MTU TSTRA 0009 5280h b7 b6 b5 b4 b3 b2 b1 b0 CST4 CST3 CST2 CST1 CS...

Page 358: ...0 0 0 0 Bit Symbol Bit Name Description R W b0 CSTW5 Counter Start W5 0 MTU5 TCNTW counting is stopped 1 MTU5 TCNTW performs count operation R W b1 CSTV5 Counter Start V5 0 MTU5 TCNTV counting is stopped 1 MTU5 TCNTV performs count operation R W b2 CSTU5 Counter Start U5 0 MTU5 TCNTU counting is stopped 1 MTU5 TCNTU performs count operation R W b7 to b3 Reserved These bits are read as 0 The write ...

Page 359: ...ynchronous Operation 0 0 MTU0 TCNT operates independently TCNT setting clearing is not related to other channels 1 MTU0 TCNT performs synchronous operation TCNT synchronous setting synchronous clearing is enabled R W b1 SYNC1 Timer Synchronous Operation 1 0 MTU1 TCNT operates independently TCNT setting clearing is not related to other channels 1 MTU1 TCNT performs synchronous operation TCNT synchr...

Page 360: ... When 1 is set to the TSTRA CST1 bit while SCH1 1 SCH0 Bit Synchronous Start 0 This bit controls synchronous start of MTU0 TCNT Clearing condition When 1 is set to the TSTRA CST0 bit while SCH0 1 Address es MTU TCSYSTR 0009 5282h b7 b6 b5 b4 b3 b2 b1 b0 SCH0 SCH1 SCH2 SCH3 SCH4 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b2 to b0 Reserved These bits are read as 0 The writ...

Page 361: ...condition When 0 is written to the RWE bit after reading RWE 1 Registers and Counters having Write Protection Capability against Accidental Modification TRWERA 24 registers MTUn TCR MTUn TCR2 MTUn TMDR1 MTUn TIORH MTUn TIORL MTUn TIER MTUn TGRA MTUn TGRB MTU TOERA MTU TOCR1A MTU TOCR2A MTU TGCRA MTU TCDRA MTU TDDRA and MTUn TCNT n 3 4 Address es MTU TRWERA 0009 5284h b7 b6 b5 b4 b3 b2 b1 b0 RWE Va...

Page 362: ... In MTU3 and MTU4 set TOERA prior to setting TIOR Set MTU TOERA after setting the CST3 and CST4 bits in MTU TSTRA to 0 refer to Figure 19 42 and Figure 19 45 Address es MTU TOERA 0009 520Ah b7 b6 b5 b4 b3 b2 b1 b0 OE4D OE4C OE3D OE4B OE4A OE3B Value after reset 1 1 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 OE3B Master Enable MTIOC3B 0 MTU output is disabled 1 1 MTU output is enabled R W b...

Page 363: ...M mode and complementary PWM mode The initial output is selected while the counter is stopped TOCS Bit TOC Select This bit selects either the TOCR1j or TOCR2j j A setting to be used for the output level in complementary PWM mode and reset synchronized PWM mode TOCL Bit TOC Register Write Protection This bit enables or disables write access to the TOCS OLSN and OLSP bits in TOCR1j j A PSYE Bit PWM ...

Page 364: ...vel Compare Match Output Up Counting Down Counting 0 High level Low level Low level High level 1 Low level High level High level Low level Table 19 31 Output Level Select Function Bit 1 Function OLSN Initial Output Active Level Compare Match Output Up Counting Down Counting 0 High level Low level High level Low level 1 Low level High level Low level High level MTU3 TCNT and MTU4 TCNT values MTU3 T...

Page 365: ...output level on MTIOC3D in reset synchronized PWM mode and complementary PWM mode Refer to Table 19 33 R W b2 OLS2P Output Level Select 2P 1 2 This bit selects the output level on MTIOC4A in reset synchronized PWM mode and complementary PWM mode Refer to Table 19 34 R W b3 OLS2N Output Level Select 2N 1 2 This bit selects the output level on MTIOC4C in reset synchronized PWM mode and complementary...

Page 366: ... Low level High level Table 19 34 MTIOCmA Output Level Select Function Bit 2 Function OLS2P Initial Output Active Level Compare Match Output Up Counting Down Counting 0 High level Low level Low level High level 1 Low level High level High level Low level Table 19 35 MTIOCmC Output Level Select Function Bit 3 Function OLS2N Initial Output Active Level Compare Match Output Up Counting Down Counting ...

Page 367: ...o TOCR2j Does not transfer data from the buffer register TOLBRj to TOCR2j 0 1 Transfers data from the buffer register TOLBRj to TOCR2j at the crest of the MTUn TCNT count Transfers data from the buffer register TOLBRj to TOCR2j when MTUm TCNT or MTUn TCNT is cleared 1 0 Transfers data from the buffer register TOLBRj to TOCR2j at the trough of the MTUn TCNT count Setting prohibited 1 1 Transfers da...

Page 368: ...vel Select 1N Specify the buffer value to be transferred to the OLS1N bit in TOCR2j R W b2 OLS2P Output Level Select 2P Specify the buffer value to be transferred to the OLS2P bit in TOCR2j R W b3 OLS2N Output Level Select 2N Specify the buffer value to be transferred to the OLS2N bit in TOCR2j R W b4 OLS3P Output Level Select 3P Specify the buffer value to be transferred to the OLS3P bit in TOCR2...

Page 369: ...MTIOC4A and MTIOC4B pins N Bit Negative Phase Output N Control This bit selects the level output or the reset synchronized PWM complementary PWM output for the negative phase output pins MTIOC3D MTIOC4C and MTIOC4D pins BDC Bit Brushless DC Motor This bit selects whether to make the functions of TGCRA effective or ineffective Address es MTU TGCRA 0009 520Dh b7 b6 b5 b4 b3 b2 b1 b0 BDC N P FB WF VF...

Page 370: ...r in complementary PWM mode respectively When a match occurs the TCNTSA counter switches the count direction down count to up count The initial value of TCDRA after a reset is FFFFh Table 19 39 Output Level Select Function Bit 2 Bit 1 Bit 0 Function WF VF UF MTIOC3B MTIOC4A MTIOC4B MTIOC3D MTIOC4C MTIOC4D U Phase V Phase W Phase U Phase V Phase W Phase 0 0 0 OFF OFF OFF OFF OFF OFF 0 0 1 ON OFF OF...

Page 371: ... Note TDDRA must not be accessed in 8 bits it should be accessed in 16 bits TDDRA is a 16 bit readable writable register used only in complementary PWM mode that specify the MTU3 TCNT and MTU4 TCNT counter offset value In complementary PWM mode when the MTU3 TCNT and MTU4 TCNT counters are cleared and then restarted the TDDRA value is loaded into the MTU3 TCNT counter and the count operation start...

Page 372: ... for MTU3 TDERA should be modified only while TCNT stops TDER Bit Dead Time Enable This bit specifies whether to generate dead time Clearing condition When 0 is written to TDER after reading TDER 1 Address es MTU TDERA 0009 5234h b7 b6 b5 b4 b3 b2 b1 b0 TDER Value after reset 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R W b0 TDER Dead Time Enable 0 No dead time is generated 1 Dead time is gen...

Page 373: ...ansfer set register TBTERA to 0 If link with interrupt skipping is enabled while interrupt skipping is disabled buffer transfer will not be performed Address es MTU TBTERA 0009 5232h b7 b6 b5 b4 b3 b2 b1 b0 BTE 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 BTE 1 0 Buffer Transfer Disable and Interrupt Skipping Link Setting These bits enable or disable transfer fro...

Page 374: ...R1A and TOCR2A are output regardless of the WRE bit setting The initial values specified in TOCR1A and TOCR2A are also output when synchronous clearing occurs in the Tb interval at the trough immediately after MTU3 TCNT and MTU4 TCNT start operation For the Tb interval at the trough in complementary PWM mode refer to Figure 19 47 Setting condition When 1 is written to the WRE bit after reading WRE...

Page 375: ...neration of an unexpected edge select the output compare function for the relevant pin in the timer I O control register or set the TMDR MD 3 0 bits to a value other than that for normal mode 0000b before doing so NFDEN Bit Noise Filter D Enable This bit disables or enables the noise filter for input from the MTIOCnD pin Since changing the value of the bit may lead to the internal generation of an...

Page 376: ...lter C Enable This bit disables or enables the noise filter for input from the MTCLKC pin Since changing the value of the bit may lead to the internal generation of an unexpected edge do so after stopping the internal counter NFDEN Bit Noise Filter D Enable This bit disables or enables the noise filter for input from the MTCLKD pin Since changing the value of the bit may lead to the internal gener...

Page 377: ...from the MTIC5W pin Since unexpected edges may be internally generated when the value of this bit is changed select the output compare function for the relevant pin in the timer I O control register NFCS 1 0 Bits Noise Filter Clock Select These bits set the sampling interval for the noise filters When setting the NFCS 1 0 bits wait for two cycles of the selected sampling interval before setting th...

Page 378: ...TGIA3 interrupt skipping 1 are linked R W b2 ITA4VE TCIV4 Interrupt Skipping Link Enable 1 2 3 0 A D converter start request signal TRG4AN and TCIV4 interrupt skipping 1 are not linked 1 A D converter start request signal TRG4AN and TCIV4 interrupt skipping 1 are linked R W b3 ITA3AE TGIA3 Interrupt Skipping Link Enable 1 2 3 0 A D converter start request signal TRG4AN and TGIA3 interrupt skipping...

Page 379: ...DCOBRB to the cycle set register MTU4 TADCORA MTU4 TADCORB at the crest of the MTU4 TCNT Data is transferred from the cycle set buffer register MTU4 TADCOBRA MTU4 TADCOBRB to the cycle set register MTU4 TADCORA MTU4 TADCORB when a compare match occurs between MTU3 TCNT and MTU3 TGRA Data is transferred from the cycle set buffer register MTU4 TADCOBRA MTU4 TADCOBRB to the cycle set register MTU4 TA...

Page 380: ...uld be equal to or greater than 4 PCLKB cycles the TADCORB update value should be the previous value 4 or greater or previous value 4 or smaller 2 When skipping function 2 is specified with the skipping count set to 1 or greater The difference between the TADCORA and TADCORB values should be equal to or greater than 2 The TADCORB compare interval should be equal to or greater than 2 PCLKB cycles t...

Page 381: ...ping function 2 TITMRA is used to select either of two skipping functions for the TITMRA register Address es MTU TITMRA 0009 523Ah b7 b6 b5 b4 b3 b2 b1 b0 TITM Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 TITM Interrupt Skipping Function Select Selects one of the two types of interrupt skipping functions 0 Selects interrupt skipping function 1 1 1 Selects interrupt skip...

Page 382: ...b4 T3ACOR 2 0 TGIA3 Interrupt Skipping Count Setting These bits specify the TGIA3 interrupt skipping count within the range from 0 to 7 1 For details refer to Table 19 43 R W b7 T3AEN T3AEN 0 TGIA3 interrupt skipping disabled 1 TGIA3 interrupt skipping enabled R W Table 19 42 Setting of Interrupt Skipping Count by T4VCOR 2 0 Bits Bit 2 Bit 1 Bit 0 Description T4VCOR 2 T4VCOR 1 T4VCOR 0 0 0 0 Does ...

Page 383: ...bits in TITCR1A T3ACNT 2 0 Bits TGIA3 Interrupt Counter Clearing conditions When the TITM bit in TITMRA is 1 When the T3AEN bit in TITCR1A is set to 0 When the T3ACOR 2 0 bits in TITCR1A are set to 000b When the T3ACNT 2 0 bits in TITCNT1A match the T3ACOR 2 0 bits in TITCR1A Address es MTU TITCNT1A 0009 5231h b7 b6 b5 b4 b3 b2 b1 b0 T3ACNT 2 0 T4VCNT 2 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symb...

Page 384: ...within the range from 0 to 7 For details refer to Table 19 44 R W b7 to b3 Reserved These bits are read as 0 The write value should be 0 R W Table 19 44 Setting of Interrupt Skipping Count by TRG4COR 2 0 Bits Bit 2 Bit 1 Bit 0 Description TRG4COR 2 TRG4COR 1 TRG4COR 0 0 0 0 Does not skip TRG4AN and TRG4BN interrupts 0 0 1 Sets the TRG4AN and TRG4BN interrupt skipping count to 1 0 1 0 Sets the TRG4...

Page 385: ... or TRG4BN interrupt is generated When the count reaches 0 and is reloaded the TRG4AN and TRG4BN interrupts become valid Clearing conditions When the TITM bit in TITMRA is 0 When the TRG4COR 2 0 bits in TITCR2A are set to 000b When the count of TRG4AN and TRG4BN occurrence matches the TRG4COR 2 0 value in TITCR2A Address es MTU TITCNT2A 0009 523Ch b7 b6 b5 b4 b3 b2 b1 b0 TRG4CNT 2 0 Value after re...

Page 386: ...tart request and settings Settings other than those listed in Table 19 45 are prohibited R W b7 to b5 Reserved These bits are read as 0 The write value should be 0 R W Table 19 45 Settings of A D Conversion Start Request for Generating Frame Synchronization Signal TADSTRS0 4 0 Source Descriptions 4 3 2 1 0 0 0 0 0 0 Source not selected 0 0 0 0 1 TRGA0N Compare match input capture in MTU0 TGRA 0 0 ...

Page 387: ...ple of Count Operation Setting Procedure Figure 19 4 shows an example of the count operation setting procedure Figure 19 4 Example of Count Operation Setting Procedure Periodic counter Free running counter Select count clock Operation selection Periodic counter Set period Select output compare register Select counter clearing source Start count operation Free running counter Start count operation ...

Page 388: ...mpare match is selected as the TCNT clearing source TCNT for the relevant channel performs periodic count operation TGR for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bits CCLR 2 0 in TCR After the settings have been made TCNT starts up count operation as a periodic counter when the CSTn bit in TSTRA or MTU5 TSTR is ...

Page 389: ... Procedure for Setting Waveform Output by Compare Match Enable waveform output mode Output selection 1 Waveform output Select waveform output mode Set output timing Start count operation 2 3 4 1 Enable TOERA output when outputting a waveform from the MTIOC pin of MTU3 and MTU4 2 Select initial value low output or high output and compare match output value low output high output or toggle output by...

Page 390: ... pin level does not change Figure 19 8 Example of low output and high output Operation n 0 to 4 Figure 19 9 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing on compare match B and settings have been made so that the output is toggled by both compare match A and compare match B Figure 19 9 Example of Toggle Output Operation n 0 t...

Page 391: ...sed as the input capture input for MTU0 and MTU1 PCLKB 1 should not be selected as the count clock used for input capture input Input capture will not be generated if PCLKB 1 is selected a Example of Input Capture Operation Setting Procedure Figure 19 10 shows an example of the input capture operation setting procedure Figure 19 10 Example of Input Capture Operation Setting Procedure 1 2 Input sel...

Page 392: ... falling edges have been selected as the MTIOCnA pin input capture input edge the falling edge has been selected as the MTIOCnB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT n 0 to 4 Figure 19 11 Example of Input Capture Operation n 0 to 4 TCNT value 0180h 0000h MTIOCnA TGRA Time 0010h 0005h 0160h 0005h 0160h 0010h TGRB 0180h MTIOCnB Counter c...

Page 393: ... 12 Example of Synchronous Operation Setting Procedure No Yes 1 3 5 4 5 2 Synchronous clearing Counter clearing Synchronous setting Start count Start count Set synchronous counter clearing Select counter clearing source Clearing source generation channel Synchronous clearing Synchronous setting Set TCNT Set synchronous operation Synchronous operation selection 1 Set to 1 in the SYNC bits in TSYRA ...

Page 394: ...ng has been set for the counter clearing source in MTU1 and MTU2 Three phase PWM waveforms are output from pins MTIOC0A MTIOC1A and MTIOC2A At this time synchronous setting and synchronous clearing by MTU0 TGRB compare match are performed for the TCNT counters in MTU0 to MTU2 and the data set in MTU0 TGRB is used as the PWM period For details of PWM modes refer to section 19 3 5 PWM Modes Figure 1...

Page 395: ...egister When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register This operation is illustrated in Figure 19 14 Figure 19 14 Compare Match Buffer Operation When TGR is an input capture register When an input capture occurs the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the ...

Page 396: ... match B In this example the TTSA bit in TBTM is set to 0 As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA This operation is repeated each time compare match A occurs For details of PWM modes refer to section 19 3 5 PWM Modes Figure 19 17 Example of Buffer Operation 1 1...

Page 397: ...A and TGRC Counter clearing by TGRA input capture has been set for TCNT and both rising and falling edges have been selected as the MTIOCnA pin input capture input edge n 0 to 4 As buffer operation has been set when the TCNT value is transferred to TGRA upon occurrence of input capture A the value previously stored in TGRA is simultaneously transferred to TGRC Figure 19 18 Example of Buffer Operat...

Page 398: ... When TCNT overflows FFFFh to 0000h When 0000h is written to TCNT during counting When TCNT becomes 0000h under the condition specified in the CCLR 2 0 bits in TCR Note TBTM must be modified only while TCNT stops Figure 19 19 shows an operation example in which PWM mode 1 is designated for MTU0 and buffer operation is designated for MTU0 TGRA and MTU0 TGRC The settings used in this example are MTU...

Page 399: ...ounting mode For simultaneous input capture of MTU1 TCNT and MTU2 TCNT during cascaded operation additional input capture input pins can be specified by the input capture control register TICCR The input capture condition is of edges in the signal produced by taking the logical OR of the input level on the main input pin and the input level on the added input pin Accordingly if either is at the hi...

Page 400: ...NT overflow underflow and MTU2 is set for phase counting mode 1 while MTU1 TCNT and MTU2 TCNT are cascaded MTU1 TCNT is incremented by MTU2 TCNT overflow and decremented by MTU2 TCNT underflow Figure 19 21 Cascaded Operation Example a 1 2 1 Set bits TPSC 2 0 in TCR to 111b in MTU1 to select MTU2 TCNT overflow underflow counting 2 Set the CSTn bit in TSTRA for the upper and lower channels to 1 to s...

Page 401: ...ted the MTIOC1A rising edge for the input capture timing while the MTU2 TIOR IOA 3 0 bits have selected the MTIOC2A rising edge for the input capture timing Under these conditions the rising edge of both MTIOC1A and MTIOC2A is used for the MTU1 TGRA input capture condition For the MTU2 TGRA input capture condition the MTIOC2A rising edge is used Figure 19 22 Cascaded Operation Example b MTU2 TCNT ...

Page 402: ...mple the IOA 3 0 bits in both MTU1 TIOR and MTU2 TIOR have selected both the rising and falling edges for the input capture timing Under these conditions the ORed result of MTIOC1A and MTIOC2A input is used for the MTU1 TGRA and MTU2 TGRA input capture conditions Figure 19 23 Cascaded Operation Example c MTU2 TCNT value Time 0514h 0514h 0513h 0512h 0513h 0512h C256h 6128h 2064h 9192h 0000h MTU1 TG...

Page 403: ...ch or input capture for the input capture timing while the IOA 3 0 bits in MTU2 TIOR have selected the MTIOC2A rising edge for the input capture timing Under these conditions as MTU1 TIOR has selected occurrence of MTU0 TGRA compare match or input capture for the input capture timing the MTIOC2A edge is not used for MTU1 TGRA input capture condition although the I2AE bit in TICCR has been set to 1...

Page 404: ... is set in TGRA or TGRC If the values set in paired TGRs are identical the output value does not change even when a compare match occurs In PWM mode 1 PWM waveforms in up to eight phases can be output b PWM Mode 2 PWM waveform output is generated using one TGR as the period register and the others as duty registers The level specified in TIOR is output at compare matches Upon counter clearing by a...

Page 405: ...WM Mode 1 Operation n 0 to 4 1 PWM mode Enable waveform output 2 3 4 5 6 7 Select count clock Select counter clearing source Set PWM mode Select waveform output level Set TGR Start count PWM mode 1 Enable TOERA output when outputting a waveform from the MTIOC pin of MTU3 and MTU4 2 Select the count clock source with bits TPSC 2 0 in TCR At the same time select the clock edge with bits CKEG 1 0 in ...

Page 406: ...low is set as the initial output value and high as the output value for the other TGR registers MTU0 TGRA to MTU0 TGRD and MTU1 TGRA outputting 5 phase PWM waveforms In this case the value set in MTU1 TGRB is used as the period and the values set in the other TGRs are used as the duty ratio Figure 19 27 Example of PWM Mode 2 Operation Time TCNT value Counter cleared by MTU1 TGRB compare match MTU1...

Page 407: ...ur simultaneously in period register and duty register 0 duty TCNT value TGRB modified TGRA 0000h MTIOCnA TGRB TGRA 0000h MTIOCnA TGRB TGRA 0000h MTIOCnA TGRB Time Time 100 duty TCNT value TGRB modified TGRB modified TGRB modified TGRB modified 100 duty TGRB modified TCNT value TGRB modified Output does not change when compare matches occur simultaneously in period register and duty register TGRB ...

Page 408: ... Counting Mode 19 3 6 1 16 Bit Phase Counting Mode When the MTU1 TMDR3 LWA is 0 16 bit phase counting mode can be set individually for MTU1 and MTU2 In 16 bit phase counting mode the phase difference between two external input clocks is detected and the 16 bit counter TCNT of the corresponding channel is incremented or decremented When 16 bit phase counting mode is specified an external clock is s...

Page 409: ...MDR3 LWA bit of MTU1 to 0 Set the TMDR1 MD 3 0 bits to select the phase counting mode 2 When the MTU2 is set to phase counting mode select the A or B phase input signal with the PHCKSEL bit in TMDR3 This setting is not necessary for MTU1 because MTCLKA and MTCLKB are always selected for A phase and B phase respectively 3 Set the CSTn bit in TSTRA to 1 to start the count operation 16 bit phase coun...

Page 410: ... is input from MTCLKA or MTCLKB and that for MTU2 is input from MTCLKC or MTCLKD a Phase Counting Mode 1 Figure 19 30 shows an example of operation in phase counting mode 1 and Table 19 51 summarizes the TCNT up counting and down counting conditions Figure 19 30 Example of Operation in Phase Counting Mode 1 Rising edge Falling edge Table 19 51 Up Counting and Down Counting Conditions in Phase Coun...

Page 411: ...Operation in Phase Counting Mode 2 When MTUn TCR2 PCB 1 0 00b n 1 2 Figure 19 32 Example of Operation in Phase Counting Mode 2 When MTUn TCR2 PCB 1 0 01b n 1 2 Figure 19 33 Example of Operation in Phase Counting Mode 2 When MTUn TCR2 PCB 1 0 1xb n 1 2 Time TCNT value MTCLKA MTU1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 Down counting Up counting Time TCNT value MTCLKA MTU1 MTCLKC MTU2 Down counting Up c...

Page 412: ...1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 Operation 00b High Not counted Don t care Low Low High Up counting High Not counted Don t care Low High Low Down counting 01b High Not counted Don t care Low Low Down counting High Not counted Don t care High Low High Up counting Low Not counted Don t care 1xb High Not counted Don t care Low Low Down counting High Up counting High Not counted Don t care Low Hi...

Page 413: ...19 53 summarizes the TCNT up counting and down counting conditions Figure 19 34 Example of Operation in Phase Counting Mode 3 When MTUn TCR2 PCB 1 0 00b n 1 2 Figure 19 35 Example of Operation in Phase Counting Mode 3 When MTUn TCR2 PCB 1 0 01b n 1 2 TCNT value MTCLKA MTU1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 Time Down counting Up counting TCNT value MTCLKA MTU1 MTCLKC MTU2 Time Down counting Up co...

Page 414: ...U1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 Operation 00b High Not counted Don t care Low Low High Up counting High Down counting Low Not counted Don t care High Low 01b High Down counting Low Not counted Don t care Low High High Low High Up counting Low Not counted Don t care 1xb High Down counting Low Not counted Don t care Low High Up counting High Down counting Low Not counted Don t care High Up co...

Page 415: ...g and down counting conditions Figure 19 37 Example of Operation in Phase Counting Mode 4 Rising edge Falling edge Table 19 54 Up Counting and Down Counting Conditions in Phase Counting Mode 4 MTCLKA MTU1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 Operation High Up counting Low Low Not counted Don t care High High Down counting Low High Not counted Don t care Low Up counting Down counting TCNT value MTCL...

Page 416: ...e 5 and Table 19 55 summarizes the TCNT up counting and down counting conditions Figure 19 38 Example of Operation in Phase Counting Mode 5 When MTUn TCR2 PCB 1 0 0xb n 1 2 Figure 19 39 Example of Operation in Phase Counting Mode 5 When MTUn TCR2 PCB 1 0 1xb n 1 2 TCNT value MTCLKA MTU1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 Time Up counting TCNT value MTCLKA MTU1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 ...

Page 417: ...nd Down Counting Conditions in Phase Counting Mode 5 PCB 1 0 MTCLKA MTU1 MTCLKC MTU2 MTCLKB MTU1 MTCLKD MTU2 Operation 0xb High Not counted Don t care Low Low High Up counting High Not counted Don t care Low High Low Up counting 1xb High Not counted Don t care Low Up counting Low Not counted Don t care High High Up counting Low Not counted Don t care High Low ...

Page 418: ...l period MTU0 TGRB is used for input capture with MTU0 TGRB and MTU0 TGRD operating in buffer mode The MTU1 count clock is designated as the MTU0 TGRB input capture source and the widths of 2 phase encoder 4 multiplication pulses are detected MTU1 TGRA and MTU1 TGRB for MTU1 are designated for the input capture function and MTU0 TGRA and MTU0 TGRC compare matches in MTU0 are selected as the input ...

Page 419: ...nnection 32 Bit Phase Counting Mode Figure 19 41 shows an example of the procedure for setting cascade connection 32 bit phase counting mode Figure 19 41 Procedure for Setting Cascade Connection 32 Bit Phase Counting Mode 32 bit Phase Counting Mode Combine MTU1 and MTU2 for access as a 32 bit unit Select the phase counting mode and external clock input pin 1 2 3 Counting starts in MTU1 and MTU2 32...

Page 420: ... for Reset Synchronized PWM Mode Channel Output Pin Description MTU3 MTIOC3B PWM output pin 1 MTIOC3D PWM output pin 1 negative phase waveform of PWM output 1 MTU4 MTIOC4A PWM output pin 2 MTIOC4C PWM output pin 2 negative phase waveform of PWM output 2 MTIOC4B PWM output pin 3 MTIOC4D PWM output pin 3 negative phase waveform of PWM output 3 Table 19 57 Register Settings for Reset Synchronized PWM...

Page 421: ... only when MTU3 and MTU4 are used 4 Set MTU3 TCNT and MTU4 TCNT to 0000h 5 MTU3 TGRA is the period register Set the PWM period in MTU3 TGRA Set the PWM output transition timing in MTU3 TGRB MTU4 TGRA and MTU4 TGRB Note that the setting values should be within the range of compare match with MTU3 TCNT X MTU3 TGRA X Set value 6 Set the PSYE bit in the TOCR1A register to enable or disable toggle outp...

Page 422: ...ers are cleared when a compare match occurs between MTU3 TCNT and MTU3 TGRA and then begin incrementing from 0000h The output from the PWM pins toggles every time a compare match occurs in MTU3 TGRB MTU4 TGRA and MTU4 TGRB and the counters are cleared Figure 19 43 Example of Reset Synchronized PWM Mode Operation When OLSN 1 and OLSP 1 in MTU3 TOCR1 and MTU4 TOCR1 MTU3 TCNT and MTU4 TCNT values Tim...

Page 423: ...MTU3 MTIOC3A Toggle output synchronized with PWM period or I O port MTIOC3B PWM output pin 1 MTIOC3C I O port 1 MTIOC3D PWM output pin 1 negative phase waveform output of PWM output 1 MTU4 MTIOC4A PWM output pin 2 MTIOC4C PWM output pin 2 negative phase waveform output of PWM output 1 MTIOC4B PWM output pin 3 MTIOC4D PWM output pin 3 negative phase waveform output of PWM output 1 Table 19 59 Regis...

Page 424: ...er A TCDRA Set MTU4 TCNT upper limit value 1 2 carrier period Maskable by TRWERA setting 1 Timer period buffer register A TCBRA TCDRA buffer register Readable writable Subcounter A TCNTSA Subcounter A for dead time generation Read only Temporary register 1A TEMP1A PWM output 1 MTU3 TGRB temporary register A Not readable writable Temporary register 1B TEMP1B PWM output 1 MTU3 TGRB temporary registe...

Page 425: ...nput MTIOC3D MTIOC4A MTIOC4B MTIOC4C MTIOC4D Registers that can be read or written from the CPU Registers that can be read or written from the CPU but for which access disabling can be set by TRWERA Registers that cannot be read or written from the CPU except for TCNTSA which can only be read MTU3 TGRA compare match interrupt MTU4 TCNT underflow interrupt MTU3 TCNT MTU4 TCNT MTU3 TGRA Registers th...

Page 426: ... channel generating the synchronous clear with MTU3 and MTU4 6 When MTU3 is used set the PWM output duty ratio in the duty registers MTU3 TGRB MTU4 TGRA and MTU4 TGRB and buffer registers MTU3 TGRD MTU4 TGRC and MTU4 TGRD Be sure to set the same value in each pair of the duty registers MTU3 TGRD MTU4 TGRC and MTU4 TGRD and buffer registers MTU3 TGRB MTU4 TGRA and MTU4 TGRB Only when the double buf...

Page 427: ...initialized to 0000h after a reset When the CST4 bit is set to 1 MTU4 TCNT counts up in synchronization with MTU3 TCNT and switches to down counting when MTU3 TCNT matches MTU3 TGRA On reaching 0000h MTU4 TCNT switches to up counting and the operation is repeated in this way TCNTSA is a read only counter It does not need to be initialized after a reset In counting up by MTU3 TCNT and MTU4 TCNT MTU...

Page 428: ...te as buffer registers for the timer period registers to temporary registers is also enabled Data is transferred to all five temporary registers at the same time When transfer is enabled in the Ta interval data written to a buffer register is transferred to the temporary register The data is not transferred to the temporary register in the Tb1 and Tb2 intervals Data enabled for transfer in this in...

Page 429: ...CNT 0000h Tb2 Output waveform is active low 6400h 0080h 6400h 6400h 0080h 0080h Transfer from temporary register to compare register Transfer from temporary register to compare register Ta Tb1 Ta Ta Tb2 MTU3 TGRA TCDRA MTU4 TGRA MTU4 TGRC TDDRA Buffer register MTU4 TGRC Temporary register Compare register MTU4 TGRA Positive phase output Negative phase output MTU3 TCNT MTU3 TCNT MTU4 TCNT TCNTSA ...

Page 430: ...oon as complementary PWM mode is set Set MTU4 TCNT to 0000h before setting complementary PWM mode Note The value set in MTU3 TGRC should be the sum of 1 2 the PWM period set in TCBRA and dead time Td set in TDDRA When dead time generation is disabled by TDERA TGRC should be set to 1 2 the PWM period 1 d PWM Output Level Setting In complementary PWM mode the PWM output level is set with bits OLSN a...

Page 431: ...ove settings PWM waveforms without dead time can be obtained Figure 19 48 shows an example of operation without dead time MTU3 and MTU4 Figure 19 48 Example of Operation without Dead Time MTU3 and MTU4 TCNTSA MTU3 TGRA TCDRA 1 TCDRA 0000h Buffer register MTU4 TGRC Temporary register Compare register MTU4 TGRA Positive phase output Initial output Initial output Negative phase output Ta MTU3 TCNT MT...

Page 432: ...er TCDRA setting TDDRA setting 2 2 The MTU3 TGRA and TCDRA settings are made by setting values in buffer registers MTU3 TGRC and TCBRA When data is written to MTU4 TGRD to enable transfers the values set in MTU3 TGRC and TCBRA are transferred simultaneously to the MTU3 TGRA and TCDRA with the transfer timing selected with the MTU3 TMDR1 MD 3 0 bits The new PWM period is reflected from the next cyc...

Page 433: ...emporary register value is transferred to the compare register at the data update timing set with MTU3 TMDR1 MD 3 0 bits Figure 19 50 shows an example of data updating in complementary PWM mode MTU3 and MTU4 This example shows the mode in which data is updated at both the counter crest and trough When updating buffer register data be sure to write to MTU4 TGRD at the end of the update Data is tran...

Page 434: ...ter to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value MTU3 TGRA Data1 Data2 Data3 Data4 Data5 Data6 Data1 Data1 Data2 Data3 Data4 Data6 Data2 Data3 Data4 Data5 Data6 Time Compare register Buffer register ...

Page 435: ... the TDDRA register Figure 19 51 shows an example of the initial output in complementary PWM mode An example of the waveform when the initial PWM duty ratio value is smaller than the TDDRA value is shown in Figure 19 52 Figure 19 51 Example of Initial Output in Complementary PWM Mode MTU3 and MTU4 1 Timer output control register settings TOCR1A OLSN bit 0 initial output high active level low TOCR1...

Page 436: ...er output control register settings TOCR1A OLSN bit 0 initial output high active level low TOCR1A OLSP bit 0 initial output high active level low MTU3 TCNT MTU4 TCNT value MTU4 TGRA TDDRA MTU3 TCNT MTU4 TCNT Initial output Time Active level MTU3 TCNT MTU4 TCNT count start TSTRA setting Complementary PWM mode TMDR1 setting Positive phase output Negative phase output MTU3 TCNT MTU4 TCNT TCNTSA ...

Page 437: ...ompare matches before c are ignored In most cases compare matches occur in the order a b c d or c d a b as shown in Figure 19 53 If compare matches deviate from the a b c d order since the time for which the negative phase is off is shorter than twice the dead time the positive phase is not turned on If compare matches deviate from the c d a b order since the time for which the positive phase is o...

Page 438: ... is active low Buffer operation is set for transfer at the crest and trough MTU4 TGRA TEMP2 OFF OFF ON OFF ON Don t care T1 interval T2 interval T1 interval Counter for generating a turn off timing Counter for generating a turn on timing a b c a b d MTU3 TGRA TCDRA TDDRA 0000h Positive phase output Negative phase output Output waveform is active low Buffer operation is set for transfer at the cres...

Page 439: ...s are ignored and the waveform does not change Figure 19 56 Example of 0 and 100 Waveform Output in Complementary PWM Mode MTU3 and MTU4 1 Figure 19 57 Example of 0 and 100 Waveform Output in Complementary PWM Mode MTU3 and MTU4 2 a b c d a b MTU3 TGRA TCDRA TDDRA 0000h Positive phase output Negative phase output Output waveform is active low Buffer operation is set for transfer at the crest and t...

Page 440: ...or transfer at the crest and trough MTU4 TGRA TEMP2 OFF Don t care 0 duty ratio output 100 duty ratio output ON T1 interval T2 interval T1 interval Counter for generating a turn off timing Counter for generating a turn on timing a b b d MTU3 TGRA TCDRA TDDRA 0000h Positive phase output Negative phase output a Output waveform is active low Buffer operation is set for transfer at the crest and troug...

Page 441: ...compare match between MTU3 TCNT and MTU3 TGRAand a compare match between MTU4 TCNT and 0000h pin is assigned for this toggle output The initial output is high level output Figure 19 61 Example of Toggle Output Waveform Synchronized with PWM Output MTU3 and MTU4 c a d b MTU3 TGRA TCDRA TDDRA 0000h Positive phase output Negative phase output MTU3 TCNT MTU4 TCNT Output waveform is active low Buffer o...

Page 442: ...l is specified through the TSYRA register and synchronous clearing is selected with MTU3 TCR CCLR 2 0 bits Figure 19 62 illustrates an example of this operation Use of this function enables a counter to be cleared and restarted through an external signal Figure 19 62 Counter Clearing Synchronized with Another Channel MTU3 and MTU4 TCNTSA MTU1 MTU1 TCNT MTU3 TCNT MTU4 TCNT Synchronous counter clear...

Page 443: ...3 When synchronous clearing occurs outside that interval the initial value specified by the OLSN and OLSP bits in TOCR1A is output Even in the Tb2 interval if synchronous clearing occurs in the initial value output period indicated by 1 in Figure 19 63 immediately after the counters start operation initial value output is not suppressed This function can be used in both channel combinations of MTU...

Page 444: ... Control at Synchronous Counter Clearing in Complementary PWM Mode MTU3 and MTU4 Stop count operation Output waveform control at synchronous counter clearing Set TWCRA and complementary PWM mode Start count operation Output waveform control at synchronous counter clearing 1 2 3 1 Set the TSTRA CST3 and TSTRA CST4 bits to 0 to stop operation of the timer counter TCNT Specify the TWCRA register whil...

Page 445: ...unter clearing occurs at timing 3 6 8 and 11 shown in Figure 19 63 respectively Figure 19 65 Example of Synchronous Clearing in Dead Time during Up Counting Timing 3 in Figure 19 63 TWCRA WRE Bit is 1 Figure 19 66 Example of Synchronous Clearing in Tb1 interval Timing 6 in Figure 19 63 TWCRA WRE Bit is 1 Output waveform is active low Synchronous clearing MTU3 TCNT MTU4 TCNT WRE bit 1 MTU3 TGRA MTU...

Page 446: ...g in Tb2 interval Timing 11 in Figure 19 63 TWCRA WRE Bit is 1 Output waveform is active low Synchronous clearing MTU3 TCNT MTU4 TCNT MTU3 TGRA MTU3 TGRB TCDRA TDDRA 0000h Positive phase output Negative phase output MTU3 TCNT MTU4 TCNT TCNTSA WRE bit 1 Output waveform is active low Synchronous clearing Initial value output is suppressed MTU3 TCNT MTU4 TCNT WRE bit 1 MTU3 TGRA MTU3 TGRB TCDRA TDDRA...

Page 447: ...ction only in complementary PWM mode 1 transfer at crest Note 2 Do not specify synchronous clearing by another channel do not set 1 in the SYNC0 to SYNC4 bits in the timer synchronous register TSYRA Note 3 Do not set the PWM duty value to 0000h Note 4 Do not set the PSYE bit in timer output control register 1 TOCR1A to 1 Figure 19 69 Example of Counter Clearing Operation by MTU3 TGRA Compare Match...

Page 448: ... the output on off state is switched when the UF VF or WF bit in TGCRA is set to 0 or 1 The driving waveforms are output from the 6 phase PWM output pins for complementary PWM mode With this 6 phase output while the output is turned on chopping output is available through complementary PWM mode output function by setting the N bit or P bit in TGCRA to 1 When the N bit or P bit is 0 the level outpu...

Page 449: ...e Switching through UF VF and WF Bit Settings 2 UF bit VF bit WF bit 6 phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin TGCRA When TGCRA BDC 1 TGCRA N 0 TGCRA P 0 TGCRA FB 1 and output active level high UF bit VF bit WF bit 6 phase output MTIOC3B pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin MTIOC3D pin When TGCRA BDC 1 TGCRA N 1 TGCRA P 1 TGCRA FB 1 and o...

Page 450: ...WM Mode Setting Procedure Note When a buffer register B is set to the buffer register A value symmetric PWM waveforms are output When a buffer register B is not set to the buffer register A value asymmetric PWM waveforms are output Figure 19 74 shows an example of double buffer operation Each register data is transferred as follows After MTU4 TGRD buffer A is written to data is transferred from MT...

Page 451: ...r Operation Buffer Write Value is Smaller than TDDRA Figure 19 76 Example of Double Buffer Operation Buffer Write Value is Greater than TCDRA MTU3 TGRA TCNTSA MTU4 TCNT MTU4 TCNT TCDRA MTU4 TGRB TDDRA MTU4 TGRD buffer A 1111h 1011h MTU4 TGRF buffer B Temp3A temporary A Temp3B temporary B MTU4 TGRB compare 1 1 1 2 2 2 Buffer A modified 1111h 1011h 1110h 1010h 1110h 1111h 1011h MTIOC4B output 1011h ...

Page 452: ...T4VENbits to 0 to clear the skipping counter a Example of Interrupt Skipping Function 1 Setting Procedure Figure 19 77 shows an example of the interrupt skipping function 1 setting procedure Figure 19 78 shows the periods during which interrupt skipping count can be changed Figure 19 77 Example of Interrupt Skipping Function 1 Setting Procedure Figure 19 78 Periods during which Interrupt Skipping ...

Page 453: ...mple of TGIA3 interrupt skipping in which the interrupt skipping count is set to three by the T3ACOR bits and the T3AEN bit is set to 1 in the TITCR1A register Figure 19 79 Example of Interrupt Skipping Function 1 Interrupt skipping period 00h 01h 02h 03h 00h 01h 02h 03h TGIA3 interrupt request generation timing Skipping counter TGIA3 interrupt signal Interrupt skipping period ...

Page 454: ... T4VEN bit settings in TITCR1A and buffer transfer enabled period Note This function must be used in combination with interrupt skipping function 1 When interrupt skipping is disabled the T3AEN and T4VEN bits in the timer interrupt skipping set register 1 TITCR1A are set to 0 or the skipping count set bits T3ACOR and T4VCOR in TITCR1A are set to 0 make sure that buffer transfer is not linked with ...

Page 455: ...CNT MTU4 TCNT Timing for modifying the buffer register Timing for modifying the buffer register Data Data Data Data1 Data1 Data1 Data2 Data2 Data2 2 2 1 1 0 0 TGIA3 generated 2 When the buffer register is modified after one carrier period has elapsed after a TGIA3 interrupt Buffer transfer enabled period TITCR1A T3ACOR 2 0 bits TITCNT1A T3ACNT 2 0 bits Buffer register Temporary register Compare re...

Page 456: ...sfer enabled period TITCNT1A T3AEN bit is set to 1 Buffer transfer enabled period TITCNT1A T4VEN bit is set to 1 Buffer transfer enabled period TITCNT1A T3AEN and T4VEN bits are set to 1 Skipping counter TITCNT1A T3ACNT 2 0 bits MTU3 TCNT MTU4 TCNT TCNTSA Skipping counter TITCNT1A T4VCNT 2 0 bits Note The skipping count is set to three Buffer transfer at the crest and trough is selected 1 2 3 0 1 ...

Page 457: ...shown below 24 registers in total MTU3 TCR MTU4 TCR MTU3 TCR2 MTU4 TCR2 MTU3 TMDR1 MTU4 TMDR1 MTU3 TIORH MTU4 TIORH MTU3 TIORL MTU4 TIORL MTU3 TIER MTU4 TIER MTU3 TCNT MTU4 TCNT MTU3 TGRA MTU4 TGRA MTU3 TGRB MTU4 TGRB MTU TOERA MTU TOCR1A MTU TOCR2A MTU TGCRA MTU TCDRA and MTU TDDRA This function can disable CPU access to the mode registers control registers and counters to prevent miswriting due ...

Page 458: ... request cycle Set the timing of transfer from cycle set buffer register Set linkage with interrupt skipping Enable A D converter start request delaying function A D converter start request delaying function 1 Set the cycle in the timer A D converter start request cycle buffer register MTU4 TADCOBRA or MTU4 TADCOBRB and timer A D converter start request cycle register MTU4 TADCORA or MTU4 TADCORB ...

Page 459: ...RG4AN or TRG4BN is issued When the UT4AE and UT4BE bits in the MTU4 TADCR register are set to 1 in complementary PWM mode A D converter start requests are enabled during the MTU4 TCNT up counting 0 MTU4 TCNT TCDR 1 When the DT4AE and DT4BE bits in the MTU4 TADCR register are set to 1 A D converter start requests are enabled during MTU4 TCNT down counting TCDR MTU4 TCNT 1 Refer to Figure 19 84 MTU4...

Page 460: ...mer A D converter start request cycle set registers when MTU4 TGRD register is updated There are notes on the timing for transferring data when using buffer transfer in complementary PWM mode For details section 19 6 27 Usage Notes on A D Converter Delaying Function in Complementary PWM Mode In modes other than complementary PWM mode set the BF1 bit in the MTU4 TADCR register to 0 Figure 19 85 Exa...

Page 461: ...VE ITB3AE and ITB4VE bits in the MTU4 TADCR register to 0 Note This function should be used in combination with interrupt skipping 1 When interrupt skipping is disabled the T3AEN and T4VEN bits in the timer interrupt skipping set register TITCR1A are set to 0 or the skipping count set bits T3ACOR and T4VCOR in TITCR1A are set to 0 make sure that A D converter start requests are not linked with int...

Page 462: ...AE 0 00h 01h 00h 01h 02h 00h 01h 00h 01h 02h MTU4 TCNT MTU4 TADCORA UT4AE 1 DT4AE 0 TGIA3 interrupt skipping counter TCIV4 interrupt skipping counter TGIA3 A D request enabled period TCIV4 A D request enabled period A D converter start request TRG4AN When linked with TGIA3 and TCIV4 interrupt skipping When linked with TGIA3 interrupt skipping When linked with TCIV4 interrupt skipping Note When the...

Page 463: ...unction 2 Figure 19 88 Example of Procedure for Setting Interrupt Skipping Function 2 b Example of Interrupt Skipping Function 2 Operation Figure 19 89 shows an example of interrupt skipping function 2 operation Figure 19 89 Example of Interrupt Skipping Function 2 Operation Skipping Count is Set to Four Set interrupt skipping mode Interrupt skipping 2 Set skipping count Interrupt skipping 2 1 Set...

Page 464: ... start Set TCSYSTR Stop timer counter 1 Set TSTRA to stop the counters used for synchronous start operation 2 Specify the necessary operation with appropriate registers such as TCR TMDR1 and TMDR2 3 In TCSYSTR set the bits corresponding to the counters to be started synchronously to 1 at the same time When TCSYSTR is set TSTRA for the target timer counters are automatically set appropriately the c...

Page 465: ...easurement and Figure 19 93 an example of external pulse width measurement Figure 19 92 Example of External Pulse Width Measurement Setting Procedure Figure 19 93 Example of External Pulse Width Measurement Measuring High Pulse Width 1 2 3 External pulse width measurement Select count clock Select pulse width measuring conditions Start count operation External pulse width measurement 1 Use the TPS...

Page 466: ...tput after measuring a delay of the inverter output from the complementary PWM output by an external pulse measurement function for MTU5 Figure 19 95 Figure 19 96 shows the procedure for setting dead time compensation using MTU3 to MTU5 For details on MTU5 operation at this time refer to section 19 3 13 TCNTU TCNTV and TCNTW Capture at Crest and or Trough in Complementary PWM Mode Figure 19 94 Mot...

Page 467: ...ndition specified in TIOR is satisfied the MTU5 TCNT value is captured in MTU5 TGR To prevent the generation of the MTU5 TGIm5 interrupt m U V W request under the capture condition specified in TIOR do not enable interrupt requests in MTU5 TIER 5 For U phase dead time compensation when an interrupt is generated at the crest TGIA3 or trough TCIV4 in complementary PWM mode read the MTU5 TGRU value c...

Page 468: ...s in the TCNTCMPCLR register are set to 1 TCNTU TCNTV and TCNTW become 0000h at the transfer timing for TGRU TGRV and TGRW Figure 19 97 shows an operation example in which TCNTU is used as a free running counter without being cleared and the value is captured in TGRU at the crest and trough in complementary PWM mode Figure 19 97 TCNTU Capture at Crest and Trough in Complementary PWM Operation Dead...

Page 469: ...When the A D conversion request signal to be monitored is selected by the TADSTRGR0 register a pulse signal is output from the ADSM0 pin that is at the high level when the A D conversion start request signal is generated and at the low level in the timer cycle used to generate the A D conversion start request signal Figure 19 99 shows an example of outputting the A D conversion start request frame...

Page 470: ...TGRB input capture compare match Possible TGIC0 MTU0 TGRC input capture compare match Possible TGID0 MTU0 TGRD input capture compare match Possible TCIV0 MTU0 TCNT overflow Not possible TGIE0 MTU0 TGRE compare match Not possible TGIF0 MTU0 TGRF compare match Not possible MTU1 TGIA1 MTU1 TGRA input capture compare match Possible TGIB1 MTU1 TGRB input capture compare match Possible TCIV1 MTU1 TCNT o...

Page 471: ...except MTU5 Note that an overflow interrupt is generated also when an underflow of the MTU4 TCNT occurs while operating in complementary PWM mode 3 Underflow Interrupt If the TIER TCIEU bit is set to 1 when a TCNT underflow occurs on a channel an interrupt is requested The MTU has two underflow interrupts one each for MTU1 and MTU2 19 4 2 DTC Trigger Sources 1 DTC Trigger Sources The DTC can be tr...

Page 472: ...om the MTU is selected as the trigger in the A D converter A D conversion will start 2 A D Conversion Start by Compare Match between MTU0 TCNT and MTU0 TGRE A D converter start request signal TRG0N is issued to the A D converter when a compare match occurs between MTU0 TCNT and MTU0 TGRE When a compare match occurs between MTU0 TCNT and MTU0 TGRE while the TTGE2 bit in MTU0 TIER2 is set to 1 A D c...

Page 473: ...A D converter start request by compare match between MTU4 TCNT and MTU4 TADCORA TADCORB Table 19 63 Interrupt Sources and A D Converter Start Request Signals Target Registers Interrupt Source A D Converter Start Request Signal MTU0 TGRA and MTU0 TCNT Input capture compare match TRGA0N MTU1 TGRA and MTU1 TCNT TRGA1N MTU2 TGRA and MTU2 TCNT TRGA2N MTU3 TGRA and MTU3 TCNT TRGA3N MTU4 TGRA and MTU4 TC...

Page 474: ...al clock operation phase counting mode Figure 19 100 Count Timing in Internal Clock Operation MTU0 to MTU4 Figure 19 101 Count Timing in Internal Clock Operation MTU5 Figure 19 102 Count Timing in External Clock Operation MTU0 to MTU4 Figure 19 103 Count Timing in External Clock Operation Phase Counting Mode Internal clock TCNT TCNT count clock Falling edge Rising edge N 1 N N 1 PCLKB Internal clo...

Page 475: ...nd TGR the compare match signal is not generated until the TCNT count clock is generated Figure 19 104 shows the output compare output timing normal mode or PWM mode and Figure 19 105 shows the output compare output timing complementary PWM mode or reset synchronized PWM mode Figure 19 104 Output Compare Output Timing Normal Mode or PWM Mode n 0 to 4 m A to D Figure 19 105 Output Compare Output Ti...

Page 476: ...RX13T Group 19 Multi Function Timer Pulse Unit 3 MTU3c 3 Input Capture Signal Timing Figure 19 106 shows the input capture signal timing Figure 19 106 Input Capture Input Signal Timing TCNT N N 1 N TGR Input capture signal Input capture input N 2 N 2 PCLKB ...

Page 477: ...ed and Figure 19 109 shows the timing when counter clearing on input capture is specified Figure 19 107 Counter Clear Timing Compare Match MTU0 to MTU4 Figure 19 108 Counter Clear Timing Compare Match MTU5 Figure 19 109 Counter Clear Timing Input Capture MTU0 to MTU5 TCNT Counter clear signal Compare match signal TGR N N 0000h PCLKB N N 1 0000h TCNT Counter clear signal Compare match signal TGR PC...

Page 478: ...ration Figure 19 110 Buffer Operation Timing Compare Match Figure 19 111 Buffer Operation Timing Input Capture Figure 19 112 Buffer Operation Timing When TCNT Cleared n N N n n 1 TGRA TGRB Compare match signal TGRC TGRD TCNT PCLKB N n n N N N 1 Input capture signal TCNT TGRA TGRB TGRC TGRD N 1 PCLKB n N N n 0000h TCNT clear signal TCNT TGRA TGRB TGRE TGRC TGRD TGRF Buffer transfer signal PCLKB ...

Page 479: ...porary Register TCNTSA Stopped Figure 19 114 Transfer Timing from Buffer Register to Temporary Register TCNTSA Operating Figure 19 115 Transfer Timing from Temporary Register to Compare Register n N n N 0000h Buffer register Buffer register write signal Temporary register transfer signal TCNTS Temporary register PCLKB n N n N P x P 0000h Buffer register Buffer register write signal TCNTS Temporary...

Page 480: ...ch Figure 19 116 and Figure 19 117 show the TGI interrupt request signal timing when a compare match occurs Figure 19 116 TGI Interrupt Timing Compare Match MTU0 to MTU4 Figure 19 117 TGI Interrupt Timing Compare Match MTU5 TGR TCNT TCNT count clock N N N 1 Compare match signal Interrupt signal PCLKB TGR TCNT N N 1 N TCNT count clock Compare match signal Interrupt signal PCLKB ...

Page 481: ...Capture Figure 19 118 and Figure 19 119 show the TGI interrupt request signal timing when an input capture occurs Figure 19 118 TGI Interrupt Timing Input Capture MTU0 to MTU4 Figure 19 119 TGI Interrupt Timing Input Capture MTU5 TGR TCNT Input capture signal N N Interrupt signal PCLKB TGR TCNT Input capture signal N N Interrupt signal PCLKB ...

Page 482: ... request signal timing when an overflow is generated Figure 19 121 shows the TCIU interrupt request signal timing when an underflow is generated Figure 19 120 TCIV Interrupt Timing Figure 19 121 TCIU Interrupt Timing TCNT count clock Interrupt signal TCNT overflow 0000h FFFFh Overflow signal PCLKB TCNT count clock Interrupt signal TCNT underflow FFFFh 0000h Underflow signal PCLKB ...

Page 483: ...etween the two input clocks must be at least three PCLKB cycles and the pulse width must be at least five PCLKB cycles Figure 19 122 shows the input clock conditions in phase counting mode Figure 19 122 Phase Difference Overlap and Pulse Width in Phase Counting Mode 19 6 3 Note on Period Setting When counter clearing on compare match is set TCNT is cleared in the final state in which it matches th...

Page 484: ...ure 19 123 shows the timing in this case Figure 19 123 Contention between TCNT Write and Clear Operations 19 6 5 Contention between TCNT Write and Increment Operations If incrementing occurs in a TCNT write cycle TCNT write operation takes precedence and TCNT is not incremented Figure 19 124 shows the timing in this case Figure 19 124 Contention between TCNT Write and Increment Operations Counter ...

Page 485: ...GR Write Operation and Compare Match 19 6 7 Contention between Buffer Register Write Operation and Compare Match If a compare match occurs in the T2 state in a TGR write cycle the data before write operation is transferred to TGR by the buffer operation Figure 19 126 shows the timing in this case Figure 19 126 Contention between Buffer Register Write Operation and Compare Match Compare match signa...

Page 486: ...peration Figure 19 127 shows the timing in this case Figure 19 127 Contention between Buffer Register Write and TCNT Clear Operations 19 6 9 Contention between TGR Read Operation and Input Capture If an input capture signal is generated in a TGR read cycle the data before input capture transfer is read Figure 19 128 shows the timing in this case Figure 19 128 Contention between TGR Read Operation ...

Page 487: ...he TGR write operation is not performed in MTU0 to MTU4 In MTU5 the TGR write operation is performed and the input capture signal is generated Figure 19 129 and Figure 19 130 show the timing in this case Figure 19 129 Contention between TGR Write Operation and Input Capture MTU0 to MTU4 Figure 19 130 Contention between TGR Write Operation and Input Capture MTU5 Input capture signal TCNT M TGR M Wr...

Page 488: ...Capture If an input capture signal is generated in the buffer register write cycle the buffer operation takes precedence and the buffer register write operation is not performed Figure 19 131 shows the timing in this case Figure 19 131 Contention between Buffer Register Write Operation and Input Capture Input capture signal TCNT N TGR N M M Buffer register Written by CPU PCLKB ...

Page 489: ...MTU1 TCNT count clock is selected as the input capture source of MTU0 MTU0 TGRA to MTU0 TGRD work in input capture mode In addition when the MTU0 TGRC compare match input capture is selected as the input capture source of MTU1 TGRB MTU1 TGRB works in input capture mode Figure 19 132 shows the timing in this case When setting the TCNT clearing function in cascaded operation be sure to synchronize M...

Page 490: ...mentary PWM Mode When modifying the PWM period set register MTU3 TGRA timer period data register TCDRA and duty set registers MTU3 TGRB MTU4 TGRA and MTU4 TGRB in complementary PWM mode be sure to use buffer operation In addition set the BFA and BFB bits in MTU4 TMDR1 to 0 The MTIOC4C pin cannot output waveforms if the BFA bit in MTU4 TMDR1 is set to 1 Likewise the MTIOC4D pin cannot output wavefo...

Page 491: ...ctions as a buffer register for MTU3 TGRA At the same time MTU4 TGRC functions as a buffer register for MTU4 TGRA While the MTU3 TGRC and MTU3 TGRD are operating as buffer registers a TGImn interrupt m C D n 3 4 is not generated Figure 19 134 shows an example of MTU3 TGR MTU4 TGR MTIOC3 and MTIOC4 operation with the BFA and BFB bits in MTU3 TMDR1 set to 1 and the BFA and BFB bits in MTU4 TMDR1 set...

Page 492: ...FFFh and the MTU3 TGRA compare match selected as the counter clearing source MTU3 TCNT and MTU4 TCNT count up to FFFFh then a compare match occurs with MTU3 TGRA and MTU3 TCNT and MTU4 TCNT are both cleared In this case a TCIVn interrupt n 3 4 is not generated Figure 19 135 shows an example of operation in reset synchronized PWM mode with period register MTU3 TGRA set to FFFFh and the MTU3 TGRA co...

Page 493: ...36 Contention between Overflow and Counter Clearing 19 6 18 Contention between TCNT Write Operation and Overflow Underflow If TCNT counts up or down in a TCNT write cycle and an overflow or an underflow occurs the TCNT write operation takes precedence A TCIVn interrupt n 0 to 4 nor a TCIUn interrupt n 1 2 is not generated Figure 19 137 shows the operation timing when there is contention between TC...

Page 494: ...to 00h The output level in negative phase when the TDERA TDER bit is set to 0 in complementary PWM mode the dead time is not generated does not depend on the setting of the TOCR1A OLSN bit It is equivalent to the inverted level of positive phase output based on the setting of the TOCR1A OLSP bit 19 6 21 Simultaneous Input Capture in MTU1 TCNT and MTU2 TCNT in Cascade Connection When timer counters...

Page 495: ... TADCORA and MTU4 TADCORB must be at least two The interval of comparison for MTU4 TADCORB must be at least two cycles of PCLKB the updated value of MTU4 TADCORB is set to the previous value plus or minus at least two 19 6 23 Notes When Complementary PWM Mode Output Protection Function is Not Used The complementary PWM mode output protection function is initially enabled For details refer to secti...

Page 496: ...n Figure 19 138 synchronous clearing occurs within the dead time period for PWM output Condition 2 In portions 10 and 11 of the initial output inhibition period in Figure 19 139 synchronous clearing occurs when any condition from among MTU3 TGRB TDDRA MTU4 TGRA TDDRA or MTU4 TGRB TDDRA is satisfied The following method avoids the above phenomena Ensure that synchronous clearing proceeds with the v...

Page 497: ...Applies MTU3 TGRA TGR TDDR Positive phase output Negative phase output 10 11 10 11 Initial output inhibition Note PWM output is active low Dead time Tb interval Tb interval Synchronous clearing 0 Although there is no period for output of the active level over this interval synchronous clearing leads to output of the active level MTU3 TCNT MTU4 TCNT Dead time is eliminated ...

Page 498: ...erter Delaying Function in Complementary PWM Mode When data is transferred from a buffer register at the trough of the MTU4 TCNT counter while the MTU4 TADCOBRA and MTU4 TADCOBRB registers are set to 0 and the UT4AE and UT4BE bits in the MTU4 TADCR register are set to 1 no A D converter start request is issued during up counting immediately after transfer Refer to Figure 19 141 When data is transf...

Page 499: ...quest is not issued during up counting immediately after buffer transfer trough 1 UT4AE DT4AE BF 1 0 Bits in TADCR Note 1 An A D converter start request is issued when TCDR 1 MTU4 TADCOBRA TADCOBRB 1 is written MTU4 TADCORA MTU4 TADCOBRA A D converter start request TRG4AN Complementary PWM mode UT4AE 0 DT4AE 1 BF 1 0 01b transfer at crest Write the same value as TCDR to MTU4 TADCOBRA 1 An A D conv...

Page 500: ... I O ports MTU output can be disabled through TIOR settings Complementary PWM output MTIOC3B MTIOC3D MTIOC4A MTIOC4B MTIOC4C and MTIOC4D should be specified through TOERA setting For PWM output pins output can also be cut by hardware using port output enable 3 POE3 The pin initialization procedures for re setting due to an error during operation and the procedures for restarting in a different mod...

Page 501: ...utput to the corresponding pins MTIOCnC or MTIOCnD n 0 3 4 When a pin is configured for MTIOCnC or MTIOCnD it enters high impedance state To output a specified level set the pin to general output port In PWM mode 1 if either TGRC or TGRD operates as a buffer register waveforms are not output to the corresponding pins MTIOCnC or MTIOCnD n 0 3 4 When a pin is configured for MTIOCnC or MTIOCnD it ent...

Page 502: ... the initial output is a high level and a low level is output on compare match occurrence 5 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 6 Start count operation by setting the TSTRA register 7 Output goes low on compare match occurrence 8 An error occurs 9 Allow non active level output by setting the pins as general output ports using the port direction r...

Page 503: ...mode 2 after re setting Figure 19 145 Error Occurrence in Normal Mode Recovery in PWM Mode 2 1 to 10 are the same as in Figure 19 143 11 Set PWM mode 2 12 Initialize the pins with the TIOR register In PWM mode 2 a waveform is not output to the pin that corresponds to the TGR register used as a period register To output a specified level make necessary settings for general output ports in the port ...

Page 504: ... to 10 are the same as in Figure 19 143 11 Set the phase counting mode 12 Initialize the pins with the TIOR register 13 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 14 Restart operation by setting the TSTRA register Note The phase counting mode can only be selected for MTU1 and MTU2 and therefore the TOERA register setting is not necessary 1 Reset MTU mod...

Page 505: ...of the normal mode waveform generation block with the TIOR register 13 Disable output in MTU3 and MTU4 with the TOERA register 14 Select the complementary PWM output level and enable or disable cyclic output with registers TOCR1A and TOCR2A 15 Set complementary PWM mode 16 Enable output in MTU3 and MTU4 with the TOERA register 17 Set MTU output using the MPC and port mode registers PMR correspondi...

Page 506: ...n Figure 19 147 14 Select the reset synchronized PWM output level and enable or disable cyclic output with registers TOCR1A and TOCR2A 15 Set reset synchronized PWM mode 16 Enable output in MTU3 and MTU4 with the TOERA register 17 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 18 Restart operation by setting the TSTRA register 1 Reset MTU module output Hi Z...

Page 507: ... 1 the MTIOCnB side is not initialized 5 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 6 Start count operation by setting the TSTRA register 7 Output goes low on compare match occurrence 8 An error occurs 9 Allow non active level output by setting the pins as general output ports using the port direction registers PDR port output data registers PODR and po...

Page 508: ...e 2 after re setting Figure 19 151 Error Occurrence in PWM Mode 1 Recovery in PWM Mode 2 1 to 10 are the same as in Figure 19 149 11 Set PWM mode 2 12 Initialize the pins with the TIOR register In PWM mode 2 a waveform is not output to the pin that corresponds to the TGR register used as a period register To output a specified level make necessary settings for general output ports in the port dire...

Page 509: ...he same as in Figure 19 149 11 Set the phase counting mode 12 Initialize the pins with the TIOR register 13 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 14 Restart operation by setting the TSTRA register Note The phase counting mode can only be selected for MTU1 and MTU2 and therefore the TOERA register setting is not necessary 1 Reset MTU module output H...

Page 510: ...ation of the PWM mode 1 waveform generation block with the TIOR register 14 Disable output in MTU3 and MTU4 with the TOERA register 15 Select the complementary PWM output level and enable or disable cyclic output with registers TOCR1A and TOCR2A 16 Set complementary PWM mode 17 Enable output in MTU3 and MTU4 with the TOERA register 18 Set MTU output using the MPC and port mode registers PMR corres...

Page 511: ...set synchronized PWM output level and enable or disable cyclic output with registers TOCR1A and TOCR2A 16 Set reset synchronized PWM mode 17 Enable output in MTU3 and MTU4 with the TOERA register 18 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 19 Restart operation by setting the TSTRA register 1 Reset MTU module output Hi Z Hi Z Hi Z MTIOC3A MTIOC3B MTIOC...

Page 512: ...Un TGRA register is used as a period register 4 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 5 Start count operation by setting the TSTRA register 6 Output goes low on compare match occurrence 7 An error occurs 8 Allow non active level output by setting the pins as general output ports using the port direction registers PDR port output data registers PODR...

Page 513: ... the TIOR register In PWM mode 1 waveforms are not output to the MTIOCnB MTIOCnD pins To output a specified level make necessary settings for general output ports in the port direction registers PDR and port output data registers PODR of the I O ports 12 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 13 Restart operation by setting the TSTRA register 1 Rese...

Page 514: ...tting the TSTRA register 16 Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Phase Counting Mode Figure 19 158 shows a case in which an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re setting Figure 19 158 Error Occurrence in PWM Mode 2 Recovery in Phase Counting Mode 1 to 9 are the same as in Figure 19 155 10 Set the phase counting mode...

Page 515: ... MTU output using the MPC and port mode registers PMR corresponding to the I O ports 5 Start count operation by setting the TSTRA register 6 Output goes low on compare match occurrence 7 An error occurs 8 Allow non active level output by setting the pins as general output ports using the port direction registers PDR port output data registers PODR and port mode registers PMR of the I O ports 9 Sto...

Page 516: ...e 1 11 Initialize the pins with the TIOR register In PWM mode 1 waveforms are not output to the MTIOCnB MTIOCnD pins To output a specified level make necessary settings for general output ports in the port direction registers PDR and port output data registers PODR of the I O ports 12 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 13 Restart operation by se...

Page 517: ...he TSTRA register 20 Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Phase Counting Mode Figure 19 162 shows a case in which an error occurs in phase counting mode and operation is restarted in phase counting mode after re setting Figure 19 162 Error Occurrence in Phase Counting Mode Recovery in Phase Counting Mode 1 to 9 are the same as in Figure 19 159 10 This st...

Page 518: ...sters PMR corresponding to the I O ports 6 Start count operation by setting the TSTRA register 7 The complementary PWM waveform is output on compare match occurrence 8 An error occurs 9 Allow non active level output by setting the pins as general output ports using the port direction registers PDR port output data registers PODR and port mode registers PMR of the I O ports 10 Stop count operation ...

Page 519: ...2 Initialize the pins with the TIOR register In PWM mode 1 waveforms are not output to the MTIOCnB MTIOCnD pins To output a specified level make necessary settings for general output ports in the port direction registers PDR and port output data registers PODR of the I O ports 13 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 14 Restart operation by setting...

Page 520: ...nd duty settings at the time of stopping the counter Figure 19 165 Error Occurrence in Complementary PWM Mode Recovery in Complementary PWM Mode 1 1 to 10 are the same as in Figure 19 163 11 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 12 Restart operation by setting the TSTRA register 13 The complementary PWM waveform is output on compare match occurrenc...

Page 521: ...e the same as in Figure 19 163 11 Set normal mode and make new settings MTU output goes low 12 Disable output in MTU3 and MTU4 with the TOERA register 13 Select the complementary PWM output level and enable or disable cyclic output with registers TOCR1A and TOCR2A 14 Set complementary PWM mode 15 Enable output in MTU3 and MTU4 with the TOERA register 16 Set MTU output using the MPC and port mode r...

Page 522: ...63 11 Set normal mode MTU output goes low 12 Disable output in MTU3 and MTU4 with the TOERA register 13 Select the reset synchronized PWM output level and enable or disable cyclic output with registers TOCR1A and TOCR2A 14 Set reset synchronized PWM mode 15 Enable output in MTU3 and MTU4 with the TOERA register 16 Set MTU output using the MPC and port mode registers PMR corresponding to the I O po...

Page 523: ...ding to the I O ports 6 Start count operation by setting the TSTRA register 7 The reset synchronized PWM waveform is output on compare match occurrence 8 An error occurs 9 Allow non active level output by setting the pins as general output ports using the port direction registers PDR port output data registers PODR and port mode registers PMR of the I O ports 10 Stop count operation by setting the...

Page 524: ...negative phase output goes high 12 Initialize the pins with the TIOR register In PWM mode 1 waveforms are not output to the MTIOCnB MTIOCnD pins To output a specified level make necessary settings for general output ports in the port direction registers PDR and port output data registers PODR of the I O ports 13 Set MTU output using the MPC and port mode registers PMR corresponding to the I O port...

Page 525: ...s in Figure 19 168 11 Disable output in MTU3 and MTU4 with the TOERA register 12 Select the complementary PWM output level and enable or disable cyclic output with registers TOCR1A and TOCR2A 13 Set complementary PWM mode MTU cyclic output pin goes low 14 Enable output in MTU3 and MTU4 with the TOERA register 15 Set MTU output using the MPC and port mode registers PMR corresponding to the I O port...

Page 526: ...etting Figure 19 171 Error Occurrence in Reset Synchronized PWM Mode Recovery in Reset Synchronized PWM Mode 1 to 10 are the same as in Figure 19 168 11 Set MTU output using the MPC and port mode registers PMR corresponding to the I O ports 12 Restart operation by setting the TSTRA register 13 The reset synchronized PWM waveform is output on compare match occurrence 3 TMDR RPWM Hi Z Hi Z Hi Z MTU ...

Page 527: ... simultaneous conduction between the output signal levels at the active level over one or more cycles on the following combination of pins MTU Complementary PWM Output Pins 1 MTIOC3B and MTIOC3D 2 MTIOC4A and MTIOC4C 3 MTIOC4B and MTIOC4D The SPOER register setting Detection that the main clock oscillator had stopped oscillating Detection of the comparator C CMPC outputs Function Each of the POE0 ...

Page 528: ...quest interrupt request generating circuit High impedance request interrupt request generating circuit High impedance request interrupt request generating circuit POECR1 to POECR5 SPOER OCSR1 MTIOC3B MTIOC3D MTIOC4A MTIOC4C MTIOC4B MTIOC4D PCLK 8 PCLK 16 PCLK 128 High impedance request signal or interrupt request signal OEI3 for MTU0 pin Interrupt request signal OEI4 Main clock oscillation stop de...

Page 529: ...ination I O Description MTIOC3B and MTIOC3D Output The MTU complementary PWM output pins MTU3 and MTU4 pins are in the high impedance state when two pins of the set simultaneously output the active level low level when the MTU TOCR1A OLSP bit is 0 or high level when the OLSP bit is 1 while the OLSEN bit in the ALR1 register is 0 and the MTU TOCR1A TOCS bit is 0 low level when the OLS1P OLS1N OLS2P...

Page 530: ...o write 0 to this flag For details refer to section 20 3 7 Recover from High Impedance State Address es POE ICSR1 0008 C4C0h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 POE0F PIE1 POE0M 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 POE0M 1 0 POE0 Mode Select b1 b0 0 0 Accepts a request on the falling edge of POE0 pin input 0 1 Accepts a r...

Page 531: ...e 0 to this flag Address es POE ICSR3 0008 C4C8h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 POE8F POE8E PIE3 POE8M 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 POE8M 1 0 POE8 Mode Select b1 b0 0 0 Accepts a request on the falling edge of POE8 pin input 0 1 Accepts a request when POE8 pin input has been sampled 16 times at PCLK 8 clock p...

Page 532: ...1 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 POE10 F POE10 E PIE4 POE10M 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 POE10M 1 0 POE10 Mode Select b1 b0 0 0 Accepts a request on the falling edge of POE10 pin input 0 1 Accepts a request when POE10 pin input has been sampled 16 times at PCLK 8 clock pulses and all are low level 1 0 Accepts a request when POE...

Page 533: ...least 10 cycles of PCLK after this flag becomes 1 and write 0 to this flag while the OSTDSR OSTDF flag is 0 Writing 0 to this flag while the OSTDSR OSTDF flag is 1 cannot clear this flag After clearing this flag confirm that the flag has actually been modified to 0 Setting condition When oscillation stop is detected Clearing condition By writing 0 to the OSTSTF flag after reading OSTSTF 1 Address ...

Page 534: ...When the MTIOC4A and MTIOC4C pins simultaneously go to the active level 1 for at least one cycle of PCLK while the POECR2 MTU4ACZE bit is 1 When the MTIOC4B and MTIOC4D pins simultaneously go to the active level 1 for at least one cycle of PCLK while the POECR2 MTU4BDZE bit is 1 Note 1 The setting condition is judged only by the level of the pin regardless the setting of the MPC PmnPFS register Cl...

Page 535: ...s the low level and to 1 sets the high level as the active level for detection of simultaneous conduction OLSG1B Bit MTIOC4C Pin Active Level Setting This bit sets the active level of the MTIOC4C output Specifically setting the OLSG1B bit to 0 sets the low level and to 1 sets the high level as the active level for detection of simultaneous conduction Address es POE ALR1 0008 C4DAh b15 b14 b13 b12 ...

Page 536: ...l of the MTIOC4D output Specifically setting the OLSG2B bit to 0 sets the low level and to 1 sets the high level as the active level for detection of simultaneous conduction OLSEN Bit Active Level Setting Enable This bit enables or disables of the active level settings in the OLSGnm bits n 0 to 2 m A B Clearing the OLSEN bit to 0 disables the OLSGnm bits in which case the active levels of the MTU ...

Page 537: ...pedance Enable This bit specifies whether to put the outputs of the MTU0 pins in the high impedance state Setting condition By writing 1 to the MTUCH0HIZ bit Clearing conditions Reset By writing 0 to the MTUCH0HIZ bit after reading MTUCH0HIZ 1 Address es POE SPOER 0008 C4CAh b7 b6 b5 b4 b3 b2 b1 b0 MTUC H0HIZ MTUC H34HIZ Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 MTUC...

Page 538: ... High Impedance Enable This bit specifies whether to switch the MTIOC0D output of PB0 to the high impedance state when any of the ICSR3 POE8F flag SPOER MTUCH0HIZ bit and ICSR6 OSTSTF flag when the OSTSTE bit is 1 or as additionally Address es POE POECR1 0008 C4CBh b7 b6 b5 b4 b3 b2 b1 b0 MTU0D 1ZE MTU0C 1ZE MTU0B 1ZE MTU0A 1ZE MTU0D ZE MTU0C ZE MTU0B ZE MTU0A ZE Value after reset 0 0 0 0 0 0 0 0 ...

Page 539: ...F flag SPOER MTUCH0HIZ bit and ICSR6 OSTSTF flag when the OSTSTE bit is 1 or as additionally specified in the POECR5 register the ICSRn POEmF flag n 1 4 m 0 10 or POECMPFR CnFLAG flag n 0 to 2 is set to 1 MTU0C1ZE Bit MTIOC0C PD5 Pin High Impedance Enable This bit specifies whether to switch the MTIOC0C output of PD5 to the high impedance state when any of the ICSR3 POE8F flag SPOER MTUCH0HIZ bit ...

Page 540: ...2 is set to 1 MTU3BDZE Bit MTIOC3B MTIOC3D Pin High Impedance Enable This bit specifies whether to switch the MTIOC3B output and MTIOC3D output to the high impedance state when at least one of the OCSR1 OSF1 flag ICSR1 POE0F flag SPOER MTUCH34HIZ bit ICSR6 OSTSTF flag when the OSTSTE bit is 1 or as additionally specified in the POECR4 register the ICSRn POEmF flag n 3 4 m 8 10 or POECMPFR CnFLAG f...

Page 541: ...IOC4B MTIOC4D Address es POE POECR4 0008 C4D0h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IC4ADD MT34ZE IC3ADD MT34ZE CMADD MT34ZE Value after reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 Bit Symbol Bit Name Description R W b0 CMADDMT34ZE MTU3 and MTU4 High Impedance Condition CFLAG Add 0 Does not add the flags to the conditions to put the output in the high impedance state 1 Adds the flags to...

Page 542: ...OC0A MTIOC0B MTIOC0C MTIOC0D Address es POE POECR5 0008 C4D2h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IC4ADD MT0ZE IC1ADD MT0ZE CMADD MT0ZE Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Bit Symbol Bit Name Description R W b0 CMADDMT0ZE MTU0 High Impedance Condition CFLAG Add 0 Does not add the flags to the conditions to put the output in the high impedance state 1 Adds the flags ...

Page 543: ...ator is set to inverted output the input voltage changes from higher to lower than the reference voltage Clearing condition By writing 0 to the CnFLAG flag after reading CnFLAG 1 Address es POE POECMPFR 0008 C4E6h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 C2FLA G C1FLA G C0FLA G Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 C0FLAG Comparator C...

Page 544: ...9 b8 b7 b6 b5 b4 b3 b2 b1 b0 POERE Q2 POERE Q1 POERE Q0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 POEREQ0 Comparator Channel 0 High Impedance Request Enable 0 Disables high impedance request generation upon comparator output detection 1 Enables high impedance request generation upon comparator output detection R W 1 b1 POEREQ1 Comparator Channel 1 Hig...

Page 545: ... POEREQ1 bit is 1 When the POECMPFR C2FLAG flag becomes 1 while the POECR4 CMADDMT34ZE bit is 1 and the POECMPSEL POEREQ2 bit is 1 Detection of oscillation stop When the ICSR6 OSTSTF flag becomes 1 while the ICSR6 OSTSTE bit is 1 2 MTU4 pins MTIOC4A MTIOC4C When one of the following conditions is satisfied while the POECR2 MTU4ACZE bit is 1 the pins become high impedance Operation for detection of...

Page 546: ...C2FLAG flag becomes 1 while the POECR4 CMADDMT34ZE bit is 1 and the POECMPSEL POEREQ2 bit is 1 Detection of oscillation stop When the ICSR6 OSTSTF flag becomes 1 while the ICSR6 OSTSTE bit is 1 4 MTU0 pin PB3 MTIOC0A When one of the following conditions is satisfied while the POECR1 MTU0AZE bit is 1 the pin becomes high impedance Operation for detection of the POE8 input level When the ICSR3 POE8F...

Page 547: ...POECR1 MTU0BZE bit is 1 the pin becomes high impedance Operation for detection of the POE8 input level When the ICSR3 POE8F flag becomes 1 while the ICSR3 POE8E bit is 1 SPOER setting When the SPOER MTUCH0HIZ bit is set to 1 Conditions added by POECR5 When the ICSR1 POE0F flag becomes 1 while the POECR5 IC1ADDMT0ZE bit is 1 When the ICSR4 POE10F flag becomes 1 while the POECR5 IC4ADDMT0ZE bit and ...

Page 548: ... ICSR1 POE0F flag becomes 1 while the POECR5 IC1ADDMT0ZE bit is 1 When the ICSR4 POE10F flag becomes 1 while the POECR5 IC4ADDMT0ZE bit and the ICSR4 POE10E bit are 1 Comparator output detection When the POECMPFR C0FLAG flag becomes 1 while the POECR5 CMADDMT0ZE bit is 1 and the POECMPSEL POEREQ0 bit is 1 When the POECMPFR C1FLAG flag becomes 1 while the POECR5 CMADDMT0ZE bit is 1 and the POECMPSE...

Page 549: ...CMPFR C1FLAG flag becomes 1 while the POECR5 CMADDMT0ZE bit is 1 and the POECMPSEL POEREQ1 bit is 1 When the POECMPFR C2FLAG flag becomes 1 while the POECR5 CMADDMT0ZE bit is 1 and the POECMPSEL POEREQ2 bit is 1 Detection of oscillation stop When the ICSR6 OSTSTF flag becomes 1 while the ICSR6 OSTSTE bit is 1 11 MTU0 pin PB0 MTIOC0D When one of the following conditions is satisfied while the POECR...

Page 550: ...E SPOER MTUCH0HIZ MTU0AZE MTU0A1ZE MTU0BZE POECR2 Hi Z request signal for MTIOC0A PB3 pin Hi Z request signal for MTIOC0A PD3 pin Hi Z request signal for MTIOC0B PB2 pin MTU0B1ZE Hi Z request signal for MTIOC0B PD4 pin MTU0CZE Hi Z request signal for MTIOC0C PB1 pin MTU0DZE Hi Z request signal for MTIOC0D PB0 pin POECR1 Comparator output detection signal Oscillation stop detection signal ICSR3 POE...

Page 551: ...nge from a high to low level is input to the POE0 POE8 and POE10 pins the outputs of the pins multiplexed with MTU complementary PWM output pins and MTU0 pins are in the high impedance state The falling edge is detected after the level is sampled with PCLK Input a low level for at least one PCLK clock to the POE0 POE8 and POE10 pins Figure 20 4 shows a sample timing after the level changes in inpu...

Page 552: ... impedance state after the sampling clock is input is the same in both falling edge detection and in low level detection Figure 20 5 Operation when A Low Level Detection is Selected 20 3 2 Output Level Compare Operation Figure 20 6 shows an example of the output level compare operation for the combination of MTIOC3B and MTIOC3D The operation is the same for the other pin combinations Figure 20 6 O...

Page 553: ...y PWM output pins and MTU0 pins can be added by setting the POECR4 and POECR5 registers For instance the settings listed below can be added as high impedance control conditions for the MTU3 and MTU4 pins Setting the POECR4 CMADDMT34ZE bit to 1 adds comparator output detection Setting the POECR4 IC3ADDMT34ZE bit to 1 and adds the input level detection by the POE8 pin Setting the POECR4 IC4ADDMT34ZE...

Page 554: ...CnFLAG flag is not set to 1 again in the following cases This flag is cleared without confirmation that the analog input signal has returned to a normal value and 1 the analog input signal remains above the reference voltage when the comparator is set to non inverted output or 2 the analog input signal remains below the reference voltage when the comparator is set to inverted output The outputs wh...

Page 555: ...1 OSF1 flag becomes 1 while the OCSR1 OIE1 bit is 1 OEI3 Output enable interrupt 3 POE8F When the ICSR3 POE8F flag becomes 1 while the ICSR3 PIE3 bit is 1 OEI4 Output enable interrupt 4 POE10F When the ICSR4 POE10F flag is set to 1 while the ICSR4 PIE4 bit is 1 1 Start Set the ALR1 OLSG0A and OLSG0B bits to 0 and the ALR1 OLSEN bit to 1 Set the POECR2 MTU3BDZE bit to 1 Make the setting to operate ...

Page 556: ...trol When the MTU is Not Selected If high impedance control for a pin having a multiplexed MTU pin function is enabled by setting the POECR1 and POECR2 registers and the high impedance control condition is satisfied the output is to be in the high impedance state even if the MTU function is not selected for the pin on which it is multiplexed 20 6 3 When the POE is Not Used The high impedance contr...

Page 557: ...gram Table 21 1 CMT Specifications Item Description Count clocks Four frequency dividing clocks One clock from PCLK 8 PCLK 32 PCLK 128 and PCLK 512 can be selected for each channel Interrupt A compare match interrupt can be requested for each channel Low power consumption function Module stop state can be set Control circuit Clock selection Module bus CMI0 PCLK 32 PCLK 512 PCLK 128 PCLK 8 Control ...

Page 558: ...reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 STR0 Count Start 0 0 CMT0 CMCNT count is stopped 1 CMT0 CMCNT count is started R W b1 STR1 Count Start 1 0 CMT1 CMCNT count is stopped 1 CMT1 CMCNT count is started R W b15 to b2 Reserved These bits are read as 0 The write value should be 0 R W Address es CMT0 CMCR 0008 8002h CMT1 CMCR 0008 8008h b15 b14 b13 b12 b11 b10 b...

Page 559: ...lue in the CMCOR register match the CMCNT counter is set to 0000h At the same time a compare match interrupt CMIn n 0 1 is generated 21 2 4 Compare Match Constant Register CMCOR The CMCOR register is a readable writable register to set a value for compare match with the CMCNT counter Address es CMT0 CMCNT 0008 8004h CMT1 CMCNT 0008 800Ah b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value ...

Page 560: ...erated The CMCNT counter then starts counting up again from 0000h Figure 21 2 shows the operation of the CMCNT counter Figure 21 2 CMCNT Counter Operation 21 3 2 CMCNT Count Timing As the count clock to be input to the CMCNT counter one of four frequency dividing clocks PCLK 8 PCLK 32 PCLK 128 and PCLK 512 obtained by dividing the peripheral module clock PCLK can be selected with the CMCR CKS 1 0 ...

Page 561: ...Match Interrupt Generation When the CMCNT counter and the CMCOR register match a compare match interrupt CMIn n 0 1 is generated A compare match signal is generated at the last state in which the values match the timing when the CMCNT counter updates the matched count value That is after a match between the CMCOR register and the CMCNT counter the compare match signal is not generated until the ne...

Page 562: ...riting to the CMCNT counter clearing the CMCNT counter has priority over writing to it In this case the CMCNT counter is not written to Figure 21 5 shows the timing to clear the CMCNT counter Figure 21 5 Conflict between CMCNT Counter Writing and Compare Match 21 5 3 Conflict between CMCNT Counter Writing and Incrementing If writing to the counter and the incrementing conflict the writing has prio...

Page 563: ... power consumption states depends on the register setting 2 A counter underflows or a refresh error occurs only in register start mode Window function Window start and end positions can be specified refresh permitted and refresh prohibited periods Reset output sources Down counter underflows Refreshing outside the refresh permitted period refresh error Non maskable interrupt sources Down counter u...

Page 564: ...f the IWDT Figure 22 1 IWDT Block Diagram IWDT control circuit 14 bit counter IWDTRR IWDT refresh register IWDTCR IWDT control register IWDTSR IWDT status register IWDTRCR IWDT reset control register IWDTCSTPR IWDT count stop control register IWDT reset output IWDTCSTPR Option function select register 0 OFS0 IWDTCLK IWDTCLK 16 IWDTCLK 64 IWDTCLK 32 IWDTCLK 128 IWDTCLK 256 Reset control circuit Int...

Page 565: ...ue selected by the IWDTTOPS 1 0 bits in option function select register 0 OFS0 in auto start mode In register start mode counting down starts from the value selected by setting the IWDTCR TOPS 1 0 bits in the first refresh operation after a reset is released When 00h is written the read value is 00h When a value other than 00h is written the read value is FFh For details of the refresh operation r...

Page 566: ... 0 RPES 1 0 CKS 3 0 TOPS 1 0 Value after reset 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 Bit Symbol Bit Name Description R W b1 b0 TOPS 1 0 Timeout Period Select b1 b0 0 0 128 cycles 007Fh 0 1 512 cycles 01FFh 1 0 1024 cycles 03FFh 1 1 2048 cycles 07FFh R W b3 b2 Reserved These bits are read as 0 Writing to these bits has no effect R b7 to b4 CKS 3 0 Clock Divide Ratio Select b7 b4 0 0 0 0 No division 0 0 1...

Page 567: ... bits select the IWDTCLK clock divide ratio from among divide by 1 16 32 64 128 and 256 Combination with the TOPS 1 0 bit setting a count period between 128 and 524288 cycles of the IWDTCLK clock can be selected for the IWDT Table 22 2 Settings and Timeout Periods CKS 3 0 Bits TOPS 1 0 Bits Clock Divide Ratio Timeout Period Number of Cycles Cycles of IWDTCLK b7 b6 b5 b4 b1 b0 0 0 0 0 0 0 No divisi...

Page 568: ...nderflows The interval between the window start position and window end position is the refresh permitted period and the other periods are refresh prohibited periods Figure 22 2 shows the relationship between of the RPSS 1 0 and RPES 1 0 bit setting and the refresh permitted and refresh prohibited periods Figure 22 2 RPSS 1 0 and RPES 1 0 Bit Settings and the Refresh Permitted Period Table 22 3 Re...

Page 569: ...es that the counter has not underflowed Write 0 to the UNDFF flag to set the value to 0 Writing 1 has no effect REFEF Flag Refresh Error Flag This bit is used to confirm whether or not a refresh error performing a refresh operation during a refresh prohibited period The value 1 indicates that a refresh error has occurred The value 0 indicates that no refresh error has occurred Write 0 to the REFEF...

Page 570: ... option function select register 0 OFS0 are enabled The bit setting mode to the IWDTRCR register can also be made in the OFS0 register For details refer to section 22 3 8 Correspondence between Option Function Select Register 0 OFS0 and IWDT Registers Address es IWDT IWDTRCR 0008 8036h b7 b6 b5 b4 b3 b2 b1 b0 RSTIR QS Value after reset 1 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b6 to b0 R...

Page 571: ...r details refer to section 22 3 8 Correspondence between Option Function Select Register 0 OFS0 and IWDT Registers SLCSTP Bit Sleep Mode Count Stop Control This bit selects whether to stop counting at a transition to sleep mode software standby mode or deep sleep mode 22 2 6 Option Function Select Register 0 OFS0 For option function select register 0 OFS0 refer to section 22 3 8 Correspondence bet...

Page 572: ...ut in the IWDTRCR register and the counter stop control at transitions to low power consumption states in the IWDTCSTPR register Then refresh the counter to start counting down from the value selected by setting the IWDTCR TOPS 1 0 bits Thereafter as long as the program continues normal operation and the counter is refreshed in the refresh permitted period the value in the counter is re set each t...

Page 573: ...tus flag cleared Counter value Refresh permitted period Refresh prohibited period 100 75 50 25 0 RES pin IWDTCR register Refresh the counter active high REFEF flag UNDFF flag Reset output from IWDT active high Counting starts Counting starts Counting starts Writing to the register is valid H H L H L Writing to the register is invalid Underflow Refresh error Writing to the register is invalid Refre...

Page 574: ...iod the value in the counter is re set each time the counter is refreshed and counting down continues The IWDT does not output the reset signal as long as this continues However if the counter underflows because refreshing of the counter is not possible due to the program having entered crashed execution or if a refresh error occurs due to refreshing outside the refresh permitted period the IWDT o...

Page 575: ... period Refresh prohibited period Refresh permitted period Status flag cleared Status flag cleared Counter value 100 75 50 25 0 RES pin Refresh the counter active high REFEF flag UNDFF flag Reset output from IWDT active high H L H L L Refresh error Refresh error Counting starts Counting starts Underflow Counting starts Counting starts Interrupt request WUNI active low ...

Page 576: ...s IWDTCR IWDTRCR and IWDTCSTPR against subsequent attempts at writing This protection is released by the reset source of the IWDT With other reset sources the protection is not released Figure 22 5 shows control waveforms produced in response to writing to the IWDTCR register Figure 22 5 Control Waveforms Produced in Response to Writing to the IWDTCR Register 3300h IWDTCR register is protected wri...

Page 577: ...value other than FFh FFh Even when 00h is written to the IWDTRR register outside the refresh permitted period if FFh is written to the IWDTRR register in the refresh permitted period the writing sequence is valid and refreshing will be done After FFh is written to the IWDTRR register refreshing the counter requires up to four cycles of the signal for counting the IWDTCR CKS 3 0 bits determine how ...

Page 578: ...DT Refresh Operation Waveforms IWDTCR CKS 3 0 0000b IWDTCR TOPS 1 0 11b Invalid Valid Refreshing Peripheral module clock PCLK IWDT dedicated clock IWDTCLK Data written to IWDTRR register IWDTRR register write signal internal signal IWDTRR register Refresh synchronization signal Refresh signal after synchronization with IWDTCLK Counter value n 2 n 1 n n 1 n 2 n 3 FFh FFh 00h 00h Refresh request 00h...

Page 579: ...cted 22 3 5 Reset Output When the IWDTRCR RSTIRQS bit is set to 1 in register start mode or when the IWDTRSTIRQS bit in option function select register 0 OFS0 is set to 1 in auto start mode a reset signal is output when an underflow in the counter or a refresh error occurs In register start mode the counter is initialized 0000h and kept in that state after assertion of the reset signal After the r...

Page 580: ...lue requires multiple PCLK clock cycles up to four clock cycles and the read counter value may differ from the actual counter value by a value of one count Figure 22 7 shows the processing for reading the IWDT counter value when PCLK IWDTCLK and clock divide ratio IWDTCLK Figure 22 7 Processing for Reading IWDT Counter Value IWDTCR CKS 3 0 0000b IWDTCR TOPS 1 0 11b Peripheral module clock PCLK IWD...

Page 581: ...set values which ensure that refreshing is possible 22 4 2 Clock Divide Ratio Setting Satisfy the frequency of the peripheral module clock PCLK 4 the frequency of the count source after divide Table 22 5 Correspondence between Option Function Select Register 0 OFS0 and IWDT Registers Target of Control Function OFS0 Register Enabled in Auto Start Mode OFS0 IWDTSTRT 0 IWDT Registers Enabled in Regis...

Page 582: ...k diagram of SCI12 SCIh Table 23 1 SCIg Specifications 1 2 Item Description Serial communication modes Asynchronous Clock synchronous Smart card interface Simple I2C bus Simple SPI bus Transfer speed Bit rate specifiable with the on chip baud rate generator Full duplex communications Transmitter Continuous transmission possible using double buffer structure Receiver Continuous reception possible u...

Page 583: ...stable Simple SPI bus Data length 8 bits Detection of errors Overrun error SS input pin function Applying the high level to the SSn pin can cause the output pins to enter the high impedance state Clock settings Four kinds of settings for clock phase and clock polarity are selectable Bit rate modulation function Correction of outputs from the on chip baud rate generator can reduce errors Table 23 2...

Page 584: ...ransfer rate Fast mode is supported refer to section 23 2 11 Bit Rate Register BRR to set the transfer rate Noise cancellation The signal paths from input on the SSCLn and SSDAn pins incorporate digital noise filters and the interval for noise cancellation is adjustable Simple SPI bus Data length 8 bits Detection of errors Overrun error SS input pin function Applying the high level to the SSn pin ...

Page 585: ...al bus Clock Module data bus RDRH RDR L TDRH TDR L Transmission and reception control SCMR Baud rate generator BRR MDDR SSR SCR SMR SEMR SPMR Parity addition Parity check TEI interrupt request TXI interrupt request RXI interrupt request ERI interrupt request SIMR1 SNFR SIMR2 SIMR3 SISR RSR TSR RDR Receive data register RDRH Receive data register H RDRL Receive data register L RSR Receive shift reg...

Page 586: ...ock Extended serial mode control section Controller Timer RXI interrupt request TXI interrupt request TEI interrupt request ERI interrupt request SCIX0 interrupt request SCIX1 interrupt request SCIX2 interrupt request SCIX3 interrupt request RXD12 SSCL12 SMISO12 RXDX12 TXD12 SSDA12 SMOSI12 TXDX12 SIOX12 RTS12 CTS12 SS12 SCK12 Internal peripheral bus MTIOC1A MTIOC2A MTU ...

Page 587: ...in Name I O Function SCI1 SSCL1 I O SCI1 I2C clock input output SSDA1 I O SCI1 I2C data input output SCI5 SSCL5 I O SCI5 I2C clock input output SSDA5 I O SCI5 I2C data input output SCI12 SSCL12 I O SCI12 I2C clock input output SSDA12 I O SCI12 I2C data input output Table 23 6 SCI Pin Configuration in Simple SPI Mode Channel Pin Name I O Function SCI1 SCK1 I O SCI1 clock input output SMISO1 I O SCI...

Page 588: ...gister RDR RDR is an 8 bit register that stores receive data When one frame of serial data has been received the received serial data is transferred from RSR to RDR Then the RSR register can receive the next data Since RSR and RDR function as a double buffer in this way continuous receive operations can be performed Read RDR only once after a receive data full interrupt RXI has occurred Note that ...

Page 589: ...ixed to 0 These bits are read as 0 The RDRHL register can be accessed in 16 bit units 23 2 4 Transmit Data Register TDR TDR is an 8 bit register that stores transmit data When the SCI detects that the TSR register is empty it transfers the transmit data written in the TDR register to the TSR register and starts transmission The double buffered structures of the TDR register and the TSR register en...

Page 590: ...transmitting operation is continued by transfer to the TSR register The CPU can read and write to the TDRH and TDRL registers Bits 0 to 7 in RDRH are fixed to 1 These bits are read as 1 The write value should be 1 Writing transmit data to the TDRH and TDRL registers should be performed only once in the order from TDRH to TDRL when a transmit data empty interrupt TXI request is issued The TDRHL reg...

Page 591: ...de Address es SCI1 SMR 0008 A020h SCI5 SMR 0008 A0A0h SCI12 SMR 0008 B300h b7 b6 b5 b4 b3 b2 b1 b0 CM CHR PE PM STOP MP CKS 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 CKS 1 0 Clock Select b1 b0 0 0 PCLK n 0 1 0 1 PCLK 4 n 1 1 1 0 PCLK 16 n 2 1 1 1 PCLK 64 n 3 1 R W 4 b2 MP Multi Processor Mode Valid only in asynchronous mode 0 Multi processor communications fun...

Page 592: ... Selects the parity mode even or odd for transmission and reception The setting of the PM bit is invalid in multi processor mode PE Bit Parity Enable When this bit is set to 1 the parity bit is added to transmit data and the parity bit is checked in reception Irrespective of the setting of the PE bit the parity bit is not added or checked in multi processor format CHR Bit Character Length Selects ...

Page 593: ... PE PM BCP 1 0 CKS 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 CKS 1 0 Clock Select b1 b0 0 0 PCLK n 0 1 0 1 PCLK 4 n 1 1 1 0 PCLK 16 n 2 1 1 1 PCLK 64 n 3 1 R W 2 b3 b2 BCP 1 0 Base Clock Pulse Selects the number of base clock cycles in combination with the SCMR BCP2 bit Table 23 8 lists the combinations of the SCMR BCP2 bit and SMR BCP 1 0 bits R W 2 b4 PM Par...

Page 594: ...d to transmit data before transmission and the parity bit is checked in reception BLK Bit Block Transfer Mode Setting this bit to 1 allows block transfer mode operation For details refer to section 23 6 3 Block Transfer Mode GM Bit GSM Mode Setting this bit to 1 allows GSM mode operation In GSM mode the SSR TEND flag set timing is put forward to 11 0 etu elementary time unit 1 bit transfer time fr...

Page 595: ...it rate should be input from the SCKn pin Input a clock signal with a frequency eight times the bit rate when the SEMR ABCS bit is 1 The SCKn pin becomes high impedance when the MTU clock is used Clock synchronous mode b1 b0 0 x Internal clock The SCKn pin functions as the clock output pin 1 x External clock The SCKn pin functions as the clock input pin R W 1 b2 TEIE Transmit End Interrupt Enable ...

Page 596: ...essor bit set to 1 is received the MPB bit is set to 1 the MPIE bit is automatically cleared to 0 the RXI and ERI interrupt requests are enabled if the SCR RIE bit is set to 1 and setting the flags ORER and FER to 1 is enabled Set the MPIE bit to 0 if multi processor communications function is not to be used RE Bit Receive Enable Enables or disables serial reception When this bit is set to 1 seria...

Page 597: ...SCR 0008 A0A2h SMCI12 SCR 0008 B302h b7 b6 b5 b4 b3 b2 b1 b0 TIE RIE TE RE MPIE TEIE CKE 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 CKE 1 0 Clock Enable When SMR GM 0 b1 b0 0 0 Output disabled The SCKn pin becomes high impedance 0 1 Clock output 1 x Setting prohibited When SMR GM 1 b1 b0 0 0 Output fixed low x 1 Clock output 1 0 Output fixed high R W 1 b2 TEIE ...

Page 598: ... Transmit Enable Enables or disables serial transmission When this bit is set to 1 serial transmission is started by writing transmit data to the TDR register Note that the SMR register should be set prior to setting the TE bit to 1 in order to designate the transmission format RIE Bit Receive Interrupt Enable Enables or disables RXI and ERI interrupt requests An RXI interrupt request is disabled ...

Page 599: ... When setting the TEND flag to 0 to complete the interrupt handling refer to section 14 4 1 2 Operation of Status Flags for Level Detected Interrupts Address es SCI1 SSR 0008 A024h SCI5 SSR 0008 A0A4h SCI12 SSR 0008 B304h b7 b6 b5 b4 b3 b2 b1 b0 TDRE RDRF ORER FER PER TEND MPB MPBT Value after reset 1 0 0 0 0 1 0 0 Bit Symbol Bit Name Description R W b0 MPBT Multi Processor Bit Transfer Sets the m...

Page 600: ...pt request occurs In addition when the FER flag is being set to 1 the subsequent receive data is not transferred to RDR Clearing condition When 0 is written to FER after reading FER 1 When setting the FER flag to 0 to complete the interrupt handling refer to section 14 4 1 2 Operation of Status Flags for Level Detected Interrupts Even when the SCR RE bit is set to 0 the FER flag is not affected an...

Page 601: ...13T Group 23 Serial Communications Interface SCIg SCIh TDRE Flag Transmit Data Empty Flag Indicates whether the TDR register has data to be transmitted Setting condition When data is transferred from TDR to TSR Clearing condition When data is written to TDR ...

Page 602: ...he start of transmission Clearing condition When transmit data are written to the TDR register while the SCR TE bit is 1 When setting the TEND flag to 0 to complete the interrupt handling refer to section 14 4 1 2 Operation of Status Flags for Level Detected Interrupts Address es SMCI1 SSR 0008 A024h SMCI5 SSR 0008 A0A4h SMCI12 SSR 0008 B304h b7 b6 b5 b4 b3 b2 b1 b0 TDRE RDRF ORER ERS PER TEND MPB...

Page 603: ...ation of Status Flags for Level Detected Interrupts Even when the SCR RE bit is set to 0 the ERS flag is not affected and retains its previous value ORER Flag Overrun Error Flag Indicates that an overrun error has occurred during reception and the reception ends abnormally Setting condition When the next data is received before receive data is read from RDR In RDR the receive data prior to an over...

Page 604: ...R 0008 B306h b7 b6 b5 b4 b3 b2 b1 b0 BCP2 CHR1 SDIR SINV SMIF Value after reset 1 1 1 1 0 0 1 0 Bit Symbol Bit Name Description R W b0 SMIF Smart Card Interface Mode Select 0 Non smart card interface mode Asynchronous mode clock synchronous mode simple SPI mode or simple I2C mode 1 Smart card interface mode R W 1 b1 Reserved This bit is read as 1 The write value should be 1 R W b2 SINV Transmitted...

Page 605: ...ts Note 1 S is the value of S in BRR refer to section 23 2 11 Bit Rate Register BRR Table 23 9 Combinations of the SCMR BCP2 Bit and SMR BCP 1 0 Bits SCMR BCP2 Bit SMR BCP 1 0 Bits Number of Base Clock Cycles for 1 Bit Transfer Period 0 0 0 93 clock cycles S 93 1 0 0 1 128 clock cycles S 128 1 0 1 0 186 clock cycles S 186 1 0 1 1 512 clock cycles S 512 1 1 0 0 32 clock cycles S 32 1 Initial Value ...

Page 606: ... 23 13 Note 1 Adjust the bit rate so that the widths at high and low level of the SCL output in simple I2C mode satisfy the I2C bus standard Address es SCI1 BRR 0008 A021h SCI5 BRR 0008 A0A1h SCI12 BRR 0008 B301h b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 1 1 1 1 1 1 1 1 Table 23 10 Relationship between N Setting in BRR Register and Bit Rate B Mode SEMR Settings BRR Setting Error BGDM bit ABCS bit ...

Page 607: ...fer to section 23 6 4 Receive Data Sampling Timing and Reception Margin Table 23 16 and Table 23 19 list the maximum bit rates with external clock input When either the SEMR ABCS or BGDM bit is set to 1 in asynchronous mode the bit rate becomes twice that listed in Table 23 14 When both of those bits are set to 1 the bit rate becomes four times the listed value Table 23 12 Clock Source Settings SM...

Page 608: ...11 0 00 0 11 2 40 38400 0 7 0 00 0 7 1 73 0 9 2 34 0 9 0 00 Bit Rate bps Operating Frequency PCLK MHz 14 16 17 2032 18 19 6608 n N Error n N Error n N Error n N Error n N Error 110 2 248 0 17 3 70 0 03 3 75 0 48 3 79 0 12 3 86 0 31 150 2 181 0 16 2 207 0 16 2 223 0 00 2 233 0 16 2 255 0 00 300 2 90 0 16 2 103 0 16 2 111 0 00 2 116 0 16 2 127 0 00 600 1 181 0 16 1 207 0 16 1 223 0 00 1 233 0 16 1 2...

Page 609: ... 1 0 0 2150400 9 8304 0 0 0 0 307200 18 0 0 0 0 562500 1 0 0 614400 1 0 0 1125000 1 0 0 0 1 0 0 0 1 0 0 1228800 1 0 0 2250000 10 0 0 0 0 312500 19 6608 0 0 0 0 614400 1 0 0 625000 1 0 0 1228800 1 0 0 0 1 0 0 0 1 0 0 1250000 1 0 0 2457600 12 0 0 0 0 375000 20 0 0 0 0 625000 1 0 0 750000 1 0 0 1250000 1 0 0 0 1 0 0 0 1 0 0 1500000 1 0 0 2500000 12 288 0 0 0 0 384000 25 0 0 0 0 781250 1 0 0 768000 1 ...

Page 610: ...500 16 4 0000 250000 500000 17 2032 4 3008 268800 537600 18 4 5000 281250 562500 19 6608 4 9152 307200 614400 20 5 0000 312500 625000 25 6 2500 390625 781250 30 7 5000 468750 937500 Table 23 17 Maximum Bit Rate with MTU Clock Input Asynchronous Mode PCLK MHz MTU Clock MHz Maximum Bit Rate bps SEMR ABCS Bit 0 SEMR ABCS Bit 1 8 4 250000 500000 9 8304 4 9152 307200 614400 10 5 312500 625000 12 6 3750...

Page 611: ...e is 8 9 times the bit rate Bit Rate bps Operating Frequency PCLK MHz 8 10 16 20 25 30 n N n N n N n N n N n N 110 250 3 124 3 155 3 249 500 2 249 3 77 3 124 3 155 3 194 3 233 1 k 2 124 2 155 2 249 3 77 3 97 3 116 2 5 k 1 199 1 249 2 99 2 124 2 155 2 187 5 k 1 99 1 124 1 199 1 249 2 77 2 93 10 k 0 199 0 249 1 99 1 124 1 155 1 187 25 k 0 79 0 99 0 159 0 199 0 249 1 74 50 k 0 39 0 49 0 79 0 99 0 124...

Page 612: ... 9600 7 1424 0 0 0 00 10 00 0 1 30 00 10 7136 0 1 25 00 13 00 0 1 8 99 14 2848 0 1 0 00 16 00 0 1 12 01 18 00 0 2 15 99 20 00 0 2 6 66 25 00 0 3 12 49 30 00 0 3 5 01 Table 23 21 Maximum Bit Rate for Each Operating Frequency Smart Card Interface Mode S 32 PCLK MHz Maximum Bit Rate bps n N 10 00 156250 0 0 10 7136 167400 0 0 13 00 203125 0 0 16 00 250000 0 0 18 00 281250 0 0 20 00 312500 0 0 25 00 3...

Page 613: ...it Rates Simple I2C Mode Bit Rate bps Operating Frequency PCLK MHz 8 10 16 20 n N Min Widths at High Low Level for SCL μs n N Min Widths at High Low Level for SCL μs n N Min Widths at High Low Level for SCL μs n N Min Widths at High Low Level for SCL μs 10 k 0 24 43 75 50 00 0 31 44 80 51 20 1 12 45 50 52 00 1 15 44 80 51 20 25 k 0 9 17 50 20 00 0 12 18 20 20 80 1 4 17 50 20 00 1 6 19 60 22 40 50 ...

Page 614: ...13 section 23 2 11 Bit Rate Register BRR Note 1 Do not use this function in clock synchronous mode and in the highest speed settings in simple SPI mode SMR CKS 1 0 00b SCR CKE 1 0 and BRR 0 Note 2 Adjust the bit rate so that the widths at high and low level of the SCL output in simple I2C mode satisfy the I2C bus standard Address es SCI1 MDDR 0008 A032h SCI5 MDDR 0008 A0B2h SCI12 MDDR 0008 B312h b...

Page 615: ...function is disabled 1 Bit rate modulation function is enabled R W 1 b3 Reserved This bit is read as 0 The write value should be 0 R W b4 ABCS Asynchronous Mode Base Clock Select Valid only in asynchronous mode 0 Selects 16 base clock cycles for 1 bit period 1 Selects 8 base clock cycles for 1 bit period R W 1 b5 NFEN Digital Noise Filter Function Enable In asynchronous mode 0 Noise cancellation f...

Page 616: ...3 4 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 4 1 bit Base clock 16 Average transfer rate 3 MHz 16 187 5 kbps 4 MHz 3 MHz SCKn base clock 4 MHz 3 4 3 MHz average Clock source MTIOC1A output 4 MHz Clock enable MTIOC2A output This figure shows an example when MTU clock is input to SCIn n 1 5 12 When generating 187 5 kbps of MTU average transfer rate for PCLK 32 MHz 1 G...

Page 617: ... Mode Select Selects the cycle of output clock for the baud rate generator This bit is valid when the on chip baud rate generator is selected as the clock source SCR CKE 1 0 in asynchronous mode SMR CM 0 For the clock output from the baud rate generator either normal or doubled frequency can be selected The base clock is generated by the clock output from the baud rate generator When the BGDM bit ...

Page 618: ... b3 b2 b1 b0 NFCS 2 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b2 to b0 NFCS 2 0 Noise Filter Clock Select In asynchronous mode the standard setting for the base clock is as follows b2 b0 0 0 0 The clock signal divided by 1 is used with the noise filter In simple I2C mode the standard settings for the clock source of the on chip baud rate generator selected by the SMR ...

Page 619: ... in the SMR CKS 1 0 bits is supplied as the clock signal from the on chip baud rate generator Set these bits to 00000b unless operation is in simple I2C mode In simple I2C mode set the bits to a value in the range from 00001b to 11111b Address es SCI1 SIMR1 0008 A029h SCI5 SIMR1 0008 A0A9h SCI12 SIMR1 0008 B309h b7 b6 b5 b4 b3 b2 b1 b0 IICDL 4 0 IICM Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bi...

Page 620: ...SCLn clock signal is generated in accord with the rate selected in the BRR regardless of the level being input on the SSCLn pin Set the IICCSC bit to 1 except during debugging IICACKT Bit ACK Transmission Data Transmitted data contains ACK bits Set this bit to 1 when ACK and NACK bits are received Address es SCI1 SIMR2 0008 A02Ah SCI5 SIMR2 0008 A0AAh SCI12 SIMR2 0008 B30Ah b7 b6 b5 b4 b3 b2 b1 b0...

Page 621: ... Completion of generation of the start condition Address es SCI1 SIMR3 0008 A02Bh SCI5 SIMR3 0008 A0ABh SCI12 SIMR3 0008 B30Bh b7 b6 b5 b4 b3 b2 b1 b0 IICSCLS 1 0 IICSDAS 1 0 IICSTIF IICSTP REQ IICRST AREQ IICSTA REQ Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 IICSTAREQ Start Condition Generation 0 A start condition is not generated 1 A start condition is generated 1 3...

Page 622: ...neration is completed When using the IICSTAREQ IICRSTAREQ or IICSTPREQ bit to cause generation of a condition do so after setting the IICSTIF flag to 0 When the IICSTIF flag is 1 while an interrupt request is enabled by setting the SCR TEIE bit an STI request is output Setting condition Completion of the generation of a start restart or stop condition however in cases where this conflicts with any...

Page 623: ...of SSCLn clock for the ACK NACK receiving bit Address es SCI1 SISR 0008 A02Ch SCI5 SISR 0008 A0ACh SCI12 SISR 0008 B30Ch b7 b6 b5 b4 b3 b2 b1 b0 IICACK R Value after reset 0 0 x x 0 x 0 0 x Undefined Bit Symbol Bit Name Description R W b0 IICACKR ACK Reception Data Flag 0 ACK received 1 NACK received R W 1 b1 Reserved This bit is read as 0 The write value should be 0 R W b2 Reserved The read value...

Page 624: ...ce mode simple SPI mode and simple I2C mode Do not set both the CTSE and SSE bits to enabled even if this setting is made operation is the same as that when these bits are set to 0 MSS Bit Master Slave Select This bit selects between master and slave operation in simple SPI mode When the MSS bit is set to 1 data is received through the SMOSIn pin and transmitted through the SMISOn pin Set this bit...

Page 625: ...in Refer to Figure 23 57 for details Set the bit to 0 in other than simple SPI mode and clock synchronous mode 23 2 20 Extended Serial Module Enable Register ESMER ESME Bit Extended Serial Mode Enable When the ESME bit is 1 the facilities of the extended serial mode control section are enabled When the ESME bit is 0 the extended serial mode control section is initialized Note 1 Operation is only p...

Page 626: ...b2 b1 b0 PIBS 2 0 PIBE CF1DS 1 0 CF0RE BFE Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 BFE Break Field Enable 0 Break Field detection is disabled 1 Break Field detection is enabled R W b1 CF0RE Control Field 0 Reception Enable 0 Reception of Control Field 0 is disabled 1 Reception of Control Field 0 is enabled R W b3 b2 CF1DS 1 0 Control Field 1 Data Register Select b3...

Page 627: ...0 Base clock frequency divided by 4 1 1 Setting prohibited When SEMR BGDM 1 and SMR CKS 1 0 00b b5 b4 0 0 Base clock frequency divided by 2 0 1 Base clock frequency divided by 4 1 0 Setting prohibited 1 1 Setting prohibited R W b7 b6 RTS 1 0 RXDX12 Reception Sampling Timing Select When SCI12 SEMR ABCS 0 b7 b6 0 0 Rising edge of the 8th cycle of base clock 0 1 Rising edge of the 10th cycle of base ...

Page 628: ...d 1 Detection of Start Frame is performed R W b7 to b1 Reserved These bits are read as 0 The write value should be 0 R W Address es SCI12 PCR 0008 B325h b7 b6 b5 b4 b3 b2 b1 b0 SHARP S RXDXP S TXDXP S Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 TXDXPS TXDX12 Signal Polarity Select 0 The polarity of TXDX12 signal is not inverted for output 1 The polarity of TXDX12 signa...

Page 629: ...ts on detection of a match with Control Field 0 are enabled R W b2 CF1MIE Control Field 1 Match Detected Interrupt Enable 0 Interrupts on detection of a match with Control Field 1 are disabled 1 Interrupts on detection of a match with Control Field 1 are enabled R W b3 PIBDIE Priority Interrupt Bit Detected Interrupt Enable 0 Interrupts on detection of the priority interrupt bit are disabled 1 Int...

Page 630: ...between the value received in Control Field 0 and the set value Clearing condition Writing 1 to the CF0MCL bit in STCR R b2 CF1MF Control Field 1 Match Flag Setting condition A match between the data received in Control Field 1 and the set values Clearing condition Writing 1 to the CF1MCL bit in STCR R b3 PIBDF Priority Interrupt Bit Detection Flag Setting condition Detection of the priority inter...

Page 631: ...g this bit to 1 clears the STR BFDF flag This bit is read as 0 R W b1 CF0MCL CF0MF Clear Setting this bit to 1 clears the STR CF0MF flag This bit is read as 0 R W b2 CF1MCL CF1MF Clear Setting this bit to 1 clears the STR CF1MF flag This bit is read as 0 R W b3 PIBDCL PIBDF Clear Setting this bit to 1 clears the STR PIBDF flag This bit is read as 0 R W b4 BCDCL BCDF Clear Setting this bit to 1 cle...

Page 632: ...d 0 is enabled R W b2 CF0CE2 Control Field 0 Bit 2 Compare Enable 0 Comparison with bit 2 of Control Field 0 is disabled 1 Comparison with bit 2 of Control Field 0 is enabled R W b3 CF0CE3 Control Field 0 Bit 3 Compare Enable 0 Comparison with bit 3 of Control Field 0 is disabled 1 Comparison with bit 3 of Control Field 0 is enabled R W b4 CF0CE4 Control Field 0 Bit 4 Compare Enable 0 Comparison w...

Page 633: ... 0 Comparison with bit 1 of Control Field 1 is disabled 1 Comparison with bit 1 of Control Field 1 is enabled R W b2 CF1CE2 Control Field 1 Bit 2 Compare Enable 0 Comparison with bit 2 of Control Field 1 is disabled 1 Comparison with bit 2 of Control Field 1 is enabled R W b3 CF1CE3 Control Field 1 Bit 3 Compare Enable 0 Comparison with bit 3 of Control Field 1 is disabled 1 Comparison with bit 3 ...

Page 634: ...mer counting R W b7 to b1 Reserved These bits are read as 0 The write value should be 0 R W Address es SCI12 TMR 0008 B331h b7 b6 b5 b4 b3 b2 b1 b0 TCSS 2 0 TWRC TOMS 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 TOMS 1 0 Timer Operating Mode Select 1 b1 b0 0 0 Timer mode 0 1 Break Field low width determination mode 1 0 Break Field low width output mode 1 1 Settin...

Page 635: ...d to the read buffer is returned in reading It takes one PCLK cycle to load a value from the reload register to the counter 23 2 39 Timer Count Register TCNT TCNT consists of an 8 bit reload register a read buffer and a counter each of which has FFh as its initial value This down counter counts underflows of the TPRE register until the TCNT register underflows and is then reloaded with the value f...

Page 636: ...ll duplex communications Both the transmitter and the receiver also have a double buffered structure so that data can be read or written during transmission or reception enabling continuous data transmission and reception Figure 23 4 Data Format in Asynchronous Serial Communications Example with 8 Bit Data Parity 2 Stop Bits 23 3 1 Serial Data Transfer Format Table 23 27 lists the serial data tran...

Page 637: ...bit data STOP 0 0 0 0 1 S 9 bit data STOP STOP 0 0 1 0 0 S 9 bit data P STOP 0 0 1 0 1 S 9 bit data P STOP STOP 1 0 0 0 0 S 8 bit data STOP 1 0 0 0 1 S 8 bit data STOP STOP 1 0 1 0 0 S 8 bit data P STOP 1 0 1 0 1 S 8 bit data P STOP STOP 1 1 0 0 0 S 7 bit data STOP 1 1 0 0 1 S 7 bit data STOP STOP 1 1 1 0 0 S 7 bit data P STOP 1 1 1 0 1 S 7 bit data P STOP STOP 0 0 1 0 S 9 bit data MPB STOP 0 0 1 ...

Page 638: ...tio of bit rate to clock N 16 when SEMR ABCS 0 N 8 when SEMR ABCS 1 D Duty cycle of clock D 0 5 to 1 0 L Frame length L 9 to 13 F Absolute value of clock frequency deviation Assuming values of F 0 and D 0 5 in formula 1 the reception margin is determined by the formula below M 0 5 1 2 16 100 46 875 However this is only the computed value and a margin of 20 to 30 should be allowed in system design ...

Page 639: ...ising edge of the clock is in the middle of the transmit data as shown in Figure 23 6 Figure 23 6 Phase Relationship between Output Clock and Transmit Data Asynchronous Mode SMR CHR 0 PE 1 MP 0 STOP 1 23 3 4 Double Speed Mode The output clock frequency of the on chip baud rate generator is doubled by setting the SEMR BGDM bit to 1 enabling high speed communication at a doubled bit rate If the SEMR...

Page 640: ...n is in progress does not affect transmission of the current frame which continues In the RTS function by using the function of output on the RTSn pin a low level is output when reception becomes possible Conditions for output of the low and high level are shown below Conditions for low level output When the following conditions are all satisfied The SCR RE bit is 1 Reception is not in progress Th...

Page 641: ...7 Sample SCI Initialization Flowchart Asynchronous Mode Initialization completed Start initialization 1 Set the SCR TIE RIE TE RE and TEIE bits to 0 1 Make I O port settings to enable input and output functions as required for TXDn RXDn and SCKn pins 2 Set the clock selection in SCR When the clock output is selected in asynchronous mode the clock is output immediately after SCR settings are made 3...

Page 642: ...et to the TXD pin it is still high impedance because the SCR TE bit is 0 When the transmit data is written after setting the TE bit to 1 a data transmission starts After the TE bit is set to 1 one frame of high is output from TXD pin internal wait time and then the data transmission starts Figure 23 8 Example of Data Transmission Timing in Asynchronous Mode Asynchronous mode Mode SCR TE bit TXD pi...

Page 643: ... bit to 1 a TEI interrupt request is enabled after the last of the data to be transmitted are written to the TDR register 1 2 from the handling routine for TXI requests 3 Data is sent from the TXDn pin in the following order start bit transmit data parity bit or multi processor bit may be omitted depending on the format and stop bit 4 The SCI checks for updating of writing to the TDR register 3 at...

Page 644: ...XI interrupt handling routine SSR TEND flag 0 D0 D1 D7 0 1 D7 0 1 1 0 D0 1 D1 Data written to TDR in TXI interrupt handling routine SCR TE bit 0 Data written to TDR in TXI interrupt handling routine Note 1 Refer to section 14 Interrupt Controller ICUb for details on the corresponding interrupt vector number TXI interrupt flag IRn in ICU 1 1 frame Data Parity bit Stop bit Start bit Idle state mark ...

Page 645: ...1 1 frame Data Parity bit Stop bit Start bit Idle state mark state TEI interrupt request generated TXI interrupt request generated TXI interrupt request generated Data written to TDR in TXI interrupt handling routine SSR TEND flag TIE 1 TIE 0 0 D0 D7 0 1 1 0 D0 D1 D7 0 1 D7 0 1 1 0 D0 1 D1 D1 Data written to TDR in TXI interrupt handling routine Set the TIE bit to 0 and the TEIE bit to 1 after wri...

Page 646: ... frame and transmission is enabled 2 Transmit data write to TDR by a TXI interrupt request When transmit data is transferred from TDR to TSR a transmit data empty interrupt TXI request is generated Write transmit data to TDR once in the TXI interrupt handling routine 3 Serial transmission continuation procedure To continue serial transmission write transmit data to TDR once using a TXI interrupt r...

Page 647: ...is 1 at this time an ERI interrupt request is generated 6 When reception finishes successfully receive data is transferred to the RDR register 1 If the SCR RIE bit is 1 at this time an RXI interrupt request is generated Continuous reception is enabled by reading the receive data transferred to the RDR register 1 in this RXI interrupt handling routine before reception of the next receive data is co...

Page 648: ...eft in RDR or the RDRL Figure 23 15 and Figure 23 16 show samples of flowcharts for serial data reception Note 1 Read data not in RDR but in the RDRH and RDRL registers when 9 bit data length is selected Table 23 28 Flags in the SSR Status Register and Receive Data Handling Flags in the SSR Status Register Receive Data Receive Error Type ORER FER PER 1 0 0 Lost Overrun error 0 1 0 Transferred to R...

Page 649: ...L 1 SCI initialization Set data reception 2 3 Receive error processing and break detection If a receive error occurs an ERI interrupt is generated An error is identified by reading the ORER PER and FER flags in SSR After performing the appropriate error processing be sure to set the ORER PER and FER flags to 0 Reception cannot be resumed if any of these flags is set to 1 In the case of a framing e...

Page 650: ...essing SSR ORER flag 1 SSR FER flag 1 Break SSR PER flag 1 Set RE bit in SCR to 0 3 7 7 Clearing the error flag Write 0 to the error flag 6 6 Processing in response to an overrun error Read the RDR In combination with step 7 this will make correct reception of the next frame possible Read the SSR ORER PER and FER flags 8 8 Confirming that the error flag is cleared Read the error flag to confirm th...

Page 651: ...unication data that is subsequently transmitted If the received ID does not match with the ID of the receiving station the receiving station skips the communication data until again receiving the communication data in which the multi processor bit is set to 1 For supporting this function the SCI provides the SCR MPIE bit When the MPIE bit is set to 1 transfer of receive data from the RSR register ...

Page 652: ... registers when 9 bit data length is selected Write data in the order from TDRH to TDRL 1 SCI initialization Set data transmission After the TE bit in SCR is set to 1 high is output for a frame and transmission is enabled 2 TXI interrupt request When transmit data is transferred from TDR to TSR a transmit data empty interrupt TXI request is generated Set the MPBT bit in SSR to 0 or 1 and write tra...

Page 653: ...a1 MPB RXI interrupt request multi processor interrupt generated ID1 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 ID2 Data2 ID1 Stop bit Idle state mark state Data ID1 Start bit Stop bit Start bit RDR value MPIE 0 MPIE RXI interrupt flag IRn In ICU 1 RDR value MPIE 0 MPIE bit set to 1 again when the received ID does not match the ID of the receiving station itself RXI interrupt request not generated RDR retains ...

Page 654: ...ison of ID Read data in RDR at the first RXI interrupt and compare it with the ID of the receiving station itself If the ID does not match the ID of the receiving station itself set the MPIE bit to 1 again and wait for another RXI interrupt request 4 Data reception at an RXI interrupt Read data in RDR once in the RXI interrupt routine 5 Receive error processing and break detection If a receive err...

Page 655: ...in SCR to 0 5 Set the SSR ORER PER and FER flags to 0 7 7 Clearing the error flag Write 0 to the error flag 6 6 Processing in response to an overrun error Read the RDR In combination with step 7 this will make correct reception of the next frame possible Read the SSR ORER PER and FER flags 8 8 Confirming that the error flag is cleared Read the error flag to confirm that its value is 0 Note The RDR...

Page 656: ...or an external synchronization clock input at the SCKn pin can be selected according to the setting of the SCR CKE 1 0 bits When the SCI is operated on an internal clock the synchronization clock is output from the SCKn pin Eight synchronization clock pulses are output in the transfer of one character and when no transfer is performed the clock is held high However when only data reception is perf...

Page 657: ...t reception transmission of the current frame which continues In the RTS function RTSn pin output is used to request reception transmission start when the clock source is an external synchronizing clock A low level is output when serial communications become possible Conditions for output of the low and high level are shown below Conditions for low level output When the following conditions are al...

Page 658: ...t functions as required for TXDn RXDn and SCKn pins 2 Set the clock selection in SCR When an internal clock is selected the SCK pin functions as the clock output pin 3 Set the SIMR1 IICM bit to 0 Set the SPMR CKPH and CKPOL bits to 0 Step 3 can be skipped if the values have not been changed from the initial values 4 Set the data transmission reception format in SMR SCMR and SEMR 5 Write a value co...

Page 659: ...and the SCR TEIE bit to 1 a TEI interrupt request is enabled after the last of the data to be transmitted are written to the TDR register from the handling routine for TXI requests 3 8 bit data is sent from the TXDn pin in synchronization with the output clock when clock output mode has been specified and in synchronization with the input clock when use of an external clock has been specified Outp...

Page 660: ... TDR in TXI interrupt handling routine Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 1 frame Bit 0 TXI interrupt request generated Data written to TDR in TXI interrupt handling routine TXI interrupt request generated Note 1 Refer to section 14 Interrupt Controller ICUb for details on the corresponding interrupt vector number Synchronization clock 1 frame Serial data TXI interrupt request generated TXI inter...

Page 661: ...I interrupt request generated TEI interrupt request generated TXI interrupt request generated TXI interrupt flag IRn in ICU 1 Data written to TDR in TXI interrupt handling routine SSR TEND flag TIE 1 TIE 0 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Data written to TDR in TXI interrupt handling routine Set the TIE bit to 0 and the TEIE bit to 1 after writing the last data Note 1 Refer to...

Page 662: ...nterrupt TXI request is generated Transmit data is written to TDR once from the handling routine for TXI requests 3 Serial transmission continuation procedure To continue serial transmission write transmit data to TDR upon accepting a transmit data empty interrupt TXI request Transmit data can also be written to TDR by activating the DTC by the TXI interrupt request When TEI interrupt requests are...

Page 663: ...erred to the RDR register 4 When reception finishes successfully receive data is transferred to the RDR register If the RIE bit in the SCR register is 1 at this time an RXI interrupt request is generated Continuous reception is enabled by reading the receive data transferred to the RDR register in this RXI interrupt handling routine before reception of the next receive data is completed Reading ou...

Page 664: ...r during overrun error processing When a reception is forcibly terminated by setting the SCR RE bit to 0 during operation read the RDR register because received data which has not yet been read may be left in the RDR register 1 frame RXI interrupt flag IRn in ICU 1 SSR ORER flag Bit 7 Bit 0 Bit 7 Bit 0 RDR data read in RXI interrupt handling routine RXI interrupt request generated RXI interrupt re...

Page 665: ...error processing If a receive error occurs read the ORER flag in the SSR register perform the relevant error processing and then set the ORER flag to 0 Data reception cannot be resumed while the ORER flag is 1 4 Read the receive data in the RDR register once in the receive data full interrupt RXI request handling routine 5 Serial reception continuation procedure To continue serial reception before...

Page 666: ...ceived No Yes TXI interrupt Write transmit data to TDR No Yes RXI interrupt Read ORER flag in SSR Clear TIE RIE TE RE and TEIE bits in SCR to 0 1 2 3 4 5 1 SCI initialization The TXDn pin can act as the output pin for transmitted data and the RXDn pin can act as the input pin for received data at the same time 2 Transmit data write Write transmit data to TDR once in the TXI interrupt handling rout...

Page 667: ...gure since this MCU communicates with an IC card using a single transmission line interconnect the TXDn and RXDn pins and pull up the data transmission line to VCC using a resistor Setting the TE and RE bits in the SCR register to 1 with an IC card disconnected enables closed transmission reception allowing self diagnosis To supply an IC card with the clock pulses generated by the SCI input the SC...

Page 668: ... parity bit until the start of the next frame If a parity error is detected during reception a low level error signal is output for 1 etu after 10 5 etu has passed from the start bit If an error signal is sampled during transmission the same data is automatically retransmitted after at least 2 etu Figure 23 33 Data Formats in Smart Card Interface Mode Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp In normal transm...

Page 669: ...e SDIR and SINV bits in the SCMR register The parity bit is logic level 0 to produce even parity which is prescribed by the smart card standard and corresponds to state Z Since the SINV bit of the this MCU only inverts data bits D7 to D0 write 1 to the PM bit in the SMR register to invert the parity bit for both transmission and reception Figure 23 35 Inverse Convention SDIR in SCMR 1 SINV in SCMR...

Page 670: ...6th 32nd 186th 128th 46th 64th 93rd and 256th rising edges of the base clock so that it can be latched at the middle of each bit as shown in Figure 23 36 The reception margin here is determined by the following formula M Reception margin N Ratio of bit rate to clock N 32 64 372 256 D Duty cycle of clock D 0 to 1 0 L Frame length L 10 F Absolute value of clock frequency deviation Assuming values of...

Page 671: ...flags to 0 Set the SPMR register to 00h Set the SMR GM BLK PM BCP 1 0 and CKS 1 0 bits and set the SMR PE bit to 1 Set the SCMR BCP2 SDIR and SINV bits Set the SEMR register to 00h Set the BRR register Set the pin functions set the MPC and I O port Set the SCR CKE 1 0 bits Set the SCR TE RE TIE and RIE bits End 1 2 3 4 5 6 7 8 9 10 11 1 Set the SCR register to 00h to stop transmission and receptio...

Page 672: ...tput from the SCK pin When the transmit data is written after setting the TE bit to 1 a data transmission starts After the TE bit is set to 1 one frame of high impedance is output from TXD pin internal wait time and then the data transmission starts In smart card interface mode the clock is continuously output while the CKE 0 bit is set to 1 clock output even if both the TE and RE bits are set to ...

Page 673: ...is time an ERI interrupt request is generated Clear the ERS flag to 0 before the next parity bit is sampled 2 For a frame in which an error signal is received the TEND flag in the SSR register is not set Data is retransferred from the TDR register to the TSR register allowing automatic data retransmission 3 If no error signal is returned from the receiver the ERS flag is not set to 1 4 In this cas...

Page 674: ...fer of transmit data The TEND flag is automatically set to 0 when the DTC transfers the data If an error occurs the SCI automatically retransmits the same data During this retransmission the TEND flag is kept to 0 and the DTC is not activated Therefore the SCI and DTC automatically transmit the specified number of bytes including retransmission in the case of error occurrence However since the ERS...

Page 675: ...er Controller DTCb Note that the SSR TEND flag is set in different timings depending on the GM bit setting in the SMR register Figure 23 41 shows the TEND flag generation timing Figure 23 41 SSR TEND Flag Generation Timing during Transmission Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I O data 12 5 etu 11 5 etu in block transfer mode SSR TEND flag TXI interrupt 11 0 etu DE Guard time When GM bit in SMR 0 Ds St...

Page 676: ...R flag in the SSR register is set to 1 When the RIE bit in the SCR register is 1 at this time an ERI interrupt request is generated Clear the PER flag to 0 before the next parity bit is sampled 2 For a frame in which a parity error is detected no RXI interrupt is generated 3 When no parity error is detected the PER flag in the SSR register is not set to 1 4 In this case data is determined to have ...

Page 677: ...r is set to 1 a receive error interrupt ERI request is generated Clear the error flag after the error occurrence If an error occurs the DTC is not activated and receive data is skipped Therefore the number of bytes of receive data specified in the DTC is transferred Even if a parity error occurs and the PER flag is set to 1 during reception receive data is transferred to RDR thus allowing the data...

Page 678: ...to section 23 2 11 Bit Rate Register BRR When the CKE 1 0 bits are set to 00b output fixed low or 10b output fixed to high the SCK pin can be fixed to low or high Figure 23 44 shows a timing chart when the clock output is controlled If changing the CKE 1 0 bits while the SMR GM bit is 0 non GSM mode a pulse of unexpected width may output from SCK pin because the result is immediately reflected to ...

Page 679: ...nsfer from the master device to the slave device A A Indicates an acknowledge bit This is returned by the slave device for master transmission and by the master device for master reception Return of the low level indicates ACK and return of the high level indicates NACK Sr Indicates a restart condition i e the master device changing the level on the SSDAn line from the high to the low level while ...

Page 680: ... high level Once the high level on the SSCLn line is detected the setup time for the restart condition is secured as half of a bit period at the bit rate determined by the setting of the BRR The level on the SSDAn line falls from the high level to the low level The hold time for the restart condition is secured as half of a bit period at the bit rate determined by the setting of the BRR The level ...

Page 681: ...tart restart and stop conditions Figure 23 47 Timing of Operations in the Generation of Start Restart and Stop Conditions SSDAn SSCLn SIMR3 IICSTAREQ SIMR3 IICRSTAREQ SIMR3 IICSTPREQ Start condition generated interrupt request Restart condition generated interrupt request Stop condition generated interrupt request SIMR3 IICSDAS 1 0 SIMR3 IICSCLS 1 0 11b 01b 00b 01b 00b 01b 11b ...

Page 682: ...acing the low level on the SSCLn line If the IICCSC bit in the SIMR2 register is 1 synchronization is obtained for the transmission and reception of data by taking the logical AND of the input on the SSCLn pin and the internal SSCLn clock If the IICCSC bit in the SIMR2 register is 0 synchronization with the internal SSCLn clock is obtained for the transmission and reception of data If a slave devi...

Page 683: ... transmit data and an acknowledge bit If the SSDA output delay is shorter than the time for the level on the SSCLn pin to fall the change of the output on the SSDAn pin will start while the output level on the SSCLn pin is falling creating a possibility of erroneous operation for slave devices Ensure that settings for the delay of output on the SSDAn pin are for times greater than the time output ...

Page 684: ...use on N channel open drain output pins of the SSCLn and SSDAn pin functions 2 Place the SSCLn and SSDAn pins in the high impedance state until a start condition is to be generated 3 Set the format for transmission and reception in SMR and SCMR In SMR set the CKS 1 0 bits to the desired value and set the other bits to 0 In SCMR set the SDIR bit to 1 and the SINV and SMIF bits to 0 4 Write the valu...

Page 685: ... performed by the NACK interrupt as the trigger Figure 23 52 Example 2 of Operations for Master Transmission in Simple I2C bus Mode with 7 Bit Slave Addresses ACK Interrupts and NACK Interrupts in Use TXI interrupt flag IRn in the ICU 1 SSDAn SSCLn Generation of STI interrupt STI interrupt flag IRn in the ICU 1 Acceptance of request Generation of TXI interrupt request Acceptance of TXI interrupt r...

Page 686: ...S 1 0 bits to 11b TXI interrupt 5 4 If 10 bit slave addresses are in use processing of 3 and 4 is repeated twice 6 1 Initialization for simple I2C mode For transmission set the SCR RIE bit to 0 RXI and ERI interrupts requests are disabled 2 Generate a start condition 3 Writing to TDR Writing the slave address and value for the R W bit to TDR 4 Confirming ACK response from the slave address Check t...

Page 687: ...on Figure 23 54 Example of Operations for Master Reception in Simple I2C bus Mode with 7 Bit Slave Addresses Transmission Interrupts and Reception Interrupts in Use TXI interrupt flag IRn in the ICU 1 SSDAn SSCLn Generation of STI interrupt request STI interrupt flag IRn in the ICU 1 Acceptance of STI interrupt request Generation of TXI interrupt request Acceptance of TXI interrupt request Generat...

Page 688: ...es Set SIMR2 IICACKT to 1 Write FFh as dummy data to TDR No RXI interrupt Read received data from RDR Yes No TXI interrupt Yes 6 1 Initialization for simple I2C mode Set the RIE bit in SCR to 0 2 Generate a start condition 3 Writing to TDR Writing the slave address and value for the R W bit to TDR 4 Confirming ACK response from the slave address Check the SISR IICACKR bit If its value is 0 it is i...

Page 689: ...y an abnormal state in SCI because of the communication error reset the SCI according to the following steps and release the bus 1 Set the SCR TE and RE bit to 0 at the same time to reset SCI 2 Set the SIMR3 register to F0h to release the bus 3 If the SSR RDRF flag is 1 dummy read the RDR register to clear the flag 4 Set the SCR TE and RE bit to 1 at the same time ...

Page 690: ...ck pulses in the same way as in clock synchronous mode One character of data for transfer consists of 8 bits of data and parity bits cannot be appended to this The data can be inverted by setting the SCMR SINV bit to 1 Since the receiver and transmitter are independent of each other within the SCI module full duplex communications are possible with a common clock signal Furthermore since both the ...

Page 691: ...rting transmission or reception will not be possible Furthermore the value of the SPMR MFF bit will be 1 indicating a mode fault error In a multi master configuration start error processing by reading SPMR MFF flag Also even if a mode fault error occurs while transmission or reception is in progress transmission or reception will not be stopped but the SMOSIn and SCKn pin output will be placed in ...

Page 692: ...a is shown in Figure 23 57 The relation is the same for both master and slave operation Figure 23 57 Relation between Clock Signal and Transmit Receive Data in Simple SPI Mode SMISOn pin SCKn pin CKPOL 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSn pin slave SCKn pin CKPOL 0 1 When CKPH 0 SMOSIn pin SCKn pin CKPOL 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSn pin slave SCKn pin CKPO...

Page 693: ...ks set in the MDDR register out of the total 256 clocks input Figure 23 58 assumes the SCI is in asynchronous mode bits SMR CKS 1 0 are 00b the BRR register is 00h and the MDDR register is 160 In this example the cycle of the base clock is evenly corrected to 256 160 and the bit rate is corrected to 160 256 Note that there is an imbalance in thinning out the internal clock and expansion and contra...

Page 694: ...Break Field Control Field 0 and Control Field 1 An Information Frame is composed of a number of Data Fields a CRC16 Upper Field and a CRC16 Lower Field Figure 23 59 Protocol for Serial Transfer by the Extended Serial Mode Control Section Start Frame Information Frame Break Field Break Field low width Break Field high width Inter Field Space Inter Field Space Control Field 0 Control Field 1 Data Fi...

Page 695: ... TPRE settings 2 The output on the TXDX12 pin is inverted when the timer counter underflows and the STR BFDF flag is set to 1 An SCIX0 interrupt is also generated if the value of the ICR BFDIE bit is 1 3 Write 0 to the TCR TCST bit to stop counting by the timer and send the data for Control Field 0 After the Break Field low width output stop counting before the next underflow occurs 4 When the dat...

Page 696: ...ng for RXDX12 reception clock for bus collision detection and sampling clock for the RXDX12 signal s digital filter Set the RXDX12 and TXDX12 pins Set Break Field low width output mode as the operating mode of the timer Set the clock source for counting and registers TCNT and TPRE to values that suit the period for the Break Field low width Initialize SCI12 refer to the example of a flowchart of S...

Page 697: ...ld low width The STR BFDF flag is set to 1 on output of the Break Field low width At this time if the ICR BFDIE bit is 1 an SCIX0 interrupt is generated Clear the BFDF flag After output of the Break Field low width is completed stop the timer counting before the next underflow of the timer occurs After setting the SCR TE bit to 0 set it to 1 The transmit data empty interrupt TXI request is generat...

Page 698: ... BFDIE bit is 1 3 When the input from the RXDX12 pin goes high after the Break Field low width the CR0 RXDSF flag becomes 0 and reception of Control Field 0 starts 4 If the data received in Control Field 0 match the data set in the CF0DR register the STR CF0MF flag is set to 1 An SCIX1 interrupt is also generated if the value of the ICR CF0MIE bit is 1 Reception of Control Field 1 starts after tha...

Page 699: ...Control Field 0 8 bits Control Field 1 8 bits Break Field low width Start Frame Information Frame Data Field Write 1 to CR3 SDST Specified period for TCNT and TPRE Write 1 to STCR BFDCL Write 1 to STCR CF0MCL Write 1 to STCR CF1MCL The above diagram assumes the following ESMER ESME 1 CR1 BFE 1 CF0RE 1 CF1DS 1 0 10b PCR RXDXPS 0 ICR BFDIE 1 CF0MIE 1 CF1MIE 1 TMR TOMS 1 0 01b Set to 0 after Break Fi...

Page 700: ...Frame Select the data for comparison with Control Field 1 and the presence or absence of a priority interrupt bit Select the bit of Control Field 1 that will be the priority interrupt bit Select the bits for comparison in Control Field 1 Set the data for comparison with Control Field 1 Select the bits for comparison in Control Field 0 Set the data for comparison with Control Field 0 Set Break Fiel...

Page 701: ...ection of the Break Field low width At this time if the ICR BFDIE bit is 1 an SCIX0 interrupt is generated Clear the STR BFDF flag If the data received in Control Field 0 matches the comparison data the STR CF0MF flag is set An SCIX1 interrupt is also generated if the value of the ICR CF0MIE bit is 1 Clear the STR CF0MF flag If there is a match with the priority interrupt bit in Control Field 1 th...

Page 702: ...Ih Figure 23 66 State Transitions When Receiving a Start Frame CR3 SDST 1 Initialization Break Field low width detected CF0RR matches CF0DR Non match Non match Information Frame CR3 SDST 1 CF1RR matches PCF1DR SCF1DR or both or the priority interrupt bit is detected Break Field Control Field 0 Control Field 1 ...

Page 703: ...it is 1 Transfer of the Information Frame starts after that If the data received in Control Field 1 do not match the data set in either or both of registers PCF1DR and SCF1DR and the priority interrupt bit is not detected a transition to the state prior to Break Field low width detection proceeds Figure 23 67 Example of Operations When Receiving a Start Frame While the CR1 PIBE Bit is 1 RXDX12 pin...

Page 704: ... set with the CR2 BCCS 1 0 bits as the sampling clock and the STR BCDF flag is set to 1 if the signals fail to match three times in a row An SCIX2 interrupt is also generated if the value of the ICR BCDIE bit is 1 Figure 23 68 Example of Operations with Bus Collision Detection D C Q D C Q D C Q Base clock Divider No division Division by 2 Division by 4 RXDX12 input signal Bus collision clock STR B...

Page 705: ... the previous value is retained In other words levels are confirmed as being the signal if they are retained for at least three cycles of the sampling clock but judged to be noise rather than changes in the signal level if they change within three cycles of the sampling clock Figure 23 69 shows an example of operations with the digital filter Figure 23 69 Example of Operations with the Digital Fil...

Page 706: ... ICR AEDIE bit is 1 Retention by registers TCNT and TPRE is released by reading these registers 4 The bit rate as calculated from the values counted during intervals between valid edges can be used for adjusting the rate by changing the settings of the BRR register To disable the bit rate measurement after a match with Control Field 1 write 0 to the CR0 BRME bit Figure 23 70 Example of Operations ...

Page 707: ... CR2 RTS 1 0 bits to select the rising edges of 8th 10th 12th or 14th cycle of the base clock If the value of the SEMR ABCS bit is 1 the bits select the rising edges of 4th 5th 6th or 7th cycle of the base clock Figure 23 71 shows timing for the sampling of data received through RXDX12 Figure 23 71 Timing for Sampling of Data Received through RXDX12 16 clocks Base clock RTS 1 0 00b RXDX12 receive ...

Page 708: ...es to the high level and the STR BFDF flag is set to 1 An SCIX0 interrupt is also generated if the value of the ICR BFDIE bit is 1 When 0 is written to the TCR TCST bit counting stops after reloading of registers TPRE and TCNT After output of the Break Field low width is completed stop the timer before it underflows again Figure 23 72 shows an example of operations in Break Field low width output ...

Page 709: ...he timer after Break Field low width determination Figure 23 73 shows an example of operations in Break Field low width output mode Figure 23 73 Example of Operations in Break Field Low Width Determination Mode 3 Timer Mode This mode is for counting cycles of the internal clock as the clock source Setting the TMR TOMS 1 0 bits to 00b switches operation to timer mode The TMR TCSS 2 0 bits select th...

Page 710: ...nal produced by frequency dividing the signal from the clock source for the internal baud rate generator by one two four or eight as selected by the setting of the SNFR NFCS 2 0 bits If the base clock is stopped with the noise filter enabled and then the clock input is started again the noise filter operation resumes from where the clock was stopped If SCR TE and SCR RE are set to 0 during base cl...

Page 711: ...e the setting of the SCR TE bit is 1 2 When new data is not written by the time of transmission of the last bit of the current transmit data and the setting of the SCR TEIE bit is 1 the SSR TEND flag becomes 1 and a TEI interrupt request is generated Furthermore when the setting of the SCR TE bit is 1 the SSR TEND flag retains the value 1 until further transmit data are written to the TDR or TDRL ...

Page 712: ...automatically transmit the specified number of bytes including retransmission in the case of error occurrence However the ERS flag in the SSR register is not automatically cleared to 0 at error occurrence Therefore the ERS flag must be cleared by previously setting the RIE bit in the SCR register to 1 to enable an ERI interrupt request to be generated at error occurrence When transmitting receivin...

Page 713: ...alue of the IICINTM bit in the SIMR2 register is 0 an RXI request ACK detection if the input on the SSDAn pin is at the low level or a TXI request NACK detection if the input on the SSDAn pin is at the high level will be generated on the rising edge of the SSCLn signal for the ninth bit acknowledge bit If the RXI has been set up as an activating request for the DTC beforehand the RXI request will ...

Page 714: ...Interrupt Factors SCIX0 interrupt Break Field low width detected BFDF Detection of a Break Field low width longer than the interval corresponding to the timer setting Completion of the output of a Break Field low width over the interval corresponding to the timer setting Underflow of the timer SCIX1 interrupt Control Field 0 match CF0MF The data received in Control Field 0 matching the value set i...

Page 715: ...forcibly set the TXDn pin to mark or space state while the TE bit is 0 set the I O port associated registers and switch the TXDn pin to general output port For holding the communication line in the mark 1 state until the TE bit is set to 1 serial transmission is enabled set the corresponding bit in the PODR register to 1 for high output from general output port To start communications set the TE b...

Page 716: ...to four PCLK cycles or longer refer to Figure 23 75 Figure 23 75 Restrictions on Use of External Clock in Clock Synchronous Transmission D0 D1 D3 D4 D5 D7 D0 D2 D6 Synchronous clock external clock Serial transmit data TXI interrupt flag ICU IRn 1 1 Start of transmission and 2 Continuous transmission a D0 D1 D3 D4 D5 D7 D0 D2 D6 Update TDR before bit 7 is started to transmit when continuous transmi...

Page 717: ...ut pins may output the level before a transition to the low power consumption state is made after release from the module stopped state or software standby mode When transitions to these states are made during transmission the data being transmitted become indeterminate To transmit data in the same transmit mode after cancellation of the low power consumption state set the TE bit to 1 read SSR and...

Page 718: ...ND flag in SSR Make the I O port function settings Make the I O port function settings 2 3 1 Data being transmitted is lost halfway Data can be normally transmitted from the CPU by setting the TE bit in SCR to 1 reading SSR and writing data to TDR after canceling software standby mode However if the DTC has been activated the data remaining in the DTC will be transmitted when both the TE and TIE b...

Page 719: ...t Port Port Transition to software standby mode Software standby mode canceled SCKn output pin Port mode register PMR setting TXDn output pin SCI TXDn output SCR TE bit The level before transition to software standby mode is output The level at transition to software standby mode is retained Port input output Port input output Marking output SCI TXDn output Port Port Transition to software standby...

Page 720: ...In clock synchronous mode and simple SPI mode the external clock SCKn must be input as follows High pulse period low pulse period 2 PCLK cycles or more period 6 PCLK cycles or more Start data reception Initialization SCR RE 1 SCR RE 0 Read receive data in RDR Make transition to software standby mode Cancel software standby mode No No Yes Yes RXI interrupt Change operating mode Data reception 1 2 1...

Page 721: ... to the input signal on the SSn pin of a connected slave going to the high level before the final edge of the clock signal on the SCKn pin leading to incorrect operation of the slave In a multi master configuration take care because the SCKn pin output becomes high impedance while the input on the SSn pin is at the low level if a mode fault error occurs as the current character is being transferre...

Page 722: ... After reception of the Start Frame is completed set the SCR RIE bit to 1 by the time the first byte of the Information Frame is received 2 Set the SCR RIE bit to 1 to disable RXI interrupts and enable ERI interrupts for ICU Clear the IRn IR flag to enable the acceptance of RXI interrupts by ICU by the time the first byte of the Information Frame is received after the completion of Start Frame rec...

Page 723: ...Change the pin function to general purpose I O port output before setting the TE bit to 0 Note 1 An interrupt is generated when the TE bit is set to 1 while the TXI interrupt is enabled If this creates a problem change the pin function to TXDn first and then set the corresponding ICU IERm IENj bit to 1 23 13 15 Note on Stopping Reception When Using the RTS Function in Asynchronous Mode One clock c...

Page 724: ...owledge field in response to the received value is possible Wait function In reception the following periods of waiting can be obtained by holding the SCL clock at the low level Waiting between the eighth and ninth clock cycles Waiting between the ninth clock cycle and the first clock cycle of the next transfer SDA output delay function Timing of the output of transmitted data including the acknow...

Page 725: ... Output control Noise canceller ICDRS ICDRT ICDRR Address comparator ICCR2 ICMR1 ICMR2 ICMR3 ICFER ICSR1 ICSR2 ICSER ICIER ICBRH ICBRL Timeout circuit Interrupt generator Transmission reception control circuit Transfer clock generator ACK output circuit SCL0 SDA0 NACK decision ACK reception circuit Internal data bus BC 2 0 CKS 2 0 CLO SDAI BBSY MST TRS SDA output delay control ST RS SP IICRST SDDL...

Page 726: ...IIC is CMOS when I2C bus is selected ICMR3 SMBS bit is 0 or TTL when SMBus is selected ICMR3 SMBS bit is 1 Table 24 2 RIIC Pin Configuration Channel Pin Name I O Function RIIC0 SCL0 I O RIIC0 serial clock I O pin SDA0 I O RIIC0 serial data I O pin Power supply for pull up VCC to 5 V SCL SDA Master Slave 1 SCL SDA Slave 2 SCL SDA SCL SDA SCLin SDAin SCLout SDAout SCLin SDAin SCLout SDAout SCLin SDA...

Page 727: ...w 1 SDA0 line is high R b1 SCLI SCL Line Monitor 0 SCL0 line is low 1 SCL0 line is high R b2 SDAO SDA Output Control Monitor Read 0 The RIIC has driven the SDA0 pin low 1 The RIIC has released the SDA0 pin Write 0 The RIIC drives the SDA0 pin low 1 The RIIC releases the SDA0 pin R W b3 SCLO SCL Output Control Monitor Read 0 The RIIC has driven the SCL0 pin low 1 The RIIC has released the SCL0 pin ...

Page 728: ... reset is initiated using the IICRST bit for a bus hang up occurred during communication with the master device in slave mode the states may become different between the slave device and the master device due to the difference in the bit counter information For this reason do not initiate an internal reset in slave mode but initiate restoration processing from the master device If an internal rese...

Page 729: ...dition issuance request when the BBSY flag is set to 0 bus free state Note that arbitration may be lost due to a start condition issuance error if the ST bit is set to 1 start condition issuance request when the BBSY flag is set to 1 bus busy state Address es RIIC0 ICCR2 0008 8301h b7 b6 b5 b4 b3 b2 b1 b0 BBSY MST TRS SP RS ST Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b...

Page 730: ...slave mode the restart condition is not issued but the RS bit remains set to 1 If the operating mode changes to master mode with the bit not being cleared note that the restart condition may be issued SP Bit Stop Condition Issuance Request This bit is used to request that a stop condition be issued in master mode When this bit is set to 1 to request to issue a stop condition a stop condition is is...

Page 731: ... which an R W bit with the value 1 is appended In slave mode a match between the received address and the address enabled in the ICSER register when the value of the received R W bit is 0 including cases where the received address is the general call address In slave mode a restart condition is detected a start condition is detected with ICCR2 BBSY flag is 1 and ICCR2 MST bit is 0 When 0 is writte...

Page 732: ...tart condition has been issued When the SDA0 line changes from low to high under the condition of SCL0 line high this bit is set to 0 after the bus free time specified in the ICBRL register start condition is not detected assuming that a stop condition has been issued Setting condition When a start condition is detected Clearing conditions When the bus free time specified in the ICBRL register sta...

Page 733: ...e end of a data transfer including the acknowledge bit or when a start condition including a restart condition is detected Address es RIIC0 ICMR1 0008 8302h b7 b6 b5 b4 b3 b2 b1 b0 MTWP CKS 2 0 BCWP BC 2 0 Value after reset 0 0 0 0 1 0 0 0 Bit Symbol Bit Name Description R W b2 to b0 BC 2 0 Bit Counter b2 b0 0 0 0 9 bits 0 0 1 2 bits 0 1 0 3 bits 0 1 1 4 bits 1 0 0 5 bits 1 0 1 6 bits 1 1 0 7 bits...

Page 734: ...s enabled ICFER TMOE bit is 1 Address es RIIC0 ICMR2 0008 8303h b7 b6 b5 b4 b3 b2 b1 b0 DLCS SDDL 2 0 TMOH TMOL TMOS Value after reset 0 0 0 0 0 1 1 0 Bit Symbol Bit Name Description R W b0 TMOS Timeout Detection Time Select 0 Long mode is selected 1 Short mode is selected R W b1 TMOL Timeout L Count Control 0 Count up is disabled while the SCL0 line is at a low level 1 Count up is enabled while t...

Page 735: ...ll types of SDA output including the transmission of the acknowledge bit Set the SDA output delay time to meet the I2C bus specification within the data enable time acknowledge enable time 1 or the SMBus specification within the data hold time 300 ns or more and SCL clock low level period the data setup time 250 ns Note that if a value outside the specification is set communication with communicat...

Page 736: ...0 0 0 Bit Symbol Bit Name Description R W b1 b0 NF 1 0 Noise Filter Stage Select b1 b0 0 0 Noise of up to one IICφ cycle is filtered out single stage filter 0 1 Noise of up to two IICφ cycles is filtered out 2 stage filter 1 0 Noise of up to three IICφ cycles is filtered out 3 stage filter 1 1 Noise of up to four IICφ cycles is filtered out 4 stage filter R W b2 ACKBR Receive Acknowledge 0 0 is re...

Page 737: ...at the falling edge of the eighth SCL clock cycle and the RDRF flag is set to 1 at the rising edge of the ninth SCL clock cycle When the RDRFS bit is 1 the RDRF flag is set to 1 at the rising edge of the eighth SCL clock cycle and the SCL0 line is held low at the falling edge of the eighth SCL clock cycle The low hold of the SCL0 line is released by writing a value to the ACKBT bit After data is r...

Page 738: ... NACKE SALE NALE MALE TMOE Value after reset 0 1 1 1 0 0 1 0 Bit Symbol Bit Name Description R W b0 TMOE Timeout Function Enable 0 The timeout function is disabled 1 The timeout function is enabled R W b1 MALE Master Arbitration Lost Detection Enable 0 Master arbitration lost detection is disabled Disables the arbitration lost detection function and does not clear the ICCR2 MST and TRS bits automa...

Page 739: ...This bit is used to specify whether to synchronize the SCL clock with the SCL input clock Normally set this bit to 1 When the SCLE bit is set to 0 no SCL synchronous circuit used the RIIC does not synchronize the SCL clock with the SCL input clock In this setting the RIIC outputs the SCL clock with the transfer rate set in registers ICBRH and ICBRL regardless of the SCL0 line state For this reason...

Page 740: ...ice ID the RIIC recognizes that the device ID address has been received When the following R W bit is 0 write the RIIC recognizes the second and the following bytes as slave addresses and continues the receive operation When this bit is set to 0 the RIIC ignores the received first byte even if it matches the device ID address and recognizes the first byte as a normal slave address For details on t...

Page 741: ...t is 1 When this bit is set to 1 while the ICMR3 SMBS bit is 1 if the received slave address matches the host address the RIIC recognizes the received slave address as the host address independently of the slave addresses set in registers SARLy and SARUy y 0 to 2 and performs the receive operation When the ICMR3 SMBS bit or the HOAE bit is set to 0 the received slave address is ignored even if it ...

Page 742: ...eive Data Full Interrupt Request Enable This bit is used to enable or disable receive data full interrupt RXI requests when the ICSR2 RDRF flag is set to 1 Address es RIIC0 ICIER 0008 8307h b7 b6 b5 b4 b3 b2 b1 b0 TIE TEIE RIE NAKIE SPIE STIE ALIE TMOIE Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 TMOIE Timeout Interrupt Request Enable 0 Timeout interrupt TMOI request i...

Page 743: ... used to enable or disable transmit end interrupt TEI requests when the ICSR2 TEND flag is set to 1 An TEI interrupt request is canceled by setting the TEND flag or the TEIE bit to 0 TIE Bit Transmit Data Empty Interrupt Request Enable This bit is used to enable or disable transmit data empty interrupt TXI requests when the ICSR2 TDRE flag is set to 1 ...

Page 744: ... 0 bits value with the ICSER SARyE bit set to 1 slave address y detection enabled This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte Address es RIIC0 ICSR1 0008 8308h b7 b6 b5 b4 b3 b2 b1 b0 HOA DID GCA AAS2 AAS1 AAS0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 AAS0 Slave Address 0 Detection Flag 0 Slave address 0 is not detected 1 ...

Page 745: ...on When the first byte received immediately after a start condition or restart condition is detected matches a value of device ID 1111 100b 0 write with the ICSER DIDE bit set to 1 device ID address detection is enabled This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the first byte Clearing conditions When 0 is written to the DID flag after reading DID flag to be 1 When a ...

Page 746: ...2019 RX13T Group 24 I2C bus Interface RIICa host address detection is enabled This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte When 1 is written to the ICCR1 IICRST bit to apply an RIIC reset or an internal reset ...

Page 747: ...ot match the value of the bit being output sets the value of the AL flag to 1 to indicate that the bus is occupied by another device The RIIC can also set the flag to indicate the detection of loss of arbitration during NACK transmission in master mode or during data transmission in slave mode Address es RIIC0 ICSR2 0008 8309h b7 b6 b5 b4 b3 b2 b1 b0 TDRE TEND RDRF NACKF STOP START AL TMOF Value a...

Page 748: ... 0 is written to the AL flag after reading AL 1 When 1 is written to the ICCR1 IICRST bit to apply an RIIC reset or an internal reset Don t care START Flag Start Condition Detection Flag Setting condition When a start condition or a restart condition is detected Clearing conditions When 0 is written to the START bit after reading START 1 When a stop condition is detected When 1 is written to the I...

Page 749: ... to 0 Clearing conditions When 0 is written to the RDRF bit after reading RDRF 1 When data is read from the ICDRR register When 1 is written to the ICCR1 IICRST bit to apply an RIIC reset or an internal reset TEND Flag Transmit End Flag Setting condition At the rising edge of the ninth SCL clock cycle while the TDRE flag is 1 Clearing conditions When 0 is written to the TEND bit after reading TEND...

Page 750: ...g of this bit is ignored SVA 6 0 Bits 7 Bit Address 10 Bit Address Lower Bits When the 7 bit address format is selected SARUy FS bit is 0 these bits function as a 7 bit address When the 10 bit address format is selected SARUy FS bit is 1 these bits function as the lower 8 bits of a 10 bit address in combination with the SVA0 bit While the ICSER SARyE bit is 0 the setting of these bits is ignored A...

Page 751: ...of the SVA 1 0 bits and SARLy are valid While the ICSER SARyE bit is 0 registers SARLy and SARUy disabled the setting of the SARUy FS bit is invalid SVA 1 0 Bits 10 Bit Address Upper Bits When the 10 bit address format is selected FS 1 these bits function as the upper 2 bits of a 10 bit address When the ICSER SARyE bit is set to 1 SARLy and SARUy enabled and the SARUy FS bit is 1 these bits are va...

Page 752: ...ernal reference clock IICφ specified by the ICMR1 CKS 2 0 bits If the digital noise filter is enabled the ICFER NFE bit is 1 set the ICBRL register to a value at least one greater than the number of stages in the noise filter Regarding the number of stages in the noise filter see the description of the ICMR3 NF 1 0 bits Note 1 Data setup time tSU DAT 250 ns up to 100 kbps Standard mode Sm 100 ns u...

Page 753: ...on of the ICMR3 NF 1 0 bits The I2C transfer rate and the SCL clock duty are calculated using the following expression Transfer rate 1 ICBRH 1 ICBRL 1 IICφ 1 SCL0 line rising time tr SCL0 line falling time tf Duty cycle SCL0 line rising time tr 2 ICBRH 1 IICφ SCL0 line falling time tf 2 ICBRL 1 IICφ Note 1 IICφ PCLK Division ratio Note 2 The SCL0 line rising time tr and SCL0 line falling time tf d...

Page 754: ...F6h 25 F9h 101b 13 EDh 15 EFh 101b 16 F0h 20 F4h 50 010b 16 F0h 19 F3h 010b 21 F5h 24 F8h 011b 12 ECh 15 EFh 100 001b 15 EFh 18 F2h 001b 19 F3h 23 F7h 001b 24 F8h 29 FDh 400 000b 4 E4h 10 EAh 000b 5 E5h 12 ECh 000b 7 E7h 16 F0h Transfer Rate kbps Operating Frequency PCLK MHz 16 20 25 CKS 2 0 ICBRH ICBRL CKS 2 0 ICBRH ICBRL CKS 2 0 ICBRH ICBRL 10 101b 22 F6h 25 F9h 110b 13 EDh 15 EFh 110b 16 F0h 20...

Page 755: ...of the ICDRS register and the ICDRR register allows continuous receive operation if the received data has been read from the ICDRR register while the ICDRS register is receiving data The ICDRR register cannot be written Read data from the ICDRR register once when a receive data full interrupt RXI request is generated If the ICDRR register receives the next receive data before the current data is r...

Page 756: ...r device when R W is 1 or from the master device to the slave device when R W is 0 A Acknowledge The receive device drives the SDA0 line low In master transmit mode the slave device returns acknowledge In master receive mode the master device returns acknowledge A Not Acknowledge The receive device drives the SDA0 line high Sr Restart condition The master device drives the SDA0 line low from the h...

Page 757: ...been completed set the ICCR1 IICRST bit to 0 releases the RIIC reset This step is not necessary if initialization of the RIIC has already been completed Figure 24 5 Example of RIIC Initialization Flowchart Set transfer bit rate 1 2 Initial settings Set ICMR1 CKS 2 0 bits and ICBRL ICBRH registers Set registers ICMR2 and ICMR3 Set ICFER register Set ICCR1 ICE bit to 0 Set ICCR1 IICRST bit to 1 Set ...

Page 758: ...cally set to 0 the data are transferred from the ICDRT register to the ICDRS register and the TDRE flag is again set to 1 After the byte containing the slave address and R W bit has been transmitted the value of the TRS bit is automatically updated to select master transmit or master receive mode in accord with the value of the transmitted R W bit If the value of the R W bit was 0 the RIIC continu...

Page 759: ...es No ICSR2 TDRE 1 Write data to ICDRT register Initial settings Yes Yes All data transmitted ICSR2 TEND 1 Yes ICSR2 STOP 1 ICSR2 STOP 0 No No No No No 1 Initial settings 2 Check I2 C bus occupation and issue a start condition 6 Check stop condition issuance 7 Processing for the next transfer operation Yes 5 Check end of last data transmission and issue a stop condition 3 Transmit slave address an...

Page 760: ...RR 9 ACKBT ACKBR 0 ACK X ACK NACK 3 4 4 2 4 0 ACK ACK ACK 0 ACK XXXX Initial value last data for reception Automatic low hold to prevent wrong transmission Transmit data DATA 1 SCL0 SDA0 Transmit data upper 10 bits W 0 ACK Write data to ICDRT register 11110b 2 bits W Write data to ICDRT register lower 8 bits Write data to ICDRT register DATA 1 Write data to ICDRT register DATA 2 Write 1 to ST bit ...

Page 761: ... condition as requested by the ST bit has been successfully completed and bits MST and TRS in the ICCR2 register are automatically set to 1 placing the RIIC in master transmit mode The ICSR2 TDRE flag is also automatically set to 1 in response to setting of the TRS bit to 1 3 Check that the ICSR2 TDRE flag is 1 and then write the value for transmission the first byte indicates the slave address an...

Page 762: ...e next to last byte set the ICMR3 WAIT bit to 1 for wait insertion before reading the ICDRR register containing the second byte from last As well as enabling NACK output even in the case of delays in processing to set the ICMR3 ACKBT bit to 1 NACK in step 6 due to other interrupts etc this fixes the SCL0 line to the low level on the falling edge of the ninth clock cycle in reception of the last by...

Page 763: ...No ICSR2 STOP 0 Yes ICCR2 SP 1 Read the ICDRR register ICMR3 WAIT 0 ICSR2 STOP 0 ICCR2 SP 1 Dummy read the ICDRR register ICSR2 STOP 1 No Yes ICSR2 NACKF 0 ICSR2 STOP 0 Master reception ends 1 Initial settings 2 Check I2 C bus occupation and issue a start condition 3 Transmit the slave address followed by R and check ACK 4 Set to WAIT 5 Set to NACK When receiving 2 bytes perform dummy read 6 Read ...

Page 764: ... Next data Final byte 1 No Read ICDRR register Set ICMR3 ACKBT bit Read ICDRR register No No ICSR2 STOP 0 ICCR2 SP 1 Read ICDRR register ICMR3 WAIT 0 ICSR2 STOP 0 ICCR2 SP 1 Perform dummy read of ICDRR register ICSR2 STOP 1 No End of master reception ICSR2 NACKF 0 ICSR2 STOP 0 Yes 1 Initial settings 4 Perform dummy read 5 Read received data and prepare for receiving final data 6 Set the acknowledg...

Page 765: ...ve mode ACKBT ACKBR 3 4 5 2 0 ACK 0 ACK ACK Receive data 7 bit address R 7 bit address R ACK Receive data DATA 1 SCL0 SDA0 Write 1 to ST bit Write data to ICDRT register 11110b 2 bits R 0 ACK XXXX Initial value last data for reception XXXX Initial value last data for reception Upper 10 bits R Upper 10 bits R Master transmit mode Master receive mode Automatic low hold to prevent wrong transmission ...

Page 766: ... DATA n 2 0 ACK 0 ACK 0 ACK Write 1 to WAIT bit Read ICDRR register DATA n 2 ACK ACK XXXX last data for transmission 7 bit addresses R Upper 10 bits R Receive data DATA n 2 Clear STOP flag DATA n 1 Automatic low hold WAIT Read ICDRR register last data for reception DATA n 0 ACK DATA n DATA n 1 2 b6 4 b4 5 b3 6 b2 7 b1 3 b5 8 b0 DATA n 9 NACK 6 7 P 9 1 NACK 1 NACK Set WAIT bit to 0 Write 1 to SP bi...

Page 767: ...f the R W bit that was also received at this time is 1 the RIIC automatically places itself in slave transmit mode by setting both the ICCR2 TRS bit and the ICSR2 TDRE flag to 1 3 After the ICSR2 TDRE flag is confirmed to be 1 write the data for transmission to the ICDRT register At this time if the RIIC does not receive acknowledge from the master device receives an NACK signal while the ICFER NA...

Page 768: ...ransmission Yes No ICSR2 NACKF 0 ICSR2 TDRE 1 Write data to ICDRT register Yes Yes All data transmitted Yes ICSR2 STOP 0 No No No No 1 Initial settings 2 3 Check ACK bit and set transmit data Checking of ACK not necessary immediately after address is received 5 Check stop condition issuance Yes 4 Dummy read to release the SCL 6 Processing for the next transfer operation Initial settings ICSR2 TEND...

Page 769: ...de AASy XXXX Initial value last data for transmission 7 bit address R XXXX Initial value last data for reception 0 ACK X ACK NACK 0 ACK Write data to ICDRT register DATA 2 Write data to ICDRT register DATA 3 ACK ACK Transmit data DATA 2 Transmit data DATA 1 SCL0 SDA0 ACK TDRE MST TRS BBSY TEND STOP ICDRT ICDRS DATA n DATA n 2 b6 4 b4 5 b3 6 b2 7 b1 3 b5 8 b0 1 b7 2 b6 4 b4 5 b3 6 b2 7 b1 3 b5 8 b0...

Page 770: ...and the ICSR2 RDRF flag to be 1 dummy read the ICDRR register the dummy value consists of the slave address and R W bit when the 7 bit address format is selected or the lower 8 bits when the 10 bit address format is selected 4 When the ICDRR register is read the RIIC automatically sets the ICSR2 RDRF flag to 0 If reading of the ICDRR register is delayed and a next byte is received while the RDRF f...

Page 771: ...b4 3 b5 DATA 1 DATA 2 RDRF ICDRR ACKBT ACKBR 3 1 b7 DATA 1 3 4 8 b0 9 1 b7 DATA 1 AASy Receive data 7 bit address W Receive data DATA 1 XXXX Initial value last data for transmission 7 bit address W 0 ACK 0 ACK Read ICDRR register DATA 1 ACK ACK SCL0 SDA0 XXXX Initial value last data for transmission 0 ACK Read ICDRR register DATA n 2 TDRE MST TRS BBSY TEND STOP ICDRT ICDRS DATA n 2 b6 4 b4 5 b3 6 ...

Page 772: ...the width at low level specified in the ICBRL register When the RIIC finishes counting out the width at low level it stops driving the SCL0 line to the low level i e releases the line At this time if the width at low level of the SCL clock signal from the other master device is longer than the width at low level set in the RIIC the width at low level of the SCL signal will be extended Once the wid...

Page 773: ...S bit selects the clock source for counting by the SDA output delay counter as the internal base clock IICφ for the RIIC module or as a clock signal derived by dividing the frequency of the internal base clock by two IICφ 2 The counter counts the number of cycles set in the ICMR2 SDDL 2 0 bits After counting of the set number of cycles of delay is completed the RIIC module places the required outp...

Page 774: ...ICφ signal When the input signal level matches the output level of the number of effective flip flop circuit stages as selected by the ICMR3 NF 1 0 bits the signal level is conveyed to the subsequent stage If the signal levels do not match the previous value is retained If the ratio between the frequency of the internal operating clock PCLK and the transfer rate is small e g data transfer at 400 k...

Page 775: ... following R W bit This causes a receive data full interrupt RXI or transmit data empty interrupt TXI to be generated The AASy flag is used to identify which slave address has been specified Figure 24 24 to Figure 24 26 show the AASy flag set timing in three cases Figure 24 24 AASy Flag Set Timing with 7 Bit Address Format Selected TDRE AASy S 1 2 3 4 5 6 7 7 bit slave address 8 W 1 8 R 9 ACK TRS ...

Page 776: ...dresses Upper 2 bits Lower 8 bits Upper 2 bits Receive data lower addresses R SCL0 SDA0 SCL0 SDA0 Upper 2 bits Address match AAS1 AAS2 AAS0 BBSY 1 W 1 1 1 0 Lower 8 bits R W Address match AAS1 AAS2 AAS0 BBSY Address mismatch Address match W DATA 1 1 1 1 0 R W AAS1 AAS2 AAS0 BBSY S 7 bit slave address SARL0 Address mismatch Address match DATA R W 7 bit slave address SARL1 R W Address match Address ...

Page 777: ...d the ICSR2 RDRF flag are set to 1 on the rising edge of the ninth cycle of SCL clock This leads to the generation of a receive data full interrupt RXI The value of the GCA flag can be confirmed to recognize that the general call address has been transmitted Operation after detection of the general call address is the same as normal slave receive operation Figure 24 27 Timing of GCA Flag Setting d...

Page 778: ...nt bytes and sets the ICSR2 TDRE flag to 1 In the device ID address detection function the RIIC sets the DID flag to 0 if a match with the RIIC s own slave address is not obtained or a match with the device ID address is not obtained after a match with the RIIC s own slave address and the detection of a restart condition If the first byte after detection of a start or restart condition matches the...

Page 779: ...Y RDRF ACK Address 1 DID Slave address match AASy BBSY ACK Address DID R W Slave address mismatch Device ID mismatch RDRF W W 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 7 bit slave address other station AASy BBSY DID TDRE 0 0 1 1 1 1 R NACK NACK 1 0 0 1 1 1 1 R NACK Comparing the second and the following bytes is stopped RDRF ACK ACK ACK 1 1 1 Read ICDRR register Dummy read 7 bit address lower 10 bits S ...

Page 780: ... bit is 0 Wr bit This causes a receive data full interrupt RXI to be generated The HOA flag is used to recognize that the host address was sent from the smart battery or other devices If the bit following the host address 0001 000b is an Rd bit R W bit is 1 the RIIC can also detect the host address After the host address is detected the RIIC operates in the same manner as normal slave operation Fi...

Page 781: ...de Low level interval between the ninth clock cycle of one transfer and the first clock cycle of the next Figure 24 30 Automatic Low Hold Operation in Transmit Mode 8 R 9 ACK TDRE AASy TRS BBSY RDRF S 1 2 3 4 5 6 7 2 3 4 5 6 7 8 9 ACK 2 3 Master transmit mode Slave transmit mode TDRE AASy TRS BBSY RDRF S 2 3 4 5 6 7 2 3 4 5 6 7 8 9 ACK 8 W 9 ACK 2 1 1 1 1 1 Data DATA 1 7 bit slave address Data DAT...

Page 782: ...CKF flag to 0 issue a restart condition or issue a stop condition and then issue a start condition again Figure 24 31 Abort of Data Transfer When NACK is Received NACKE 1 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 1 W A W A 7 bit slave address 7 bit slave address S P S BBSY AASy TRS TDRE NACKF Automatic low hold to prevent wrong transmission Master transmit mode Write data to ICDRT register 7 bit address W...

Page 783: ...s the ICMR3 ACKBT bit value for the acknowledge bit in the period from the falling edge of the eighth SCL clock cycle to the falling edge of the ninth SCL clock cycle and automatically holds the SCL0 line low at the falling edge of the ninth SCL clock cycle using the WAIT bit function This low hold is released by reading data from the ICDRR register which enables bytewise receive operation The WAI...

Page 784: ... prevent failure to receive data Automatic low hold RDRFS Automatic low hold RDRFS RDRFS 1 WAIT 0 RDRFS 1 WAIT 1 Write 0 to ACKBT bit Read ICDRR register Read ICDRR register Write 0 to ACKBT bit ACK Data ACK Data ACK Automatic low hold RDRFS Automatic low hold WAIT Automatic low hold RDRFS Write 0 to ACKBT bit Read ICDRR register Read ICDRR register Write 0 to ACKBT bit 2 3 4 5 6 7 8 1 2 3 4 2 3 4...

Page 785: ...ission including the address bits i e the internal SDA output level and the level on the SDA0 line do not match the high output as the internal SDA output i e the SDA0 pin is in the high impedance state and the low level is detected on the SDA0 line the RIIC loses in arbitration After a loss in arbitration of mastership the RIIC immediately enters slave receive mode If a slave address including th...

Page 786: ... 8 W Read ICDRR register General call address match 0000 000b W Transmit data mismatch Arbitration lost Release SCL SDA TRS AL MST BBSY GCA RDRF TRS AL MST BBSY AASy TDRE Transmit data mismatch Arbitration lost Release SCL SDA ACK ACK ACK Clear AL flag to 0 Clear AL flag to 0 ACK ACK Receive data SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 S PCLK S 1 S 8 R 9 1 2 1 2 6 7 1 ACK 7 bit 10 bit slave addres...

Page 787: ...2 final bytes of data from the slave device Meanwhile master B sends ACK because it has not received necessary 4 bytes of data At this time the NACK transmission from master A and the ACK transmission from master B conflict In general if a conflict like this occurs master A cannot detect ACK transmitted by master B and issues a stop condition Therefore the issuance of the stop condition conflicts ...

Page 788: ...ve arbitration the RIIC is immediately released from the slave matched state and enters slave receive mode This function can detect conflicts of data during transmission of UDIDs over an SMBus and eliminate subsequent redundant processing processing for the transmission of FFh The RIIC detects slave arbitration lost when the following condition is met with the ICFER SALE bit set to 1 slave arbitra...

Page 789: ...uance request is made and the RIIC issues a restart condition when the ICCR2 BBSY flag is 1 bus busy state and the ICCR2 MST bit is 1 master mode A restart condition is issued in the following sequence Restart condition issuance 1 Release the SDA0 line 2 Ensure the low level period of SCL0 line set in the ICBRL register 3 Release the SCL0 line low level to high level 4 Detect a high level of the S...

Page 790: ...igh level to low level 2 Ensure the low level period of SCL0 line set in the ICBRL register 3 Release the SCL0 line low level to high level 4 Detect a high level of the SCL0 line and ensure the time set in the ICBRH register and the stop condition setup time 5 Release the SDA0 line low level to high level 6 Ensure the time set in the ICBRL register and the bus free time 7 Set the BBSY flag to 0 to...

Page 791: ...w level period or high level period using the internal counter The timeout function resets the internal counter each time the SCL0 line changes rising or falling but continues to count unless the SCL0 line changes If the internal counter overflows due to no SCL0 line change the RIIC can detect the timeout and report the bus hung state This timeout function is enabled when the ICFER TMOE bit is 1 I...

Page 792: ...Clear internal counter Clear internal counter Clear internal counter Start internal counter Start internal counter Start internal counter 16 bit counter overflows 14 bit counter overflows Write 1 to TMOL bit Write 0 to TMOE bit Write 0 to TMOL bit Write 1 to TMOH bit Clear internal counter Start internal counter Example of operation when TMOH 1 and TMOL 1 BBSY TMOF TMOE Clear internal counter Clea...

Page 793: ...device is holding the SDA0 line at the low level because synchronization with the slave device has been lost due to the effects of noise etc the output of a stop condition is not possible The facility for output of an extra cycle of the SCL clock can be used to output extra cycles of SCL one by one to make the slave device release the SDA0 line from being held at the low level thus recovering the ...

Page 794: ...t be sure to set the ICCR1 IICRST bit to 0 Both types of reset are effective for release from bus hung states because both restore the output state of the SCL0 and SDA0 pins to the high impedance state Issuing a reset during slave operation may lead to a loss of synchronization between the master device clock and the slave device clock so avoided this where possible Note that monitoring of the bus...

Page 795: ... ms min of the SMBus specification the slave device must release the bus by writing 1 to the ICCR1 IICRST bit to issue an internal reset of the RIIC When an internal reset is issued the RIIC stops driving the bus for the SCL0 pin and SDA0 pin and make the SCL0 SDA0 pin outputs high impedance which releases the bus 2 Measuring timeout of master device The following periods timeout interval TLOW MEX...

Page 796: ... SCL clock cycle during reception of the final byte and hold the SCL0 line low at the falling edge of the eighth clock cycle 24 12 3 SMBus Host Notification Protocol Notify ARP Master Command In communications over an SMBus a slave device can temporarily act as a master device to notify the SMBus host or ARP master of its own slave address or to request its own slave address from the SMBus host Fo...

Page 797: ...detected interrupted it does not require clearing Furthermore the ICSR2 RDRF flag a condition for RXI is automatically set to 0 when data are read from the ICDRR register Note 3 When using the TEI interrupt clear the ICSR2 TEND flag in the TEI interrupt handling Note that the ICSR2 TEND flag is automatically set to 0 when data for transmission are written to the ICDRT register or a stop condition ...

Page 798: ...ained Retained ST RS To be reset To be reset TRS MST Retained To be reset SP To be reset ICMR1 BC 2 0 To be reset To be reset To be reset To be reset Retained Others Retained Retained ICMR2 To be reset To be reset Retained Retained Retained ICMR3 ACKBT To be reset To be reset Retained Retained To be reset Others Retained ICFER To be reset To be reset Retained Retained Retained ICSER To be reset To...

Page 799: ...Starting Transfer If the IR flag corresponding to the RIIC interrupt is 1 when transfer is started ICCR1 ICE bit is 1 follow the procedure below to clear interrupts before enabling operations Starting transfer with the IR flag set to 1 while the ICCR1 ICE bit is 1 leads to an interrupt request being internally retained after transfer starts and this can lead to unanticipated behavior of the IR fla...

Page 800: ...ecifications Item Description Data for CRC calculation 1 CRC codes are generated for any desired data in 8n bit units where n is a whole number CRC processor unit 8 bit parallel processing CRC generating polynomial One of three generating polynomials is selectable 8 bit CRC X8 X2 X 1 16 bit CRC X16 X15 X2 1 X16 X12 X5 1 CRC calculation switching The bit order of CRC calculation results can be swit...

Page 801: ...ad as 0 Only 1 can be written 25 2 2 CRC Data Input Register CRCDIR CRCDIR is a readable and writable register Write data for CRC calculation to this register Address es 0008 8280h b7 b6 b5 b4 b3 b2 b1 b0 DORCL R LMS GPS 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 GPS 1 0 CRC Generating Polynomial Switching b1 b0 0 0 No calculation is executed 0 1 8 bit CRC X8 X...

Page 802: ...lue Data written to the CRCDIR register is CRC calculated and the result is stored in the CRCDOR register If the CRC code is calculated following the transferred data and the result is 0000h there is no CRC error When an 8 bit CRC X8 X2 X 1 polynomial is in use the valid CRC code is obtained in the low order byte b7 to b0 The high order byte b15 to b8 is not updated Address es 0008 8282h b15 b14 b...

Page 803: ...0 CRCDIR CRC code generation 1 1 1 1 0 0 0 0 CRC code Output Data 7 7 7 F F F 0 8 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 2 Write F0h to the CRC data input register CRCDIR 3 Read the calculation result in the CRC data output register CRCDOR CRC code F78Fh 4 8 bit serial transmission LSB first 1 Write 83h to the CRC control register CRCCR 0 0 0 0 0 0 0 0 CRCDOR 15 0 1 1 1 1 0 1 1 1 1 0 ...

Page 804: ...1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 CRC code CRC code generation 1 8 bit serial reception LSB first 2 Write 83h to the CRC control register CRCCR 3 Write F0h to the CRC data input register CRCDIR 4 Write 8Fh to the CRC data input register CRCDIR 5 Write F7h to the CRC data input register CRCDIR 6 Read the calculation result in the CRC data output register CRCDOR C...

Page 805: ...OR Clear CRCDOR 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDIR 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 CRC code generation 2 Write 87h to the CRC control register CRCCR 3 Write F0h to the CRC data input register CRCDIR 4 Write EFh to the CRC data input register CRCDIR 5 Write 1Fh to the ...

Page 806: ...mission Note that the sequence of transmission for the CRC code differs according to whether transmission is LSB first or MSB first Figure 25 6 LSB First and MSB First Data Transmission CRCDIR CRCDOR 1 CRC code CRC code generation After specifying the method for generation calculation write data to CRCDIR register in the order of 1 2 3 and 4 Output 15 7 7 0 0 0 0 7 0 0 0 0 7 7 7 7 1 CRC code H CRC...

Page 807: ...During group priority operation in addition to the above mentioned operation a trigger to start scanning for the priority group is accepted during scan for the low priority group and scan for the priority group is started after scan for the low priority group was discontinued The priority order is group A group B group C Accordingly as priority operation when a trigger to start scanning for group ...

Page 808: ...arbitrarily selected A D conversion is performed only once on the internal reference voltage Continuous scan mode A D conversion is performed repeatedly on the analog inputs arbitrarily selected Group scan mode Two groups A and B or three groups A B and C can be selected as the number of the groups to be used Only the combination of groups A and B can be selected when the number of the groups is t...

Page 809: ...scan end interrupt request GCADI can be generated on completion of group C scan When double trigger mode is selected in group scan mode an A D scan end interrupt request S12ADI can be generated on completion of double scan of group A and the corresponding scan end interrupt request GBADI GCADI can be generated on completion of group B and group C scan The S12ADI GBADI and GCADI interrupts can acti...

Page 810: ...mplifier PGA is included in AN000 to AN002 Successive approximation register Analog multiplexer 12 bit D A A D control register Bus interface Control circuit including decoder A D data register Sample and hold circuit AVCC0 AVSS0 AN007 AN003 Interrupt signal S12ADI GBADI GCADI Asynchronous trigger ADTRG0 Comparator AN002 AN001 AN000 Comparator C Programmable gain amplifier Programmable gain amplif...

Page 811: ...t pin Incorporated Incorporated AN001 Input Analog input pin Incorporated Incorporated AN002 Input Analog input pin Incorporated Incorporated AN003 Input Analog input pin AN004 Input Analog input pin AN005 Input Analog input pin AN006 Input Analog input pin AN007 Input Analog input pin ADTRG0 Input External trigger input pin for starting A D conversion ADST0 Output ADST bit state output pin AVCC0 ...

Page 812: ...average The data formats for each given condition are shown below 1 When A D Converted Value Addition Average Mode is Not Selected Flush right format The A D converted value is stored in bits 11 to 0 Bits 15 to 12 are read as 0 Flush left format The A D converted value is stored in bits 15 to 4 Bits 3 to 0 are read as 0 2 When A D Converted Average Mode is Selected Flush right format The mean valu...

Page 813: ...lue added by the A D converted value of the same channel is stored in bits 15 to 0 When A D converted addition mode is selected the value added by the A D converted value of the same channel is indicated The number of A D conversions can be set to 1 2 3 4 or 16 times If A D converted addition mode is selected when the conversion count is set to 1 to 4 times the value added by the A D conversion re...

Page 814: ...re shown below Flush right format The A D converted value is stored in bits 11 to 0 The self diagnosis status is stored in bits 15 and 14 Bits 13 and 12 are read as 0 Flush left format The A D converted value is stored in bits 15 to 4 The self diagnosis status is stored in bits 1 and 0 Bits 3 and 2 are read as 0 Note For details of self diagnosis see section 26 2 9 A D Control Extended Register AD...

Page 815: ...erence voltage cannot be selected for group A but can be selected for groups B and C The DBLANS 4 0 bits should be set while the ADST bit is 0 They should not be set simultaneously when 1 is written to the ADST bit Address es S12AD ADCSR 0008 9000h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ADST ADCS 1 0 ADIE TRGE EXTRG DBLE GBADI E DBLANS 4 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 816: ... mode A D conversion of the internal reference voltage should not be selected for group A The DBLE bit should be set after the ADST bit has been set to 0 EXTRG Bit Trigger Select The EXTRG bit selects the synchronous trigger or the asynchronous trigger as the trigger for starting A D conversion In group scan mode the setting of this bit is valid for the selected trigger of group A For groups B and...

Page 817: ...GR GRCE bit 0 When using three groups use groups A B and C ADGCTRGR GRCE bit 1 When selecting the internal reference voltage select single scan mode and deselect all the channels selected with the ADANSA0 register before performing A D conversion When A D conversion of the selected internal reference voltage is completed A D conversion is stopped The ADCS 1 0 bits should be set while the ADST bit ...

Page 818: ...tion mode has been enabled ADCSR ADCS 1 0 bits 01b and ADGSPCR PGS bit 1 do not set the ADST bit to 1 Note When group priority control operation mode has been enabled ADCSR ADCS 1 0 bits 01b and ADGSPCR PGS bit 1 and ADGSPCR GBRP 1 do not set the ADST bit to 0 When forcibly terminating A D conversion follow the procedure for clearing the ADST bit Note When the single scan continuous function is us...

Page 819: ...responds to AN007 When double trigger mode is selected the channel selected by S12AD ADCSR DBLANS 4 0 bits is selected in group A and the ANSA0n bit setting is invalid The ANSA0n bit should be set while the S12AD ADCSR ADST bit is 0 Address es 0008 9004h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ANSA0 07 ANSA0 06 ANSA0 05 ANSA0 04 ANSA0 03 ANSA0 02 ANSA0 01 ANSA0 00 Value after reset 0...

Page 820: ...sponding to group A selected with the S12AD ADANSA0 register and the S12AD ADCSR DBLANS 4 0 bits in double trigger mode should be excluded as the channels to be selected and the number of channels to be set The ANSB000 bit corresponds to AN000 and the ANSB007 bit corresponds to AN007 The ANSB0n bit should be set while the S12AD ADCSR ADST bit is 0 Address es 0008 9014h b15 b14 b13 b12 b11 b10 b9 b...

Page 821: ...ANSC0 register is used for group scan mode only not used for any other modes The ANSC000 bit corresponds to AN000 and the ANSC007 bit corresponds to AN007 The ANSC0n bit should be set while the S12AD ADCSR ADST bit is 0 Address es 0008 90D4h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ANSC0 07 ANSC0 06 ANSC0 05 ANSC0 04 ANSC0 03 ANSC0 02 ANSC0 01 ANSC0 00 Value after reset 0 0 0 0 0 0 0 ...

Page 822: ...tegration is stored in the A D data register When the S12AD ADADC AVEE bit is 1 the mean value of the results obtained by addition integration is stored in the A D data register As for the channel on which the A D conversion is performed and addition average mode is not selected a normal one time conversion is executed and the conversion result is stored to the A D data register The ADS0n bit shou...

Page 823: ... 2 0 bits should be set while the ADCSR ADST bit is 0 AVEE Bit Average Mode Enable The AVEE bit selects addition or average mode for A D conversion of the channel for which A D conversion and A D converted value addition average mode is selected including the channels selected in double trigger mode by ADCSR DBLANS 4 0 bits and internal reference voltage When average mode is selected by setting th...

Page 824: ...age specified by the ADCER DIAGVAL 1 0 bits is converted In self diagnosis voltage rotation mode the self diagnosis voltage value does not return to 0 when scan conversion is completed When scan conversion is restarted therefore rotation starts at the voltage value following the previous value If fixed mode is switched to rotation mode rotation Address es S12AD ADCER 0008 900Eh b15 b14 b13 b12 b11...

Page 825: ...ion result falls within the normal range normal or not abnormal Self diagnosis is executed once at the beginning of each scan and one of the three voltages is converted When self diagnosis is selected in group scan mode self diagnosis is separately executed in groups A B and C The DIAGM bit should be set while the ADCSR ADST bit is 0 ADRFMT Bit A D Data Register Format Select The ADRFMT bit specif...

Page 826: ...lect the trigger to start A D conversion in single scan mode and continuous scan mode In group scan mode the trigger to start scanning of the analog input selected in group A is selected When scanning is executed in group scan mode or double trigger mode set the ADCSR TRGE bit to 1 When using the A D conversion startup source of a synchronous trigger set the ADCSR TRGE bit to 1 and set the ADCSR E...

Page 827: ...0 0 1 0 1 1 TRG4ABN Compare match between MTU4 TADCORA and MTU4 TCNT and compare match between MTU4 TADCORB and MTU4 TCNT when interrupt skipping function 2 is used 0 0 1 1 0 0 Table 26 7 Selection of A D Activation Sources by the TRSA 5 0 Bits Module Source Remarks TRSA 5 TRSA 4 TRSA 3 TRSA 2 TRSA 1 TRSA 0 Trigger source deselection state 1 1 1 1 1 1 External pin ADTRG0 Trigger input pin 0 0 0 0 ...

Page 828: ...an mode The OCSA bit should be set while the ADCSR ADST bit is 0 For A D conversion of the internal reference voltage the ADDISCR ADNDIS 4 0 bits should be automatically set to 0Fh to discharge the A D converter before sampling The sampling time should be 5 μs or longer Sampling starts after discharging is completed during A D conversion of the internal reference voltage so an auto discharging per...

Page 829: ...s to 3Fh and disable trigger selection Note that the issuance period of trigger for A D conversion must be more than or equal to the actual scan conversion time tSCAN If the issuance period is less than tSCAN A D conversion by a trigger may have no effect When the trigger from the module MTU operated in PCLKB is selected as an A D conversion start trigger a delay of the period for synchronization ...

Page 830: ...dule Source Remarks TRSC 5 TRSC 4 TRSC 3 TRSC 2 TRSC 1 TRSC 0 Trigger source deselection state 1 1 1 1 1 1 MTU TRGA0N Compare match input capture from MTU0 TGRA 0 0 0 0 0 1 TRGA1N Compare match input capture from MTU1 TGRA 0 0 0 0 1 0 TRGA2N Compare match input capture from MTU2 TGRA 0 0 0 0 1 1 TRGA3N Compare match input capture from MTU3 TGRA 0 0 0 1 0 0 TRGA4N Compare match input capture from M...

Page 831: ...ble 26 9 shows the relationship between the A D sampling state register and the relevant channels For details refer to section 26 3 5 Analog Input Sampling Time and Scan Conversion Time Table 26 9 Relationship between A D Sampling State Register and Relevant Channels Note 1 When performing A D conversion of the internal reference voltage the sampling time should be 5 μs or longer Address es S12AD ...

Page 832: ... Dedicated Sample and Hold Circuit Bypass Select These bits select whether to use or not use bypass AN000 to AN002 channel dedicated sample and hold circuits The SHANS 0 bit selects AN000 SHANS 1 bit selects AN001 and SHANS 2 bit selects AN002 The SHANS 2 0 bits should be set while the ADCSR ADST bit is 0 If any channel from among AN000 to AN002 is selected for group B or C while operation is in g...

Page 833: ...ould be set when the ADCSR ADST bit is 0 When ADNDIS 3 0 are set to any value other than 0000b and the disconnection detection assist function is enabled the channel dedicated disconnection detection assist function is also enabled Be sure to secure the wait time for the sample and hold circuit when using the channel dedicated disconnection detection assist function When the ADEXICR OCSA bit is se...

Page 834: ...nd scan for group B is started When a trigger to start scanning for group A is accepted during scan for group C group C scan is discontinued and scan for group A is started Likewise when a trigger to start scanning for group A is accepted during scan for group B group B scan is discontinued and scan for group A is started When setting the PGS bit to 0 clearing should be performed by software accor...

Page 835: ...an operation on the low priority group has been stopped due to group priority operation with the LGRRS bit set to 1 the scan operation is restarted 1 on the channel on which A D conversion is not competed after the scan for the priority group is completed The LGRRS bit should be set while the ADCSR ADST bit is 0 Note 1 If A D conversion on the addition set channel is not completed for the set numb...

Page 836: ... unit 0 Address es 0008 91A0h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 P002E NAMP P002S EL1 P001E NAMP P001S EL1 P000E NAMP P000S EL1 Value after reset 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Bit Symbol Bit Name Description R W b0 Reserved This bit is read as 1 The write value should be 1 R W b1 P000SEL1 PGA P000 Amplifier Pass Through Enable 0 Does not pass through the amplifier in the PGA 1...

Page 837: ...0 P002GAIN 3 0 Bits PGA P002 Gain Setting These bits are used to set the gain of programmable gain amplifier P002 of unit 0 Address es 0008 91A2h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 P002GAIN 3 0 P001GAIN 3 0 P000GAIN 3 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b3 to b0 P000GAIN 3 0 PGA P000 Gain Setting The relationship between each s...

Page 838: ...d Double trigger mode is to be used with single scan mode or group scan mode With double trigger mode being enabled A D conversion data of a channel selected by the ADCSR DBLANS 4 0 bits is duplicated only if the conversion is started by the synchronous trigger selected by the ADSTRGR TRSA 5 0 bits In group scan mode the double trigger function can be used only for group A Extended double trigger ...

Page 839: ... is completed a scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled 4 The ADCSR ADST bit remains 1 A D conversion start during A D conversion and is automatically cleared to 0 when A D conversion of all the selected channels is completed Then the 12 bit A D converter enters a wait state Figure 26 2 Example of Operation in Single ...

Page 840: ...rresponding A D data register ADDRy 4 When A D conversion of all the selected channels is completed a scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled 5 The ADCSR ADST bit remains 1 A D conversion start during A D conversion and is automatically cleared to 0 when A D conversion of all the selected channels is completed Then th...

Page 841: ... result is stored into the corresponding A D data register ADDRy 4 When A D conversion of all the selected channels is completed a scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled 5 The ADST bit remains 1 A D conversion start during A D conversion and is automatically cleared to 0 when A D conversion of all the selected channe...

Page 842: ...n 4 Each time A D conversion of a single channel is completed the A D conversion result is stored into the corresponding A D data register ADDRy 5 When A D conversion of all the selected channels is completed a scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt upon scanning completion enabled 6 The ADCSR ADST bit remains 1 A D conversion start during A D conversion and i...

Page 843: ... D conversion by setting the ADST bit to 1 3 When A D conversion is completed the conversion result is stored into the A D internal reference voltage data register ADOCDR If the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled a scan end interrupt request is generated 4 The ADST bit remains 1 during A D conversion and is automatically cleared to 0 upon completion of A D co...

Page 844: ...it is automatically cleared to 0 and the 12 bit A D converter enters a wait state Here a scan end interrupt request is not generated irrespective of the ADCSR ADIE bit setting interrupt generation upon scanning completion enabled 4 When the ADCSR ADST bit is set to 1 A D conversion start by the second trigger input A D conversion is started on the single channel selected by the ADCSR DBLANS 4 0 bi...

Page 845: ...rsion start by TRG4AN input A D conversion is started on the single channel selected by the ADCSR DBLANS 4 0 bits 2 When A D conversion is completed the A D conversion result is stored into the corresponding A D data register ADDRy and A D data duplication register A ADDBLDRA 3 The ADCSR ADST bit is automatically cleared to 0 and the 12 bit A D converter enters a wait state Here a scan end interru...

Page 846: ...N003 Waiting for conversion ADDR3 ADDBLDR A D conversion 1 Set A D conversion time A D conversion is executed once Waiting for conversion Set A D conversion 2 A D conversion time Synchronous trigger A D conversion is executed once 0000h MTU4 TADCORA MTU4 TADCORB MTU4 TGRA MTU4 TCNT TRG4AN TRG4BN ADDBLDRB Scan end interrupt Interrupt generation ADDBLDRA 1 3 Stored Result of A D conversion 1 2 Store...

Page 847: ...ANSA0 register starting from the channel with the smallest number n 4 The ADCSR ADST bit is not automatically cleared to 0 and steps 2 and 3 are repeated as long as the bit remains 1 A D conversion start When the ADCSR ADST bit is set to 0 A D conversion stop A D conversion stops and the 12 bit A D converter enters a wait state 5 When the ADST bit is later set to 1 A D conversion start A D convers...

Page 848: ...nerated if the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled At the same time analog input sampling is started for all the channels for which the channel dedicated sample and hold circuits are to be used 5 The ADCSR ADST bit is not automatically cleared and steps 2 to 4 are repeated as long as the bit remains 1 When the ADCSR ADST bit is set to 0 A D conversion stop A D...

Page 849: ...ng completion enabled At the same time the 12 bit A D converter starts A D conversion for self diagnosis and then starts A D conversion on ANn channels selected by the ADANSA0 register starting from the channel with the smallest number n 5 The ADCSR ADST bit is not automatically cleared and steps 2 to 4 are repeated as long as the bit remains 1 When the ADST bit is set to 0 A D conversion stop A D...

Page 850: ...ted channels is completed a scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt upon scanning completion enabled At the same time analog input sampling is started for all the channels for which the channel dedicated sample and hold circuits are to be used 6 The ADCSR ADST bit is not automatically cleared and steps 2 to 5 are repeated as long as the ADCSR ADST bit remains 1...

Page 851: ...nd register ADANSC0 for group C In group scan mode the internal reference voltage A D conversion select bit S12AD ADEXICR OCSA should be set to 0 deselected When self diagnosis is selected in group scan mode self diagnosis is separately executed for groups A and B or groups A B and C The following describes operation in group scan mode using a trigger from the MTU The TRG4AN TRG4BN and TRG4ABN tri...

Page 852: ...ed in the ADSTRGR TRSA 5 0 bits as the synchronous trigger of the group A operation is in the extended double trigger mode The channels to be scanned are selected using bits ADCSR DBLANS 4 0 for group A register ADANSB0 for group B and register ADANSC0 for group C In group scan mode the internal reference voltage A D conversion select bit S12AD ADEXICR OCSA should be set to 0 deselected When doubl...

Page 853: ...ond scanning of group A is completed the conversion result is stored into ADDBLDR a scan end interrupt is generated if the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled 9 The second scanning of group B is started by the second TRGA0N trigger from the MTU 10 When the second scanning of group B is completed a group B scan interrupt is generated if the ADCSR GBADIE bit is ...

Page 854: ...ed and the converter automatically restarts scanning for the low priority group after scanning for the priority group When the ADGSPCR LGRRS bit is 0 while the ADGSPCR GBRSCN bit is 1 the converter restarts scanning for the low priority group from the head of the group When the ADGSPCR LGRRS bit is 1 the converter restarts scanning for the low priority group from the channel on which scanning is d...

Page 855: ...t the TRSA 5 0 bits and the TRSB 5 0 bits to 3Fh and 3Fh respectively Are the ADCSR ADCS 1 0 bits set to 01b group scan mode To disable trigger input set the ADSTRGR TRSA 5 0 bits to 3Fh No Yes Are the ADCSR ADCS 1 0 bits set to 10b continuous scan mode Set the ADCSR ADST bit to 0 A D conversion stop state No Yes Is the group C used ADGCTRGR GRCE 1 No Set the ADGCTRGR TRSC 5 0 bits to 3Fh Yes Yes ...

Page 856: ...for group C is discontinued and conversion for group A starts A D conversion for group C starts after conversion for group A is completed Input of trigger for group B A D conversion in progress for group C is discontinued and conversion for group B starts A D conversion in progress for group C is discontinued and conversion for group B starts A D conversion for group C starts after conversion for ...

Page 857: ...ANSC0 register after scan for groups A and B is completed 1 1 0 Group priority operation for three groups groups A B and C After group B scan is discontinued scan is restarted from the head of the channel selected with the ADANSB0 register after group A scan is completed After group C scan is discontinued scan is restarted from the channel on which scan was discontinued 1 among the channels select...

Page 858: ... operation scan for the ANn channels of group B selected in the ADANSB0 register restarts from the channel with the smallest number n while the ADCSR ADST bit remains 1 7 On completion of A D conversion on a single channel the result is stored in the corresponding A D data register ADDRy 8 A group B scan end interrupt request is generated if the ADCSR GBADIE bit is 1 interrupt generation upon grou...

Page 859: ...DDR2 ADDR3 ADDR0 Waiting for conversion Waiting for conversion Waiting for conversion A D conversion B1 A D conversion A1 Waiting for conversion Waiting for conversion A D conversion B3 Waiting for conversion Waiting for conversion A D conversion B5 A D conversion B6 A D conversion result B1 A D conversion result B4 A D conversion result A1 A D conversion result B6 Waiting for conversion A D conve...

Page 860: ...A trigger is input during scan for group B group A scan starts as in example 1 and group B scan starts after group A scan is completed 6 On completion of A D conversion on a single channel the result is stored in the corresponding A D data register ADDRy 7 After scan for group B is completed a group B scan end interrupt request is generated if the ADCSR GBADIE bit is 1 interrupt generation upon gr...

Page 861: ... A D conversion on a single channel the result is stored in the corresponding A D data register ADDRy 5 After scan for group A is completed a scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled 6 The ADST bit is automatically cleared to 0 when scan for group A is completed and the 12 bit A D converter enters a wait state Scan for...

Page 862: ...of A D conversion on a single channel the result is stored in the corresponding A D data register ADDRy 5 After scan for group A is completed a scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt generation upon scanning completion enabled 6 If the ADGSPCR GBRP bit is set to 1 single scan is continuously operated scan for the ANn channels of group B selected in the ADANSB0...

Page 863: ...t Waiting for conversion Waiting for conversion Waiting for conversion A D conversion B1 A D conversion B2 A D conversion A1 Waiting for conversion Waiting for conversion A D conversion B3 Waiting for conversion Waiting for conversion A D conversion B4 Result of A D conversion B1 Result of A D conversion B3 Result of A D conversion A1 Waiting for conversion Result of A D conversion B4 Scan Started...

Page 864: ...the channel with the smallest number n If A D conversion is not completed when scan was discontinued the result is not stored in the corresponding A D data register ADDRy 6 On completion of A D conversion on a single channel the result is stored in the corresponding A D data register ADDRy 7 A scan end interrupt request is generated if the ADCSR ADIE bit is 1 interrupt generation upon scanning com...

Page 865: ... B1 Result of A D conversion A1 Result of A D conversion C1 Waiting for conversion Result of A D conversion B3 Scan Started Stored Stored Stored Waiting for conversion Waiting for conversion A D conversion C1 A D conversion C2 Waiting for conversion Waiting for conversion A D conversion C3 Waiting for conversion ADDR4 Result of A D conversion C3 A D conversion B2 Waiting for conversion Stored Grou...

Page 866: ... 11 ADDR1 ADDR2 ADDR3 ADDR0 1 Group C scanned Group A scanned Group priority operation Group B rescanned ADST bit Waiting for conversion A D conversion A1 Waiting for conversion Waiting for conversion A D conversion B1 Waiting for conversion Waiting for conversion B3 Result of A D conversion B1 Result of A D conversion A1 Result of A D conversion C1 Waiting for conversion Result of A D conversion ...

Page 867: ...GRRS bit is set to 1 at this time scan for group B starts from the channel on which A D conversion was discontinued When a group A trigger is input during scan for group B group A scan starts as in example 1 and group B scan starts after group A scan is completed 6 If a group C trigger is input during scan for group B scan for group C can be started 7 On completion of A D conversion on a single ch...

Page 868: ...DRy 4 On completion of A D conversion on a single channel the result is stored in the corresponding A D data register ADDRy 5 If a group A trigger is input during scan for group B group B scan is discontinued while the ADCSR ADST bit remains 1 and scan for the ANn channels of group A selected in the ADANSB0 register starts from the channel with the smallest number n If A D conversion is not comple...

Page 869: ...on A D conversion A1 Waiting for conversion Waiting for conversion A D conversion B1 Waiting for conversion Waiting for conversion Result of A D conversion B1 Result of A D conversion A1 Result of A D conversion C1 Waiting for conversion Waiting for conversion A D conversion C1 A D conversion C2 Waiting for conversion Waiting for conversion ADDR4 A D conversion B2 Waiting for conversion Trigger fo...

Page 870: ... enabled 7 If the ADGSPCR GBRSCN bit is 1 scan for the group is restarted after having been discontinued due to group priority operation scan for the ANn channels of group B selected in the ADANSB0 register restarts from the channel with the smallest number n while the ADCSR ADST bit remains 1 If the ADGSPCR LGRRS bit is set to 1 at this time scan for group B starts from the channel on which A D c...

Page 871: ...onversion Result of A D conversion C1 Result of A D conversion A1 Result of A D conversion C3 Scan Started GBRP bit Group B rescanned A D conversion C3 A D conversion C4 Group C rescanned GBRP 1 Result of A D conversion C4 3 Waiting for conversion A D conversion B1 Waiting for conversion ADDR1 Result of A D conversion B2 A D conversion B2 Waiting for conversion Group A scanned Group priority opera...

Page 872: ...ersion clock ADCLK is slow sampling time can be adjusted using the ADSSTR register The time for conversion by successive approximation tSAM is at 32 ADCLK states Table 26 13 shows the scan conversion time The scan conversion time tSCAN in single scan mode for which the number of selected channels is n can be determined as follows tSCAN tD tSPLSH tDIS n tDIAG tCONV n 5 tED The scan conversion time ...

Page 873: ...self diagnosis is to be started 2 PCLKB 6 ADCLK 4 PCLKB 6 ADCLK 6 ADCLK Other than above 2 PCLKB 4 ADCLK 2 PCLKB 4 ADCLK 4 ADCLK Channel dedicated sample and hold processing time 1 Sampling time tSPLSH tSH The setting of ADSHCR SSTSH 7 0 initial value 1Ah ADCLK Wait time between sampling and A D conversion tW 13 ADCLK Disconnection detection assistance processing time tDIS The setting of ADNDIS 3 ...

Page 874: ...9 RX13T Group 26 12 Bit A D Converter S12ADF Figure 26 27 Scan Conversion Timing Activated by Asynchronous Trigger tDIAG tSCAN tCONV tED DIAG conversion A D conversion End processing Asynchronous trigger tD Waiting ADST bit A D converter tSPLSH Sampling ...

Page 875: ...ng that the read data value is 0000h 26 3 7 A D Converted Value Addition Average Mode In A D converted value addition mode the same channel is A D converted 2 3 4 or 16 consecutive times and the sum of the converted values is stored in the data register In A D converted value average mode the same channel is A D converted two or four consecutive times and the mean of the converted values is stored...

Page 876: ...ance Example of the external circuit 1 Precharge Note 1 The converted result should be used after fully evaluated because the result data when disconnection occurs varies depending on the external circuit Unit 0 AVCC0 R 1 MΩ Precharge control signal Discharge control signal Analog input ANn OFF ON Disconnection Sampling capacitance Example of the external circuit 1 Discharge Note 1 The converted r...

Page 877: ... D Conversion with Synchronous Trigger from Peripheral Module The A D conversion can be started by a synchronous trigger To start the A D conversion by a synchronous trigger the ADCSR TRGE bit should be set to 1 the ADCSR EXTRG bit should be cleared to 0 and the relevant sources should be selected by the ADSTRGR TRSA 5 0 and ADSTRGR TRSB 5 0 bits 26 3 11 Programmable Gain Amplifier A programmable ...

Page 878: ...speed conversion of 1 4 μs the analog input pins of this MCU are designed so that the conversion accuracy is guaranteed if the impedance of the input signal source is 1 0 kΩ or less If an external capacitor of large capacitance is attached in the application in which only a single pin input is converted in single scan mode the only load on input is virtually 2 5 kΩ of the internal input resistor t...

Page 879: ...he data registers should never be read in 8 bit units 26 6 2 Notes on Stopping A D Conversion To stop A D conversion when an asynchronous trigger or a synchronous trigger has been selected as the condition for starting A D conversion follow the procedure in Figure 26 33 Figure 26 33 Procedure for Clear Operation by Software through the ADCSR ADST Bit To disable trigger inputs set the ADSTRGR regis...

Page 880: ...stop state or software standby mode make sure to stop A D conversion Here set the ADCSR ADST bit to 0 and secure certain period of time until the analog unit of the 12 bit A D converter is stopped Follow the procedure given below to secure this time Set the ADCSR ADST bit to 0 by following the procedure in Figure 26 33 Procedure for Clear Operation by Software through the ADCSR ADST Bit Then wait ...

Page 881: ...on is satisfied at the supply side AVSS0 VSS When the 12 bit A D converter is not used the following conditions should be satisfied AVCC0 VCC and AVSS0 VSS Figure 26 34 Power Supply Pin Connection Example 26 6 10 Notes on Board Design The board should be designed so that digital circuits and analog circuits are separated from each other as far as possible In addition digital circuit signal lines a...

Page 882: ... by abnormal voltage such as excessive surge a capacitor should be inserted between AVCC0 and AVSS0 and a protection circuit should be connected to protect the above analog input pins as shown Figure 26 35 Figure 26 35 Sample Protection Circuit for Analog Inputs 10µF 0 01µF Note 1 The values shown here are reference values Note 2 Rin Signal source impedance 0 1µF Rin 2 1 AVCC0 AN000 to AN007 AVSS0...

Page 883: ...cifications of the 8 bit D A converter and Figure 27 1 shows a block diagram of the 8 bit D A converter Figure 27 1 Block Diagram of 8 Bit D A Converter Table 27 1 Specifications of 8 Bit D A Converter Item Specifications Resolution 8 bits Output channels One channel Low power consumption function Module stop state can be set Control circuit Bus interface DADR0 DADPR DACR Module data bus VCC Vref ...

Page 884: ...utput is enabled the values in DADR0 are converted and the reference voltage for comparator C is supplied 8 bit data can be relocated by setting the DADPR DPSEL bit Bits are read as 0 The write value should be 0 Address es DA DADR0 0008 80C0h DADPR DPSEL bit 0 data is right justified b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADPR DPSEL...

Page 885: ...e value should be 1 R W b5 Reserved This bit is read as 0 The write value should be 0 R b6 DAOE0 D A Output Enable 0 0 D A conversion is disabled 1 D A conversion is enabled R W b7 Reserved This bit is read as 0 The write value should be 0 R DAOE0 Bit D A Output Enable 0 The DAOE0 bit controls the D A conversion Address es DA DADPR 0008 80C5h b7 b6 b5 b4 b3 b2 b1 b0 DPSEL Value after reset 0 0 0 0...

Page 886: ...he DA0 output voltage is held at this level until the DADR0 register is updated or the DAOE0 bit is set to 0 The output voltage reference is expressed by the following formula 3 When the DADR0 register is updated the conversion starts The DA0 output settles at the new output voltage after the conversion time tDCONV has elapsed 4 When the DAOE0 bit is set to 0 D A conversion is disabled Figure 27 2...

Page 887: ... current has to be reduced in the module stop state disable D A conversion by setting the DACR and DAOE0 bit to 0 27 4 3 Operation of the D A Converter in Software Standby Mode When the MCU enters software standby mode with D A conversion enabled the D A converter outputs are retained and the analog power supply current is the same as during D A conversion If the analog power supply current has to...

Page 888: ...of comparator C Figure 28 1 shows a block diagram of comparator C Table 28 2 shows a comparator C pin configuration and Table 28 3 shows the analog input pin connections for comparator C Item Specification Number of channels Three comparator C0 to comparator C2 Analog input voltages Input voltage from the CMPCnm pin n channel number m 0 to 3 Reference input voltage Input voltage from the CVREFC0 p...

Page 889: ...gnal to POE COMP1 level detection signal to POE COMP2 level detection signal to POE 0 1 Edge detector CEG 1 0 Comparator C1 HCMPON CINV COE CPOE CMPMON0 CVRS 1 0 CMPSEL0 CMPCTL CMPMON Noise filter same value sampled 3 times CMPSEL 3 0 CMPSEL1 CDFS 1 0 CMPIOC 0 1 Edge detector CEG 1 0 Comparator C2 HCMPON CINV COE CPOE CMPMON0 CVRS 1 0 CMPSEL0 CMPCTL CMPMON Noise filter same value sampled 3 times C...

Page 890: ...t voltage pin 0 COMP0 Output Comparator C0 comparison result output pin COMP1 Output Comparator C1 comparison result output pin COMP2 Output Comparator C2 comparison result output pin Table 28 3 Analog Input Pin Connections for Comparator C Analog Input Pin Connection CMPC00 AN000 pin CMPC01 Programmable gain amplifier output for AN000 pin CMPC02 AN003 pin CMPC03 AN006 pin CMPC10 AN001 pin CMPC11 ...

Page 891: ...or Edge Interrupt Detection Select These bits select which edge of comparator output signal is used to generate an interrupt request The valid edge is set for the signal after the comparator polarity is selected by the CINV bit and the filter is selected by CDFS 1 0 bits Address es CMPC0 CMPCTL 000A 0C80h CMPC1 CMPCTL 000A 0CA0h CMPC2 CMPCTL 000A 0CC0h b7 b6 b5 b4 b3 b2 b1 b0 HCMP ON CDFS 1 0 CEG ...

Page 892: ...nding interrupt status flag IR in the interrupt request register to 0 Address es CMPC0 CMPSEL0 000A 0C84h CMPC1 CMPSEL0 000A 0CA4h CMPC2 CMPSEL0 000A 0CC4h b7 b6 b5 b4 b3 b2 b1 b0 CMPSEL 3 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b3 to b0 CMPSEL 3 0 Comparator Input Select 1 Comparator C0 b3 b0 0 0 0 0 No input 0 0 0 1 CMPC00 selected 0 0 1 0 CMPC01 selected 0 1 0 0 ...

Page 893: ...e CMPCTL COE bit to 0 2 Set the CVRS 1 0 bits to 00b 3 Set a new value to the CVRS 1 0 bits with 1 set in only one of the bits 4 Wait for the stabilization time for input selection As for the value refer to section 32 Electrical Characteristics 5 Set the CMPCTL COE bit to 1 6 Set the corresponding interrupt status flag IR in the interrupt request register to 0 Address es CMPC0 CMPSEL1 000A 0C88h C...

Page 894: ...fter reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 CMPMON0 Comparator Output Monitor Flag 1 0 Comparator output is 0 1 Comparator output is 1 R b7 to b1 Reserved These bits are read as 0 The write value should be 0 R W Address es CMPC0 CMPIOC 000A 0C90h CMPC1 CMPIOC 000A 0CB0h CMPC2 CMPIOC 000A 0CD0h b7 b6 b5 b4 b3 b2 b1 b0 CPOE Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name ...

Page 895: ...C register is 1 the COMPn level detection signal is output from the COMPn pin Interrupt request is output in response to changes in the comparator output Figure 28 2 Comparator Operation Example Reference input voltage COMPn output 1 0 Analog input voltage V After COMPn output an interrupt request is generated with a delay of 2 or 3 operating clocks High Low A B B A n 0 to 2 Note The above diagram...

Page 896: ...etector Configuration Figure 28 4 Noise Filter and Interrupt Operation Example CEG 1 0 Edge detector COMPn CINV CPOE CMPMON0 Comparator output Sampling clock Noise filter same value sampled 3 times CDFS 1 0 0 1 n 0 to 2 COMPn level detection signal CMPCn interrupt request Noise filter input Sampling timing Interrupt status flag IR Unless the same value is sampled 3 consecutive times it is assumed ...

Page 897: ...nable the edge for interrupt detection set the CMPCTL CEG 1 0 bits to a value other than 00b 5 Enable input of the comparator set the CMPCTL HCMPON bit to 1 and wait for the time until the comparator operation is stabilized As for the value refer to section 32 Electrical Characteristics 6 Enable output of the comparator set the CMPCTL COE bit to 1 28 3 4 Comparator Pin Output The comparison result...

Page 898: ...nce Voltage DA Set comparator input Set comparator reference voltage Set comparator control set bits CDFS 1 0 CINV and CEG 1 0 Enable comparator operation after enabling comparator operation stabilization wait time is required As for the value refer to section 32 Electrical Characteristics Enable comparator output Set COMPn pin for comparator output 2 Refer to section 28 3 4 Comparator Pin Output ...

Page 899: ...omparator C is being used If the analog power supply current needs to be reduced in software standby mode set the CMPCTL HCMPON bit to 0 to stop comparator C 28 4 4 Comparator Operation while the 12 Bit A D Convertor is in the Module Stop State The same module stop signal controls the programmable gain amplifiers PGAs and the 12 bit A D convertor The comparison of PGA output for the following pins...

Page 900: ...gure 29 1 DOC Block Diagram Table 29 1 DOC Specifications Item Description Data operation function 16 bit data comparison addition and subtraction Lower power consumption function Module stop state can be set Interrupts An interrupt occurs at the following timings The compared values either match or mismatch The result of data addition is greater than FFFFh The result of data subtraction is less t...

Page 901: ...Clearing condition Writing 1 to the DOPCFCL bit DOPCFCL Bit DOPCF Clear Setting this bit to 1 clears the DOPCF flag This bit is read as 0 Address es 0008 B080h b7 b6 b5 b4 b3 b2 b1 b0 DOPCF CL DOPCF DOPCI E DCSEL OMS 1 0 Value after reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b1 b0 OMS 1 0 Operating Mode Select b1 b0 0 0 Data comparison mode 0 1 Data addition mode 1 0 Data subtractio...

Page 902: ...R DODSR is a 16 bit readable writable register This register stores 16 bit data for use as a reference in data comparison mode This register also stores the results of operations in data addition and data subtraction modes Address es 0008 B082h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address es 0008 B084h b15 b14 b13 b12 b11 b10 b9 b8...

Page 903: ...ects data comparison mode 2 The 16 bit reference data is set in DODSR 3 16 bit data for comparison is written to DODIR 4 Writing of 16 bit data continues until all data for comparison have been written to DODIR 5 If a value written to DODIR does not match that in DODSR 1 the DOCR DOPCF flag is set to 1 When the DOCR DOPCIE bit is 1 a data operation circuit interrupt is also generated Note 1 When D...

Page 904: ... bit data to be added is written to DODIR The result of the operation is stored in DODSR 4 Writing of 16 bit data continues until all data for addition have been written to DODIR 5 If the result of an operation is greater than FFFFh the DOCR DOPCF flag is set to 1 When the DOCR DOPCIE bit is 1 a data operation circuit interrupt is also generated Figure 29 3 Example of Operation in Data Addition Mo...

Page 905: ...s the data operation circuit interrupt as an interrupt request When an interrupt source is generated the data operation circuit flag corresponding to the interrupt is set to 1 Table 29 2 describes the interrupt request 29 5 Usage Note 29 5 1 Module Stop Function Setting Operation of the data operation circuit can be disabled or enabled using module stop control register B MSTPCRB The initial setti...

Page 906: ...MSTPCRC MSTPC0 bit to 1 stops supply of the clock signal to RAM0 Stopping supply of the clock signal places the RAM0 in the module stop state The RAM operates after initialization by a reset The RAM is not accessible in the module stop state Do not allow transitions to the module stop state while access to RAM is in progress For details on the MSTPCRC register see section 11 Low Power Consumption ...

Page 907: ...e after erasure ROM FFh E2 DataFlash FFh Interrupt An interrupt FRDYI is generated upon completion of software command processing or forced stop processing On board programming Boot mode SCI Interface 1 Channel 1 of the serial communications interface SCI1 is used for asynchronous serial communication The user area and data area are rewritable Boot mode FINE interface 1 The FINE is used The user a...

Page 908: ...s erased by the block Figure 31 1 shows the ROM Area and Block Configuration Figure 31 1 ROM Area and Block Configuration Table 31 2 Correspondence Between ROM Capacity and Addresses for Reading ROM Capacity Addresses for Reading 128 Kbytes FFFE 0000h to FFFF FFFFh 64 Kbytes FFFF 0000h to FFFF FFFFh 6 0000h 7 FFFFh 64 Kbytes 128 Kbytes 7 0000h 127 User area block number 1 block 1 Kbyte Address for...

Page 909: ...U The E2 DataFlash is divided into blocks and erased in block units Figure 31 2 shows the E2 DataFlash Area and Block Configuration Figure 31 2 E2 DataFlash Area and Block Configuration 0010 0000h DB0001 Data area 1 block 1 Kbyte DB0002 0010 0FFFh 4 Kbytes Address for reading DB0000 DB0003 Address for E2 DataFlash programming erasure F 1000h F 1400h F 1800h F 1C00h F 1FFFh ...

Page 910: ...r the E2 DataFlash STOP recovery time tDSTOP to elapse before reading the E2 DataFlash and entering E2 DataFlash P E mode Do not read the E2 DataFlash or enter E2 DataFlash P E mode until tDSTOP has elapsed Refer to section 31 7 1 Sequencer Modes for details on E2 DataFlash P E mode Refer to section 32 Electrical Characteristics for E2 DataFlash STOP recovery time tDSTOP Address es FLASH DFLCTL 00...

Page 911: ...aFlash can be rewritten by a program in the ROM Clearing condition AA00h is written to the FENTRYR register FENTRYD Bit E2 DataFlash P E Mode Entry This bit is used to place the E2 DataFlash in P E mode Setting condition AA80h is written to the FENTRYR register when the FENTRYR register is 0000h Clearing condition AA00h is written to the FENTRYR register Address es FLASH FENTRYR 007F FFB2h b15 b14...

Page 912: ... flag is set to 1 31 4 4 Protection Unlock Status Register FPSR PERR Flag Protect Error Flag When the FPMCR register is not accessed as described in the procedure to unlock protection data is not written to the register and this flag is set to 1 Setting condition The FPMCR register is not accessed as described in the procedure to unlock protection Clearing condition The FPMCR register is accessed ...

Page 913: ... tDIS refer to section 32 Electrical Characteristics Set the FMS2 bit 0 the FMS1 bit 1 the FMS0 bit 1 and the RPDIS bit 0 Set the FMS2 bit 0 the FMS1 bit 0 the FMS0 bit 0 and the RPDIS bit 1 Wait for ROM mode transition wait time 2 tMS refer to section 32 Electrical Characteristics Transition from read mode to E2 DataFlash P E mode Set the FMS2 bit 0 the FMS1 bit 1 the FMS0 bit 0 and the RPDIS bit...

Page 914: ...uency during programming erasure of the ROM E2 DataFlash When FCLK is higher than 4 MHz Set a rounded up value for a non integer frequency For example set 32 MHz PCKA 4 0 bits 11111b when the frequency is 31 5 MHz When FCLK is 4 MH or lower Do not use a non integer frequency Use the FCLK at a frequency of 1 2 3 or 4 MHz Note When the PCKA 4 0 bits are set to a frequency different from the FCLK the...

Page 915: ...area When a reset is generated after this the area is selected according to the start up area settings of the extra area 3 When switching the start up area to the alternative area temporarily When 11b is written to the SAS 1 0 bits the start up area is switched to the alternative area regardless of the start up area settings of the extra area When a reset is generated after this the area is select...

Page 916: ...rea Select Set this bit to 1 before issuing a software command unique ID read start up area information program or access window information program for the extra area Set this bit to 0 before issuing a software command program blank check or block erase for the user area After issuing a software command do not change the value until changing it for issuing the next software command Address es FLA...

Page 917: ...s erased Block erase Erase consecutive areas specified in the flash memory by the blocks Set the beginning address of the block in registers FSARH and FSARL and the end address in registers FEARH and FEARL Unique ID read When executing the unique ID read after setting registers FSARH FSARL FEARH and FEARL to 00h 0850h 00h and 086Fh respectively the unique ID is stored in registers FRBH and FRBL se...

Page 918: ...xt data is read STOP Bit Forced Processing Stop This bit is used to forcibly stop the processing blank check or block erase being executed After setting this bit to 1 wait until the FSTATR1 FRDY flag is 1 processing completed before setting the OPST bit to 0 OPST Bit Processing Start This bit is used to execute the command set in the CMD 2 0 bits This bit is not set to 0 again even when the proces...

Page 919: ...information program Access window information program This command is used to set the access window used for area protection Set the access window in block units Specify the access window start address which is the beginning address of the access window in the FWBL register specify the access window end address which is the next address of the last address of the access window in the FWBH register...

Page 920: ...gure 31 1 and Figure 31 2 for details on the addresses of the flash memory 31 4 12 Flash Processing Start Address Register L FSARL The FSARL register is used to set the target processing address or the start address of the target processing range in the flash memory when a software command is executed Set bit 15 to bit 0 of the flash memory address for programming erasure in this register When the...

Page 921: ...lash memory 31 4 14 Flash Processing End Address Register L FEARL The FEARH register is used to set the end address of the target range for processing when a software command is executed Set bit 15 to bit 0 of the flash memory address for programming erasure in this register When the target is the ROM set bit 1 and bit 0 to 00b Data can be written to this register in ROM P E mode or E2 DataFlash P...

Page 922: ...P E mode This register is initialized by a reset or setting the FRESETR FRESET bit to 1 Data cannot be written to this register while the FRESETR FRESET bit is 1 The value read from this register is undefined while a software command is being executed If this register is read while executing a software command set by the FEXCR register an undefined value is read Address es FLASH FRBH 007F C0C4h b1...

Page 923: ... mode or E2 DataFlash P E mode This register is initialized by a reset or setting the FRESETR FRESET bit to 1 Data cannot be written to this register while the FRESETR FRESET bit is 1 If this register is read while executing a software command set by the FEXCR register an undefined value is read Address es FLASH FWBL 007F FF8Ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after rese...

Page 924: ...Blank Check Error Flag This flag indicates the result of the blank check processing for the ROM E2 DataFlash Setting condition An error occurs during blank checking Address es FLASH FSTATR0 007F FF8Ah b7 b6 b5 b4 b3 b2 b1 b0 EILGLE RR ILGLER R BCERR PRGER R ERERR Value after reset x 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b0 ERERR Erase Error Flag 0 Erasure terminates normally 1 An error...

Page 925: ... the set value of registers FEARH and FEARL Program and block erase commands are executed when the FASR EXS bit is 1 The E2 DataFlash address is set in registers FSARH and FSARL and a software command is executed when the ROM is in P E mode The ROM address is set in registers FSARH and FSARL and a software command is executed when the E2 DataFlash is in P E mode The ROM and E2 DataFlash are set to...

Page 926: ...when processing of the executed software command or the forced stop processing is completed and this flag becomes 0 when setting the FCR OPST bit to 0 Also an interrupt FRDYI is generated when this flag becomes 1 EXRDY Flag Extra Area Ready Flag This flag is used to confirm whether a software command for the extra area is executed This flag is set to 1 when processing of the executed software comm...

Page 927: ...ddress Monitor Register L FEAML This register is used to check the address where the error has occurred if an error occurs during processing of a software command This register stores bit 15 to bit 0 of the address where the error has occurred for the program command or blank check command or it stores bit 15 to bit 0 of the beginning address of the area where the error has occurred for the block ...

Page 928: ...he same value set in bit 9 to bit 0 the FWBL register after the access window information program command is executed This register is used to confirm the set value of the access window start address used for area protection Address es FLASH FSCMR 007F C0B0h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SASMF Value after reset 0 1 1 1 1 1 1 Value set by user 1 0 0 0 0 0 0 0 0 Bit Symbol Bi...

Page 929: ...ress used for area protection 31 4 26 Unique ID Register n UIDRn n 0 to 31 The UIDRn register stores a 32 byte ID code unique ID for identifying the individual MCU The unique ID is stored in the extra area of the flash memory and cannot be rewritten by the user Use the unique ID read command to read the register value Address es FLASH FAWEMR 007F C0B4h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 ...

Page 930: ... 1 Program to perform operation to start the user program It includes the fixed vector table Figure 31 3 Overview of the Start Up Program Protection FFFE 0000h User program Before rewriting No program alternate area Original start up program default area FFFF 8000h FFFF C000h FFFF FFFFh User program New start up program alternate area Original start up program default area User program New start u...

Page 931: ...ly during self programming in single chip mode Figure 31 4 shows the Area Protection Overview When Blocks 4 to 6 are Set as the Access Window in Products with 128 Kbyte ROM Figure 31 4 Area Protection Overview When Blocks 4 to 6 are Set as the Access Window in Products with 128 Kbyte ROM Block 4 Block 3 Block 2 Block 1 Block 0 Block 6 Block 5 Access window Enabled Disabled Disabled Address for rea...

Page 932: ... E2 DataFlash access disabled mode access to the E2 DataFlash is disabled After a reset the sequencer enters this mode When setting the DFLCTL DFLEN bit to 1 the E2 DataFlash is placed in read mode FRNTRYR register AA01h FPMCR register 82h C2h 1 FRNTRYR register AA00h FPMCR register 08h 1 Reset FRNTRYR register AA80h FPMCR register 10h 50h 1 FRNTRYR register AA00h FPMCR register 08h 1 DFLCTL DFLEN...

Page 933: ...register 82h or C2h 2 E2 DataFlash P E Mode In this mode the ROM is in read mode and the E2 DataFlash is in P E mode The sequencer enters this mode when the setting the FENTRYR FENTRYD to 1 setting the FENTRYR FENTRY0 bit to 0 and setting the FPMCR register 10h or 50h 31 7 2 Mode Transitions 31 7 2 1 Transition from E2 DataFlash Access Disable Mode to Read Mode Reading of the E2 DataFlash requires...

Page 934: ... bits 000b Set ROM P E mode FPR register A5h FPMCR register 12h FPMCR register EDh FPMCR register 12h High speed operating mode No FPR register A5h FPMCR register 92h FPMCR register 6Dh FPMCR register 92h FPR register A5h FPMCR register D2h FPMCR register 2Dh FPMCR register D2h FPR register A5h FPMCR register 82h FPMCR register 7Dh FPMCR register 82h FPR register A5h FPMCR register C2h FPMCR regis...

Page 935: ...n E2 DataFlash P E mode No OPCCR OPCM 2 0 bits 000b Set E2 DataFlash P E mode High speed operating mode Middle speed operating mode Set the FCLK frequency in the FISR PCKA 4 0 bits Set 10h in the FPMCR register FPR register A5h FPMCR register 10h FPMCR register EFh FPMCR register 10h FPR register A5h FPMCR register 50h FPMCR register AFh FPMCR register 50h Set 50h in the FPMCR register Note 1 The ...

Page 936: ...E Mode to ROM E2 DataFlash Read Mode Start in ROM P E mode FENTRYR register AA00h FPR register A5h FPMCR register 92h FPMCR register 6Dh FPMCR register 92h FPR register A5h FPMCR register 08h FPMCR register F7h FPMCR register 08h FPR register A5h FPMCR register 12h FPMCR register EDh FPMCR register 12h Note 1 tDIS ROM mode transition wait time 1 Refer to the Electrical Characteristics chapter tMS ...

Page 937: ...o ROM E2 DataFlash Read Mode Start in E2 DataFlash P E mode FENTRYR register AA00h End in ROM E2 DataFlash read mode FENTRYR register 0000h Yes No FPR register A5h FPMCR register 08h FPMCR register F7h FPMCR register 08h Set 08h in the FPMCR register Wait for tMS 1 Note 1 tMS ROM mode transition wait time 2 Refer to the Electrical Characteristics chapter ...

Page 938: ...Software Commands Command Function Program ROM programming 4 bytes E2 DataFlash programming 1 byte Block erase ROM E2 DataFlash erasure Blank check Check whether the specified area is blank Confirm that data is not programmed in the area This command does not guarantee whether the area remains erased Start up area information program Rewrite the start up area switching information used for start u...

Page 939: ...ram command Figure 31 11 Procedure to Issue the Program Command for the ROM Set programming address in registers FSARH and FSARL Yes Set programming data in registers FWBH and FWBL FCR register 81h FCR register 00h FSTATR1 FRDY flag 1 End in ROM P E mode No FSTATR1 FRDY flag 0 Yes No Continue ROM programming Yes No FSTATR0 ILGLERR flag 1 or FSTATR0 PRGERR flag 1 Yes FRESETR FRESET bit 1 FRESETR FR...

Page 940: ...registers FSARH and FSARL Yes Set programming data in FWBL register FCR register 81h FCR register 00h FSTATR1 FRDY flag 1 End in E2 DataFlash P E mode No FSTATR1 FRDY flag 0 Yes No Yes No Yes No FSTATR0 ILGLERR flag 1 or FSTATR0 PRGERR flag 1 FRESETR FRESET bit 1 FRESETR FRESET bit 0 Sequencer initialization Continue E2 DataFlash programming FASR EXS bit 0 Start in E2 DataFlash P E mode ...

Page 941: ...r the ROM Set the beginning address of the erasure block in registers FSARH and FSARL Yes FCR register 84h FCR register 00h FSTATR1 FRDY flag 1 End in ROM P E mode No FSTATR1 FRDY flag 0 Yes No Continue ROM erasure Yes No Yes No Set the last address of the erasure block in registers FEARH and FEARL FSTATR0 ILGLERR flag 1 or FSTATR0 ERERR flag 1 FRESETR FRESET bit 1 FRESETR FRESET bit 0 Sequencer i...

Page 942: ...registers FSARH and FSARL Yes FCR register 84h FCR register 00h FSTATR1 FRDY flag 1 End in E2 DataFlash P E mode No FSTATR1 FRDY flag 0 Yes No Continue E2 DataFlash erasure Yes No Yes No Set the last address of the erasure block in registers FEARH and FEARL FSTATR0 ILGLERR flag 1 or FSTATR0 ERERR flag 1 FRESETR FRESET bit 1 FRESETR FRESET bit 0 Sequencer initialization FASR EXS bit 0 Start in E2 D...

Page 943: ...the Blank Check Command for the ROM Set the blank check start address in registers FSARH and FSARL Set the blank check end address in registers FEARH and FEARL FCR register 83h FSTATR1 FRDY flag 1 No Yes FCR register 00h FSTATR1 FRDY flag 0 No Yes FSTATR0 ILGLERR flag 1 or FSTATR0 BCERR flag 1 Yes No FRESETR FRESET bit 1 FRESETR FRESET bit 0 End in ROM P E mode Sequencer initialization FASR EXS bi...

Page 944: ...start address in registers FSARH and FSARL Set blank check end address in registers FEARH and FEARL FCR register 83h FSTATR1 FRDY flag 1 No Yes FCR register 00h FSTATR1 FRDY flag 0 No Yes FSTATR0 ILGLERR flag 1 or FSTATR0 BCERR flag 1 Yes No FRESETR FRESET bit 1 FRESETR FRESET bit 0 End in E2 DataFlash P E mode Sequencer initialization FASR EXS bit 0 Start in E2 DataFlash P E mode ...

Page 945: ... E2 DataFlash access disabled mode set the DFLCTL DFLEN bit to 1 at the beginning of the procedure Figure 31 17 Procedure to Issue the Start Up Area Information Program Command Access Window Information Program Command Start in ROM P E mode Write 81h or 82h to FEXCR register FEXCR register 00h FSTATR1 EXRDY flag 1 End in ROM P E mode No FSTATR1 EXRDY flag 0 Yes No FASR EXS bit 1 FSTATR0 EILGLERR f...

Page 946: ...d registers FRBH and FRBL Read 4 bytes of unique ID FCR register 95h FCR DRC bit 1 FSTATR1 DRRDY flag 0 No Yes FCR register 85h FCR DRC bit 0 FSTATR1 DRRDY flag 1 or FSTATR1 FRDY flag 1 Yes No FSTATR1 DRRDY flag 1 No Yes FCR register 00h FSTATR1 FRDY flag 0 No Yes End in ROM P E mode Wait until an illegal command error occurs or the state becomes ready for data read End if an illegal command error...

Page 947: ...AMH and FEAML register values to registers FSARH and FSARL Figure 31 19 Procedure for Forced Stop of Software Commands 31 7 5 Interrupt When software command processing or forced stop processing is completed an interrupt FRDYI is generated When the FSTATR1 FRDY flag becomes 0 by setting the FCR OPST bit to 0 and the FSTATR1 EXRDY flag becomes 0 by setting the FEXCR OPST bit to 0 the next interrupt...

Page 948: ... Table 31 5 Programmable and Erasable Areas and Peripheral Modules Used in Boot Mode Item Boot Mode SCI Interface FINE Interface Programmable and erasable areas User area Data area User area Data area Peripheral module SCI1 asynchronous serial communication FINE Table 31 6 I O Pins Used in Boot Mode Pin Name I O Mode Description MD Input Boot mode Select operating mode refer to section 3 Operating...

Page 949: ...nterface Table 31 7 lists Pin Handling in Boot Mode SCI Interface An example of pin connections shown in Figure 31 20 is a simplified circuit Operations are not guaranteed in all systems Figure 31 20 Example of Pin Connections in Boot Mode SCI Interface Table 31 7 Pin Handling in Boot Mode SCI Interface Pin Name Name I O Function VCC VSS Power supply Input 2 7 V or higher to the VCC pin Input 0 V ...

Page 950: ...rface a reset must be released by changing the RES pin from low to high while the MD pin is low After starting up in boot mode SCI interface wait at least 400 ms until communication with the MCU is enabled in boot mode SCI interface As shown in Figure 31 22 keep the signal of each pin unchanged for 400 ms after the reset is released Use resets according to the range described in section 32 4 2 Res...

Page 951: ...31 9 lists Pin Handling in Boot Mode FINE Interface An example of pin connections shown in Figure 31 23 is a simplified circuit Operations are not guaranteed in all systems Figure 31 23 Example of Pin Connections in Boot Mode FINE Interface Table 31 9 Pin Handling in Boot Mode FINE Interface Pin Name Name I O Function VCC VSS Power supply Input 2 7 V or higher to the VCC pin Input 0 V to the VSS p...

Page 952: ...nsist of the control code and ID code 1 to ID code 15 Set ID codes to four 32 bit data in 32 bit units Figure 31 24 shows the ID Code Configuration Figure 31 24 ID Code Configuration The following shows a program example for setting ID codes This is an example when setting the control code to 45h and setting ID codes to 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh and 0Fh from the ID co...

Page 953: ...code 1 to ID code 15 can be set to any desired value However only when disabling connection with the serial programmer the ID codes must be set to 50h 72h 6Fh 74h 65h 63h 74h FFh FFh FFh FFh FFh FFh FFh and FFh from the ID code 1 field to the ID code 15 field Table 31 10 Boot Mode ID Code Protection Specifications ID Code Protection ID Code Matching Result Operation Control Code ID Code 1 to ID Co...

Page 954: ...lator ID code protection Table 31 11 On Chip Debugging Emulator ID Code Protection Specifications ID Code Protection ID Code Matching Result Operation Control Code ID Code 1 to ID Code 15 FFh FFh and FFh 15 bytes are all FFh Disabled N A Enable connection with the on chip debugging emulator 52h 50h 72h 6Fh 74h 65h 63h and 74h any 8 bytes Enabled N A Disable connection with the on chip debugging em...

Page 955: ... including block configuration size and addresses where the user area and data area are allocated and select the endian of data and a bit rate When the MCU receives the program erase host state transition command from the host it determines whether boot mode ID code protection is enabled or disabled If boot mode ID code protection is disabled the MCU enters the inquiry setting host command wait st...

Page 956: ...the host Commands include 1 byte commands and multiple byte commands Responses include 1 byte responses multiple byte responses and error responses A multiple byte command and multiple byte response have Size for informing the number of transmit receive data bytes and SUM for detecting communication errors Size indicates the number of transmit receive data bytes excluding Command code the first by...

Page 957: ...r to Figure 31 26 for details on the state transitions Command 4Fh Response 5Fh Size State Error SUM Table 31 12 Information Regarding the States Code State 1 Description 11h Inquiry setting host command wait state Device selection wait state 12h 13h Operating frequency selection wait state 1Fh Program erase host command wait state transition command wait state 31h Boot mode ID code authentication...

Page 958: ...cters 1 byte Number of characters for the device code and device name Device code 4 bytes Identification code indicating the endian of developed software Series name n bytes The series name of the MCU ASCII code and the classification of little endian big endian SUM 1 byte Value that is calculated so the sum of response data is 00h Table 31 14 Inquiry Commands Command Description Supported device ...

Page 959: ...gram command is available SUM 1 byte Value that is calculated so the sum of response data is 00h the value is always A8h 31 10 5 3 User Area Information Inquiry When the MCU receives this command it sends the number of user areas and addresses Size 1 byte Total bytes of Number of areas Area start address and Area end address the value is always 09h Number of areas 1 byte Number of user areas the v...

Page 960: ...00 19h Start address of the user area 4 bytes Start address of the user area Block size of one block for the user area 4 bytes Memory size of one block the value is always 00 00 08 00h Number of blocks of the user area 4 bytes Number of blocks in the user area Start address of the data area 4 bytes Start address of the data area the value is always 00 10 00 00h Block size of one block for the data...

Page 961: ... If the device is not supported or the SUM of the received command does not match the MCU sends an error response Size 1 byte Number of characters of the device code the value is always 04h Device code 4 bytes Identification code to identify an endian of the developed software code in the response to the support device inquiry command SUM 1 byte Value that is calculated so the sum of command data ...

Page 962: ... confirmation data the MCU sends a response 06h If the MCU fails to receive the communication confirmation data the MCU sends an error response Size 1 byte Total bytes of data of Bit rate Dummy data Number of clocks and Multiplier the value is always 07h Bit rate 2 bytes New bit rate The value is calculated by dividing the bit rate by 100 Example Set 00C0h for 19200 bps Dummy data 2 bytes The valu...

Page 963: ... Wait State Transition This command is used for the transition from the inquiry setting host command wait state to the program erase host command wait state When the MCU receives this command it determines whether boot mode ID code protection is enabled or disabled When boot mode ID code protection is disabled all blocks in the user area and data area are erased When all blocks are successfully er...

Page 964: ...r response When the ID codes do not match three times consecutively while the control code is 45h all blocks in the user area and data area are erased If an error occurs during erasure the MCU sends an error response Also even if all blocks are successfully erased the MCU sends an error response and continues the boot mode ID code state Reset the MCU to enter the program erase host command wait st...

Page 965: ...ram wait state where only the program command to the user area or data area can be accepted and sends a response 06h Table 31 17 Program Erase Commands Command Function User data area program preparation Select the user area or data area to program and enter the program wait state Program Program the specified data to the selected area in the user area or data area Or enter the program erase host ...

Page 966: ... enter the program erase host command wait state after the program operation ends send 50h FFh FFh FFh FFh B4h from the host The MCU sends a response 06h and enters the program erase host command wait state Program address 4 bytes Address for program destination Set the lower 8 bits to 0 Set FFFF FFFFh for end of program Program data n bytes Program data n 256 0 for end of program When the program...

Page 967: ... response 06h and enters the program erase host command wait state Command 51h Program address Program data length Program data SUM Program address 4 bytes Address for program destination Set the lower 2 bits of the selected address to 0 Set FFFF FFFFh for end of data area program Program data length 1 byte Size of program data Set 4 byte data Set 00h for end of data area program Program data n by...

Page 968: ... in the block start address is successfully erased the MCU sends an error response 06h If the SUM of the received command does not match or an error occurs during an erase operation the MCU sends an error response To enter the program erase host command wait state after the erase operation ends send 59h 04h FFh FFh FFh FFh A7h from the host The MCU enters the program erase host command wait state ...

Page 969: ...ormation inquiry command or the data area information inquiry command When the MCU performs a read successfully it sends data of the specified range If the SUM of the received command does not match or the MCU fails to perform a read successfully it sends an error response Size 1 byte Total bytes for Read start address and Read size Area 1 byte Area that is read 01h User area or data area Read sta...

Page 970: ... size The address calculated from the read start address and read size is not in the selected area 31 10 9 2 User Area Checksum This command used to obtain the checksum of the entire user area When the MCU receives this command it adds data from the start address to the end address in bytes in the user area and sends the calculated result checksum as a response Size 1 byte Number of bytes for chec...

Page 971: ...ds an error response Error 1 byte Error code 52h Not blank This command used to obtain the checksum of the entire data area When the MCU receives this command it adds data from the start address to the end address in bytes in the data area and sends the calculated result checksum as a response Command 61h Response 71h Size Data area checksum SUM Size 1 byte Number of bytes for checksum of the data...

Page 972: ...the start address of the start block Set FFh to clear the access window settings Access window start address HL 1 byte Start address of the access window A23 to A16 Set A23 to A16 of the start address of the start block Set FFh to clear the access window settings Access window end address LH 1 byte End address of the access window A15 to A8 Set A15 to A8 of the end address of the end block Set FFh...

Page 973: ...sends an error response Access window start address LH 1 byte Start address of the access window range A15 to A8 Access window start address HL 1 byte Start address of the access window range A23 to A16 Access window end address LH 1 byte End address of the access window range A15 to A8 Access window end address HL 1 byte End address of the access window range A23 to A16 SUM 1 byte Value that is c...

Page 974: ...7 Program the user area and data area 2 3 8 Check data in the user area 2 9 Check data in the data area 2 10 Set the access window in the user area 11 Reset the MCU Note 1 If the necessary information has been already received step 2 can be skipped Note 2 Processing steps from 6 to 10 can be proceeded as necessary and their order can be changed Note 3 When a timeout occurs or invalid response data...

Page 975: ...he MCU in boot mode and perform the automatic adjustment for the bit rate again When the MCU receives 55h the MCU sends E6h and enters the inquiry setting command wait state If the MCU fails to receive 55h the MCU sends FFh When the programmer receives FFh restart the MCU in boot mode and perform the automatic adjustment for the bit rate again Figure 31 28 Bit Rate Automatic Adjustment Procedure A...

Page 976: ...user area 3 Send a block information inquiry command 26h to check the block configuration The MCU returns the start address the size of one block and the number of blocks for the user area and data area 4 Send a data area information inquiry command 2Bh to check the start and end addresses of the data area The MCU returns the start and end addresses of the data area Figure 31 29 Procedure to Recei...

Page 977: ...mand 10h Select the device code according to the endian of developed software 2 Send the operating frequency select command 3Fh to change the communication bit rate from 9 600 or 19 200 bps Figure 31 30 Procedure to Select the Device and Change the Bit Rate 10h device select command MCU 46h ACK 90h XXh error code 3Fh operating frequency select command 06h ACK BFh XXh error code Wait for 1 bit peri...

Page 978: ...t command wait state Use the serial programmer to start from the operation described in section 31 11 6 Procedure to Erase the User Area and Data Area 2 When the boot mode ID code protection is enabled the MCU sends a response 16h and enters the ID code authentication wait state Use the serial programmer to start from the operation described in section 31 11 5 Procedure to Unlock Boot Mode ID Code...

Page 979: ...ot erased Use the serial programmer to start from the operation described in section 31 11 6 Procedure to Erase the User Area and Data Area 2 If ID codes do not match consecutively the MCU remains in the boot mode ID code authentication state Reset the MCU and then use the serial programmer to start again from section 31 11 1 Bit Rate Automatic Adjustment Procedure Figure 31 32 Procedure to Unlock...

Page 980: ...ation command 48h 2 Send a block erase command 59h 3 To place the MCU in the program erase host command wait state send a block erase command for ending the erasure 59h 04h FFh FFh FFh FFh A7h Figure 31 33 Procedure to Erase the User Area and Data Area 48h erase preparation command 06h ACK D9h XXh error code 06h ACK Repeat until all blocks for programming the user program are erased 59h block eras...

Page 981: ...To place the MCU in the program erase host command wait state send the program command 50h FFh FFh FFh FFh B4h or the data area program command 51h FFh FFh FFh FFh 00h B3h for ending the programming Figure 31 34 Procedure to Program the User Area and Data Area 06h ACK D0h XXh error code 06h ACK Repeat until the user program is completely written 06h ACK Serial programmer MCU Program 2 1 3 43h user...

Page 982: ... successfully Send a memory read command 52h to read data in the user area 2 Send the user area checksum command 4Bh to check program data using the checksum of user area 3 Send a user area blank check command 4Dh to check if the user area has data Figure 31 35 Procedure to Check Data in the User Area 4Dh user area blank check command 06h blank D2h XXh error code 52h read data response Repeat unti...

Page 983: ...d data to check if the program operation is performed successfully Send a memory read command 52h to read data in the data area 2 Send the data area checksum command 61h to check program data using the checksum of data area 3 Send the data area blank check command 62h to check if the data area has data 62h data area blank check command 06h blank D2h XXh error code 52h read data response Repeat unt...

Page 984: ...ows 1 Send the access window program command 74h to set the access window settings 2 Send the access window read command 73h to confirm the access window settings Figure 31 37 Procedure to Set the Access Window in the User Area F4h XXh error code 06h ACK 73h access window read command 73h setting values of the access window 74h access window information program command Serial programmer Settings u...

Page 985: ...memory flash rewrite routine in the user program When rewriting the E2 DataFlash the BGO can be used to execute the flash rewrite routine on the ROM The E2 DataFlash can also be rewritten by executing the flash rewrite routine that is transferred on the RAM in advance Figure 31 38 Self Programming Overview Flash rewrite routine Flash information Erase program Note 1 The ROM cannot be rewritten by ...

Page 986: ... the ROM The description in 5 applies only to the ROM 6 Location of Interrupt Vectors during a Program Erase Operation When an interrupt occurs during a program erase operation the vector may be fetched from the ROM To avoid fetching the vector from the ROM set the destination for fetching interrupt vectors to an area other than the ROM with the CPU interrupt table register INTB 7 Abnormal Termina...

Page 987: ...t mode again 2 Notes on Power Supply Voltage in Boot Mode SCI Interface When the bit rate exceeds 500 kbps in boot mode SCI Interface use a voltage that is 3 0 V or higher 3 Notes on Option Setting Memory in Boot Mode The settings of option function select register 0 OFS0 option function select register 1 OFS1 and endian select register MDE are disabled in boot mode 4 Notes on Switching the Start ...

Page 988: ...5 V tolerant ports it will not cause problems such as damage to the MCU 32 2 Recommended operating conditions Note 1 AVCC0 and VCC can be set individually within the operating range Note 2 When powering on the VCC and AVCC0 pins power them on at the same time or the VCC pin first and then the AVCC0 pin Note 1 Use a multilayer ceramic capacitor whose nominal capacitance is 4 7 µF and a capacitance ...

Page 989: ...r input hysteresis RIIC input pin except for SMBus ΔVT VCC 0 05 P40 to P47 AVCC0 0 1 Other than RIIC input pin or P40 to P47 VCC 0 1 Input level voltage except for Schmitt trigger input pins MD VIH VCC 0 9 VCC 0 3 V EXTAL external clock input VCC 0 8 VCC 0 3 RIIC input pin SMBus 2 1 VCC 0 3 MD VIL 0 3 VCC 0 1 EXTAL external clock input 0 3 VCC 0 2 RIIC input pin SMBus 0 3 0 8 Table 32 5 DC Charact...

Page 990: ... 6 ICLK 16 MHz 3 3 ICLK 8 MHz 2 1 Deep sleep mode No peripheral operation 2 ICLK 32 MHz 1 0 ICLK 16 MHz 0 9 ICLK 8 MHz 0 8 All peripheral operation Normal 3 ICLK 32 MHz 3 8 ICLK 16 MHz 2 3 ICLK 8 MHz 1 6 Increase during BGO operation 5 2 5 Middle speed operating modes Normal operating mode No peripheral operation 6 ICLK 12 MHz 1 9 ICLK 8 MHz 1 3 ICLK 1 MHz 0 3 All peripheral operation Normal 7 ICL...

Page 991: ...program Note 6 Peripheral module clocks are stopped The clock source is the PLL when ICLK is 12 MHz is the HOCO when the ICLK is at 8 MHz or is the LOCO when the ICLK is at another frequency FCLK and PCLK are set for division by 64 Note 7 Peripheral module clocks are supplied The clock source is the PLL when ICLK is 12 MHz is the HOCO when the ICLK is at 8 MHz or is the LOCO when the ICLK is at an...

Page 992: ...a 85 C 1 Ta 105 C 2 Ta 105 C 1 Ta 85 C 2 Ta 105 C 2 Ta 105 C 1 Ta 85 C 1 Ta 55 C 2 Ta 55 C 1 Ta 25 C 2 Ta 25 C 1 Note 1 Indicates the average of the typical samples through actual measurement during product evaluation Note 2 Indicates the average of the upper limit samples through actual measurement during product evaluation 0 1 1 10 100 40 20 0 20 40 60 80 100 120 ICC µA 1 Ta C 2 1 2 Note 1 Avera...

Page 993: ...t Permissible total consumption power 1 Pd 105 mW G version product Table 32 9 DC Characteristics 6 Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ 2 Max Unit Test Conditions Analog power supply current During A D conversion when the sample and hold circuit and programmable gain amplifier are in use IAVCC 4 6 6 9 mA During A D conversion when the s...

Page 994: ... Figure 32 3 Vr VCC VCC 0 08 10 Figure 32 3 Vr VCC VCC 0 06 Allowable voltage change rising falling gradient dt dVCC 1 0 ms V When VCC change exceeds VCC 10 Table 32 12 Permissible Output Currents Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Max Unit Permissible low level output current Large current ports P71 to P76 PB6 IOL 10 0 mA RIIC pins 6 0 Ports ...

Page 995: ... V IOH 5 0 mA P40 to P47 AVCC0 0 5 IOH 1 0 mA Ports other than above Normal output mode VCC 0 5 IOH 1 0 mA High drive output mode VCC 0 5 IOH 2 0 mA Table 32 14 Output Values of Voltage 2 Conditions VCC 4 0 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Max Unit Test Conditions Low level output voltage Large current ports P71 to P76 PB6 VOL 0 8 V IOL 10 0 mA RIIC pins S...

Page 996: ... 0 mA 3 25 IOH 2 0 mA 3 21 IOH 4 0 mA 3 11 IOH 8 0 mA P71 to P76 PB6 Large current Ports VOH 3 29 V IOH 1 0 mA 3 27 IOH 2 0 mA 3 24 IOH 4 0 mA 3 23 IOH 5 0 mA 3 15 IOH 10 0 mA Table 32 16 Normal I O Pin VOH Voltage Characteristics Reference Data Conditions VCC AVCC0 5 0 V VSS AVSS0 0 V Ta 25 C Item Symbol Min Typ Max Unit Test Conditions High level output voltage All output pins except for P71 to ...

Page 997: ...mA 0 16 IOL 8 0 mA P71 to P76 PB6 Large current Ports VOL 0 01 V IOL 1 0 mA 0 02 IOL 2 0 mA 0 05 IOL 4 0 mA 0 06 IOL 5 0 mA 0 12 IOL 10 0 mA Table 32 18 Normal I O Pin VOL Voltage Characteristics Reference Data Conditions VCC AVCC0 5 0 V VSS AVSS0 0 V Ta 25 C Item Symbol Min Typ Max Unit Test Conditions Low level output voltage All output pins except for P71 to P76 PB6 Normal output mode VOL 0 02 ...

Page 998: ... to 1 MHz 2 MHz or 3 MHz A non integer frequency such as 1 5 MHz cannot be set Note 2 The frequency accuracy of FCLK should be 3 5 Note 3 The minimum frequency of PCLKD is 1 MHz when the A D converter is to be used Note 4 The maximum operating frequencies do not take errors in the HOCO frequency and jitters in the PLL signal Refer to Table 32 21 Clock Timing Table 32 19 Operating Frequency Value H...

Page 999: ...EXTAL external clock input high pulse width tXH 20 ns EXTAL external clock input low pulse width tXL 20 ns EXTAL external clock rise time tXr 5 ns EXTAL external clock fall time tXf 5 ns EXTAL external clock input wait time 1 tEXWT 0 5 μs Main clock oscillator oscillation frequency 2 fMAIN 1 20 MHz Main clock oscillation stabilization time crystal 2 tMAINOSC 3 ms Figure 32 5 Main clock oscillation...

Page 1000: ...tart Timing Figure 32 7 IWDT Dedicated Clock Oscillation Start Timing Figure 32 8 HOCO Clock Oscillation Start Timing After Reset is Canceled by Setting OFS1 HOCOEN Bit to 0 Main clock oscillator output MOSCCR MOSTP tMAINOSC LOCO clock oscillator output LOCOCR LCSTP tLOCO IWDT dedicated clock oscillator output ILOCOCR ILCSTP tILOCO RES Internal reset HOCO clock OFS1 HOCOEN tRESWT ...

Page 1001: ...32 9 HOCO Clock Oscillation Start Timing Oscillation is Started by Setting HOCOCR HCSTP Bit Figure 32 10 PLL Clock Oscillation Start Timing PLL is Operated after Main Clock Oscillation Has Settled HOCO clock HOCOCR HCSTP tHOCO PLLCR2 PLLEN PLL clock MOSCCR MOSTP tMAINOSC Main clock oscillator output tPLL ...

Page 1002: ... tRESWP 3 ms Figure 32 11 Other than above tRESW 30 μs Figure 32 12 Wait time after RES cancellation at power on tRESWT 27 5 ms Figure 32 11 Wait time after RES cancellation during powered on state tRESWT 120 μs Figure 32 12 Independent watchdog timer reset period tRESWIW 1 IWDT clock cycle Figure 32 13 Software reset period tRESWSW 1 ICLK cycle Wait time after independent watchdog timer reset can...

Page 1003: ...gister MOSCWTCR is set to 04h Note 3 When the frequency of the PLL is 24 MHz and that of the ILCK is 12 MHz When the main clock oscillator wait control register MOSCWTCR is set to 04h Note 4 When the frequency of the external clock is 12 MHz When the main clock oscillator wait control register MOSCWTCR is set to 00h Note 5 When the frequency of the PLL is 24 MHz and that of the ILCK is 12 MHz When...

Page 1004: ...m Low Power Consumption Modes 3 Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions Recovery time from deep sleep mode 1 High speed mode 2 tDSLP 2 3 5 μs Figure 32 15 Middle speed mode 3 tDSLP 3 4 Table 32 26 Operating Mode Transition Time Conditions VCC 2 7 V to AVCC0 AVCC0 2 7 V to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Mode befo...

Page 1005: ...Q Interrupt Input Timing Table 32 27 Control Signal Timing Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions NMI pulse width tNMIW 200 ns NMI digital filter disabled NMIFLTE NFLTEN 0 2 tPcyc 200 ns 2 tPcyc 1 2 tPcyc 200 ns 200 NMI digital filter enabled NMIFLTE NFLTEN 1 3 tNMICK 200 ns 3 5 tNMICK 2 3 tNMICK 200 ns IRQ pulse w...

Page 1006: ...for a comparator C is not in use CMPCTL CDFS 1 0 00 and the values exclude the time until the level of the detection signal changes after a comparator C detects the required change in voltage Register setting tPOEDS 1 tPcyc 0 2 Figure 32 25 Time for access to the register is not included Oscillation stop detection tPOEDOS 21 Figure 32 26 SCI Input clock cycle Asynchronous tScyc 4 tPcyc Figure 32 2...

Page 1007: ...0 4 0 6 tSPcyc SCK clock low pulse width tSPCKWL 0 4 0 6 SCK clock rise fall time tSPCKr tSPCKf 20 ns Data input setup time master VCC 4 0 V or above tSU 40 ns Figure 32 31 Figure 32 32 VCC 2 7 V or above 65 Data input setup time slave 40 Data input hold time tH 40 SS input setup time tLEAD 3 tSPcyc SS input hold time tLAG 3 Data output delay time master tOD 40 ns Data output delay time slave VCC ...

Page 1008: ...cyc 300 SCL SDA rise time tSr 1000 SCL SDA fall time tSf 300 SCL SDA spike pulse removal time tSP 0 1 4 tIICcyc SDA bus free time tBUF 3 6 tIICcyc 300 START condition hold time tSTAH tIICcyc 300 Repeated START condition setup time tSTAS 1000 STOP condition setup time tSTOS 1000 Data setup time tSDAS tIICcyc 50 Data hold time tSDAH 0 SCL SDA capacitive load Cb 3 400 pF RIIC Fast mode SCL cycle time...

Page 1009: ... 0 V Ta 40 to 105 C Item Symbol Min Max Unit Test Conditions Simple I2C Standard mode SDA rise time tSr 1000 ns Figure 32 35 SDA fall time tSf 300 SDA spike pulse removal time tSP 0 4 tPcyc 1 Data setup time tSDAS 250 Data hold time tSDAH 0 SCL SDA capacitive load Cb 2 400 pF Simple I2C Fast mode SDA rise time tSr 300 ns Figure 32 35 SDA fall time tSf 300 SDA spike pulse removal time tSP 0 4 tPcyc...

Page 1010: ...s Figure 32 20 MTU Clock Input Timing Figure 32 21 POE Input Timing n 0 8 10 Figure 32 22 Output Disable Time for POE in Response to Transition of the POEn Signal Level n 0 8 10 MTCLKA to MTCLKD PCLK tTCKWL tTCKWH POEn input PCLK tPOEW POEn input MTU PWM output pins Outputs disabled tPOEW tPOEDI ...

Page 1011: ...or POE in Response to Detection of the Comparator Outputs n 0 to 2 Figure 32 25 Output Disable Time for POE in Response to the Register Setting Outputs disabled Simultaneous active level outputs detected 1 Note 1 When the active level is set to low MTU PWM output pins tPOEDO COMPn level detection signal MTU PWM output pins Outputs disabled tPOEDC MTU PWM output pins Outputs disabled tPOEDS Corresp...

Page 1012: ...for POE in Response to the Oscillation Stop Detection Figure 32 27 SCK Clock Input Timing Figure 32 28 SCI Input Output Timing Clock Synchronous Mode Oscillation stop detection signal internal signal MTU PWM output pins Outputs disabled tPOEDOS Main clock tSCKW tSCKr tSCKf tScyc SCKn n 1 5 12 tTXD tRXS tRXH TXDn RXDn SCKn n 1 5 12 ...

Page 1013: ...ernal Trigger Input Timing Figure 32 30 Simple SPI Clock Timing ADTRG0 PCLK tTRGW tSPCKWH VOH VOH VOL VOL VOH VOH tSPCKWL tSPCKr tSPCKf VOL tSPcyc tSPCKWH VIH VIH VIL VIL VIH VIH tSPCKWL tSPCKr tSPCKf VIL tSPcyc VOH 0 7 VCC VOL 0 3 VCC VIH 0 7 VCC VIL 0 3 VCC n 1 5 12 SCKn Master select output SCKn Slave select input Simple SPI ...

Page 1014: ...SPI Clock Timing Master CKPH 0 tDr tDf tSU tH tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SCKn CKPOL 0 output SCKn CKPOL 1 output SMISOn input SMOSIn output n 1 5 12 Simple SPI Simple SPI SCKn CKPOL 1 output SCKn CKPOL 0 output SMISOn input SMOSIn output tDr tDf tSU tH tOH MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT tOD n 1 5 12 ...

Page 1015: ...U tH tLEAD tTD tLAG tSA MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT MSB IN MSB OUT tOH tOD tREL SCKn CKPOL 0 input SCKn CKPOL 1 input SMISOn output SMOSIn input n 1 5 12 Simple SPI SSn input tDr tDf tSA tOH tLEAD tTD tLAG tH LSB OUT Last data DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT SCKn CKPOL 1 input SCKn CKPOL 0 input SMISOn output SMOSIn input n 1 5 12 Simple SPI S...

Page 1016: ...nput Output Timing and Simple I2C Bus Interface Input Output Timing Test conditions VIH VCC 0 7 VIL VCC 0 3 SDA SCL VIH VIL tSTAH tSCLH tSCLL P 1 S 1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P 1 tBUF Sr 1 Note 1 S P and Sr indicate the following conditions respectively S START condition P STOP condition Sr Repeated START condition ...

Page 1017: ... 105 C Source impedance 1 0 kΩ Item Min Typ Max Unit Test Conditions Frequency 1 32 MHz Resolution 12 Bit Conversion time 1 Operation at PCLKD 32 MHz Sample and hold circuit not in use 1 41 μs High precision channel ADSSTRn SST 7 0 bits 0Dh Sample and hold circuit in use 2 16 High precision channel ADSSTRn SST 7 0 bits 0Dh ADSHCR SSTSH 7 0 bits 0Bh AN000 to 002 0 25 V to AVCC0 0 25 V Analog input ...

Page 1018: ...0 bits 0Dh Sample and hold circuit in use 2 25 High precision channel ADSSTRn SST 7 0 bits 0Dh ADSHCR SSTSH 7 0 bits 0Eh AN000 to 002 0 25 V to AVCC0 0 25 V Analog input capacitance 12 pF Offset error Sample and hold circuit not in use 0 5 4 5 LSB Sample and hold circuit in use 1 5 6 5 Full scale error Sample and hold circuit not in use 0 75 4 5 LSB Sample and hold circuit in use 1 5 6 5 Quantizat...

Page 1019: ...mV 1 5 mV are used as analog input voltages If analog input voltage is 6 mV absolute accuracy 5 LSB means that the actual A D conversion result is in the range of 003h to 00Dh though an output code 008h can be expected from the theoretical A D conversion characteristics Integral nonlinearity error INL Integral nonlinearity error is the maximum deviation between the ideal line when the measured off...

Page 1020: ...between 1 LSB width based on the ideal A D conversion characteristics and the width of the actual output code Offset error Offset error is the difference between a transition point of the ideal first output code and the actual first output code Full scale error Full scale error is the difference between a transition point of the ideal last output code and the actual last output code ...

Page 1021: ... V to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions Input offset voltage Vpoff 8 mV Input voltage range Vpin Vpout min G Vpout max G V Output voltage range G 2 000 2 500 3 077 Vpout 0 1 AVCC0 0 9 AVCC0 V G 5 000 8 000 10 000 0 15 AVCC0 0 85 AVCC0 Gain G 2 000 10 000 Gain error G 2 000 2 500 3 077 Gerr 1 0 1 5 G 5 000 8 000 10 000 1 5 2 5 Slew rate SR 10 V μs Opera...

Page 1022: ... 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions Offset voltage Vcioff 20 mV Reference input voltage range Vcref 0 AVCC0 V Response time tcr 200 ns VOD 100 mV CMPCTL CDFS 0 tcf 200 Stabilization wait time for input selection tcwait 300 ns Operation stabilization wait time tcmp 1 μs Reference input voltage CMPC00 02 03 CMPC10 12 13 CMPC20 22 COMPn ...

Page 1023: ...teristics 32 8 D A Conversion Characteristics Table 32 38 D A Conversion Characteristics Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions Resolution 8 Bit Conversion time tDCONV 3 0 μs Absolute accuracy 1 0 3 0 LSB ...

Page 1024: ...VL 1 0 bits Table 32 39 Power On Reset Circuit and Voltage Detection Circuit Characteristics 1 Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions Voltage detection level Power on reset POR VPOR 1 35 1 50 1 65 V Figure 32 38 Figure 32 39 Voltage detection circuit LVD0 1 Vdet0_0 3 67 3 84 3 97 Figure 32 40 At falling edge VCC Vd...

Page 1025: ... V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions Wait time after power on reset cancellation tPOR 28 4 ms Figure 32 39 Wait time after voltage monitoring 0 reset cancellation tLVD0 568 μs Figure 32 40 Wait time after voltage monitoring 1 reset cancellation tLVD1 100 μs Figure 32 41 Wait time after voltage monitoring 2 reset cancellation tLVD2 100 μs Figure 32 42 Respons...

Page 1026: ...ction Circuit Timing Vdet0 Internal reset signal active low VCC tPOR VPOR 1 0 V tw POR 1 tdet Note 1 tw POR is the time required for a power on reset to be enabled while the external power VCC is being held below the valid voltage 1 0 V When VCC turns on maintain tw POR for 1 0 ms or more tVOFF Vdet0 VCC tdet tdet Internal reset signal active low VLVH tLVD0 ...

Page 1027: ...32 42 Voltage Detection Circuit Timing Vdet2 tVOFF Vdet1 VCC tdet tdet tLVD1 Td E A LVD1E LVD1 Comparator output LVD1CMPE LVD1MON Internal reset signal active low When LVD1RN L When LVD1RN H VLVH tLVD1 tVOFF Vdet2 VCC tdet tdet tLVD2 Td E A LVD2E LVD2 Comparator output LVD2CMPE LVD2MON Internal reset signal active low When LVD2RN L When LVD2RN H VLVH tLVD2 ...

Page 1028: ...ction Timing Table 32 41 Oscillation Stop Detection Timing Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Ta 40 to 105 C Item Symbol Min Typ Max Unit Test Conditions Detection time tdr 1 ms Figure 32 43 tdr Main clock OSTDSR OSTDF Low speed clock ICLK tdr Main clock OSTDSR OSTDF ICLK When the main clock is selected When the PLL clock is selected PLL clock ...

Page 1029: ...amming or erasing of the flash memory When using FCLK at below 4 MHz the frequency can be set to 1 MHz 2 MHz or 3 MHz A non integer frequency such as 1 5 MHz cannot be set Note The frequency accuracy of FCLK should be 3 5 Check the accuracy of the frequency from the clock source Table 32 42 ROM Code Flash Memory Characteristics 1 Item Symbol Min Typ Max Unit Conditions Program erase cycle 1 NPEC 1...

Page 1030: ...he frequency from the clock source Table 32 44 ROM Code Flash Memory Characteristics 3 Middle Speed Operating Mode Conditions VCC 2 7 V to 5 5 V AVCC0 VCC to 5 5 V VSS AVSS0 0 V Temperature range for program erase Ta 40 to 85 C Item Symbol FCLK 1 MHz FCLK 8 MHz Unit Min Typ Max Min Typ Max Program time 4 byte tP4 143 1330 96 8 932 μs Erase time 1 Kbyte tE1K 8 3 269 5 85 219 ms 128 Kbyte tE128K 203...

Page 1031: ...uring programming or erasing of the flash memory When using FCLK at below 4 MHz the frequency can be set to 1 MHz 2 MHz or 3 MHz A non integer frequency such as 1 5 MHz cannot be set Note The frequency accuracy of FCLK should be 3 5 Table 32 45 E2 DataFlash Characteristics 1 Item Symbol Min Typ Max Unit Conditions Program erase cycle 1 NDPEC 100000 1000000 Times Data retention After 10000 times of...

Page 1032: ... an external capacitor close to the pins Do not apply the power supply voltage to the VCL pin Insert a multilayer ceramic capacitor as a bypass capacitor between each pair of the power supply pins Implement a bypass capacitor to the MCU power supply pins as close as possible Use a recommended value of 0 1 μF as the capacitance of the capacitors For the capacitors related to crystal oscillation see...

Page 1033: ... 47 48 46 RX13T Group PLQP0048KB B 48 pin LFQFP Top view VS S V CC VCL V SS VCC 18 17 16 15 14 13 Bypass capacitor 0 1 μF External capacitor for power supply stabilization 4 7 μF Bypass capacitor 0 1 μF Note Do not apply the power supply voltage to the VCL pin Use a 4 7 μF multilayer ceramic for the VCL pin and place it close to the pin A recommended value is shown for the capacitance of the bypas...

Page 1034: ... 1 μF External capacitor for power supply stabilization 4 7 μF Bypass capacitor 0 1 μF Note Do not apply the power supply voltage to the VCL pin Use a 4 7 μF multilayer ceramic for the VCL pin and place it close to the pin A recommended value is shown for the capacitance of the bypass capacitors VCC 15 14 13 12 11 10 9 16 26 27 28 29 30 31 32 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 Bypass capac...

Page 1035: ...canceling source while it is used as an external interrupt pin Table 1 1 Port States in Each Processing Mode Port Name Pin Name Reset Software Standby Mode P10 P11 IRQ0 IRQ1 Hi Z Keep O 1 P22 P23 P24 IRQ2 IRQ4 IRQ3 Hi Z Keep O 1 P36 P37 Hi Z Keep O P40 to P47 Hi Z Keep O P70 IRQ5 Hi Z Keep O 1 P71 to P76 Hi Z Keep O P93 P94 IRQ0 IRQ1 Hi Z Keep O 1 PA2 IRQ4 Hi Z Keep O 1 PA3 Hi Z Keep O PB0 PB2 PB3...

Page 1036: ...9 RX13T Group Appendix 2 Package Dimensions Appendix 2 Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in Packages on Renesas Electronics Corporation website Figure A 48 Pin LFQFP PLQP0048KB B ...

Page 1037: ...10 7 00 0 10 9 00 0 20 9 00 0 20 1 70 MAX 0 10 0 10 1 40 c θ e x y 0 80 0 20 0 10 L 0 50 0 20 0 to 8 0 37 0 05 b NOTE 1 Dimensions 1 and 2 do not include mold flash 2 Dimension 3 does not include trim offset y e x b M θ L c HD HE A1 A2 A D E detail of lead end 8 16 1 32 9 17 25 24 2 1 3 JEITA Package Code RENESAS Code Previous Code MASS TYP g P LQFP32 7x7 0 80 PLQP0032GB A P32GA 80 GBT 1 0 2 ...

Page 1038: ... number Changes according to the corresponding issued Technical Update Items without Technical Update document number Minor changes that do not require Technical Update to be issued REVISION HISTORY RX13T Group User s Manual Hardware Rev Date Description Classification Page Summary 1 00 Jul 31 2019 First edition issued REVISION HISTORY ...

Page 1039: ...RX13T Group User s Manual Hardware Publication Date Rev 1 00 Jul 31 2019 Published by Renesas Electronics Corporation Colophon ...

Page 1040: ...l 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1611 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886 9022 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit ...

Page 1041: ...RX13T Group R01UH0822EJ0100 Back cover ...

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