Renesas 8V19N49 Series Manual Download

Page: 9 / 20

R31UH0005EU0100 Rev.1.0

Page 9

Jun 3, 2021

8V19N49x Hardware Design Guide

3.3.1.2

Third Order Loop Filter for the VCXO PLL

This section provides design guidelines for a 3rd order loop filter for the 8V19N490 VCXO PLL. A general 3

order loop filter is displayed in

Figure 10

Figure 10. Typical 3

Order Loop Filter

The Rs, Cs, and Cp are chosen standard values from the 2

order loop filter. In this example, the chosen values

are Rs = 33KOhm, Cs = 1uF, and Cp = 27nF. The following equation can help determine the 3

order loop filter,

R3 and C3.

1. Choose an R3 value. Suggest R3 ~ 1.5xRs to ~2.5xRs or greater (e.g, R3 = 51KHz is used in this example).

C3 can be calculated using the following equation:

2. Pick γ = 4 in this example.

C3 is calculated to be 4.37nF. A closest standard capacitor value can be used.

Table 2

shows some VCXO PLL Loop Filter examples for different VCXO frequencies. Other values can also be

used to meet other specific conditions and requirements.

Table 2. Loop Filter Examples

VCXO Frequency

[1]

122.88MHz

30.72MHz

VCXO Made/Model Examples

Epson,VG4513CA/CB

Epson VG3225EFN*

Crystek CVPD922
Crystek CHPD950

Crystek CVPD-037

Rakon RVX7050M

TXC

Vectron

Epson, TXC, Rakon

Typical VCXO Gain, Kvco

10k Hz/V

2.5k Hz/V

Loop Bandwidth, Fc

~40Hz

PDF, Phase Detector Input Frequency

120kHz

960kHz

Feedback Divider (N or Mv)

1024

Charge Pump Current Setting
(Can be slightly Adjusted to change
the loop band width)

800uA

33k Ohm

1k Ohm

1uF

10uF

27nF

330nF

LFV

VCXO-VC

Summary of Contents for 8V19N49 Series

Page 1: ...5 3 2 3rd Order Loop Filter 6 3 3 Loop Filter Calculation Examples 7 3 3 1 Loop Filter for VCXO PLL 7 3 3 2 Loop Filter for VCO PLL 10 4 Input Output Interface 11 4 1 Input Termination for Reference Clock Input 11 4 2 Output Terminations for QCLK and QREF Drivers 13 4 2 1 LVPECL Type Driver Terminations 13 4 2 2 LVDS Type Driver Terminations 15 4 2 3 DC Coupling Interface for QREF Driver 15 5 Sche...

Page 2: ...U RKP ODE HTXLSPHQW PRQLWRULQJ H J SKDVH QRLVH PHDVXUHPHQW Keep this trace from noisy source Keep this trace from noisy source VDD_LCF Clean LVPECL Termination Example There are many way to terminate LVPECL driver There are many way to terminate LVPECL driver VDD1 VDD_SYNC VDD_QCLKB VDD_QREFB VDD_QCLKD VDD_QREFD VDD_QCLKE VDD_SPI VDD_CP2 VDD_LCV VDD_QREFC VDD_QCLKC VDD_LCF VDD_QCLKA VDD_QREFA VDD3...

Page 3: ...y and high frequency noise To minimize ESR between power pins and the bypass capacitors Renesas suggests at least one bypass cap per power pin and to place these capacitors as close as possible to the power pins Thicker trace widths between the bypass capacitor and power pin can also help reduce the ESR Figure 2 Example of a 100nF Bypass Capacitor Frequency Response Figure 3 Example of a 10nF Bypa...

Page 4: ...0100 Rev 1 0 Page 4 Jun 3 2021 8V19N49x Hardware Design Guide Figure 4 Example of Larger Value 4 7uF Bypass Capacitor Frequency Response Figure 5 Example of Smaller Value 100pF Bypass Capacitor Frequency Response ...

Page 5: ...e For the VDDO output supplies to reduce output frequency interference the power rails between the output banks that operate at different output frequencies can be isolated using separate LDOs or using 1 to 2 ohm resistors if they share the same power source Additional smaller value capacitors e g 100pF in parallel with the existing 0 1uF near the power pins can provide additional higher frequency...

Page 6: ...fc fz recommend α to be greater than 3 fz is frequency at zero 4 Calculate Cp Where fp is frequency at pole β is ratio between frequency at pole and loop bandwidth β fp fc recommend β greater than 3 5 Verify maximum Phase Margin PM Where The PM should be greater than 50 degrees 3 2 3rd Order Loop Filter This section provides design guidelines for a 3rd order loop filter A typical 3rd order loop fi...

Page 7: ...tool will provide the component values Rs Cs and Cp as result The tool will also calculate maximum phase margin for verification The 3rd order loop filter R3 and C3 are also calculated using the actual 2nd order loop filter components values 3 3 Loop Filter Calculation Examples 3 3 1 Loop Filter for VCXO PLL 3 3 1 1 Second Order Loop Filter for the VCXO PLL This section provides calculation exampl...

Page 8: ...und or derived from the VCXO datasheet The VCO gain can also be measured from lab experiments In this example we use Kvco 10kHz V The 8V19N490 charge pump current can be programmed from 50uA to 1 6mA In this example assume the charge pump current is programmed to Icp 800uA Cs can be calculated from the following equation For α 8 Cs is calculated to be 0 99uF Cs greater than this value can be used ...

Page 9: ...e calculated using the following equation 2 Pick γ 4 in this example C3 is calculated to be 4 37nF A closest standard capacitor value can be used Table 2 shows some VCXO PLL Loop Filter examples for different VCXO frequencies Other values can also be used to meet other specific conditions and requirements Table 2 Loop Filter Examples VCXO Frequency 1 122 88MHz 30 72MHz VCXO Made Model Examples Eps...

Page 10: ...l VCO 2nd order loop filter works in conjunction with the internal circuitries A traditional loop filter calculation method may not be accurate After simulation and actual experiment an example of external two pole loop filter value is provided in Table 3 R3 51k Ohm 1 8k Ohm C3 4 7nF 33nF 1 Other VCXO frequencies can also be used with proper loop filter and parameter setting Below are examples of ...

Page 11: ...nput driven by a differential driver with AC coupling This section discusses only few examples other termination topologies can also be used if desired Figure 13 Input Termination Example 8V19N490 Reference Clock Input CLK nCLK Driven by a 3 3V LVPECL Driver Table 3 VCO PLL 2nd Order Loop Filter Recommendation VCXO used in the 1st PLL 122 88MHz 30 72MHz PDF Phase detector input frequency with doub...

Page 12: ...k Input CLK nCLK AC Coupling Termination Example 1 Figure 16 8V19N490 Reference Clock Input CLK nCLK AC Coupling Termination Example 2 VCC 3 3V Zo 50 Zo 50 LVDS Driv er VCC 3 3V R1 100 Clock Input CLK nCLK VCC 3 3V Clock Input CLK nCLK R4 10K R2 10K R3 5 1K R1 5 1K VCC 3 3V C1 C2 Differential Signal Zo Zo R5 2 x Zo VCC 3 3V Clock Input CLK nCLK C1 C2 Differential Signal Zo Zo R5 Zo R4 10K R3 5 1K ...

Page 13: ...esistor for the DC current path in order for the output to switch A standard LVPECL driver termination is displayed in Figure 17 There are many ways to terminate the LVEPCL driver Figure 18 to Figure 21 show several examples of LVPECL style driver termination Figure 17 Standard LVEPCL 750mV Driver Termination Figure 18 LVPECL 750mV Termination Example 1 VCC 3 3V High Input Impedance CLK nCLK R4 50...

Page 14: ...PECL Driver AC Coupling Termination for the Receiver with Built in Termination VCC 3 3V R4 50 R2 50 Zo 50 Zo 50 VCC 3 3V LVPECL Driv er R2 50 C1 0 1uF optional High Input Impedance CLK nCLK 50 Ohm 50 Ohm 8V79S680 IN nIN VT VCC 3 3V Zo 50 Zo 50 VCC 3 3V LVPECL Driv er R2 120 to 240 R1 120 to 240 Zo 50 Zo 50 VCC 3 3V LVPECL Driv er R2 120 to 240 R1 120 to 240 50 Ohm 50 Ohm 8V79S680 IN nIN VT VCC 3 3...

Page 15: ...e not quite same as standard LVPECL or LVDS The amplitude can be programmed to different amplitude levels 250mV 500mV 750mV and 1000mV The DC offset is about 2V for both LVPECL and LVDS driver 2V DC offset is close the standard LVPECL signal however 8V19N490 LVDS DC offset is about 2V which is not standard In some applications the receiver requires lower DC offset level with DC coupling interface ...

Page 16: ...e s ig n file U N N A M E D 0 TL N D e s ig n e r M in g L im H y p e rL y n x V 7 7 D a te Th u rs d a y S e p 1 1 2 0 0 8 Tim e 1 1 5 0 3 9 C u rs o r 1 V o lta g e 1 3 9 1 6 V Tim e 2 4 9 1 n s C u rs o r 2 V o lta g e 8 5 5 4 m V Tim e 6 9 8 2 n s D e lta V o lta g e 5 3 6 1 m V D e lta Tim e 4 4 9 1 n s S h o w L a te s t W a ve fo rm Y E S 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 1 4 0 0 ...

Page 17: ...n for the non built in is not feasible The DC coupling interface example to shift down the DC offset level is displayed in Figure 27 Figure 26 Receiver with Built in 100 ohm Figure 27 DC Coupling Example for Receiver with Built in Termination Figure 28 Simulation Waveform at the Receiver 50 Ohm R4 100 50 Ohm 8V19N490 LVEPCL 750mV 3 3V R1 43 100 R2 43 R3 100 Receiver w ith Built in 100 Ohm across ...

Page 18: ...d to shift close to this level Figure 29 Interface to Receiver with Built in Termination and Built in DC Bias The value of the component is shown in Table 4 VDDO 3 3V The QREF output is set to LVPECL style driver and the amplitude is set to 750mV Figure 30 Simulation Waveform at the Receiver Table 4 Component Values Component References Component Values R1 100 Ohm R2 100 Ohm R3 100 Ohm R4 100 Ohm ...

Page 19: ...021 8V19N49x Hardware Design Guide 5 Schematic Diagrams The following schematic diagrams are available from request 8V19N490 EVB schematic 8V19N490 EVB board layout 6 Revision History Revision Date Description 1 0 Jun 3 2021 Initial release ...

Page 20: ...re intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing your application and 3 ensuring your application meets applicable standards and any other safety security or other requirements These resources are subject to change without notice Renesas grants yo...

Search results

Summary of Contents for 8V19N49 Series

Reviews:

Related manuals for 8V19N49 Series

Brands by name

Popular brands

Renesas 8V19N49 Series, Manual

Search results

Summary of Contents for 8V19N49 Series

Reviews:

Related manuals for 8V19N49 Series

Brands by name

Popular brands