Renesas 8V19N49 Series, Manual

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R31UH0005EU0100 Rev.1.0 Page 18
Jun 3, 2021
8V19N49x Hardware Design Guide
4.2.3.3 Receiver with Built-in Termination and DC Bias
This section provides a DC coupling termination interface example to shift down the DC offset level for 8V19N490
driver. In this example, the receiver has built-in termination and built-in DC bias of 0.5V. The DC offset is required
to shift close to this level.
Figure 29. Interface to Receiver with Built-in Termination and Built-in DC Bias
The value of the component is shown in Table 4 .
VDDO = 3.3V. The QREF output is set to LVPECL style driver and the amplitude is set to 750mV.
Figure 30. Simulation Waveform at the Receiver
Table 4. Component Values
Component References Component Values
R1 100 Ohm
R2 100 Ohm
R3 100 Ohm
R4 100 Ohm
R5 200 Ohm
R6 200 Ohm
50 Ohm
R1
R3
LVPECL
0.5V
R5
Recevier
w ith Built-in
termination
and Built-in
Bias
50 Ohm
R2
R4
50 Ohm
50 Ohm
IN
nIN
VT
R6
N490 QREF
VDDO