Renesas 8V19N49 Series, Manual

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R31UH0005EU0100 Rev.1.0 Page 11
Jun 3, 2021
8V19N49x Hardware Design Guide
4. Input Output Interface
4.1 Input Termination for Reference Clock Input
The 8V19N490 reference clock input CLK/nCLK is a high-impedance differential receiver. The inverting input
nCLK has weak bias to 1.2V. The input can accept signals from a standard 3.3V LVPECL or an LVDS driver
directly without AC coupling. The board-level termination at the CLK/nCLK input is determined by the driver type.
Figure 13 and Figure 14 provide examples of input interface without AC coupling. Figure 15 and Figure 16 provide
examples of input driven by a differential driver with AC coupling. This section discusses only few examples; other
termination topologies can also be used if desired.
Figure 13. Input Termination Example – 8V19N490 Reference Clock Input CLK/nCLK, Driven by a 3.3V LVPECL Driver
Table 3. VCO PLL 2
nd
Order Loop Filter Recommendation
VCXO used in the 1
st
PLL 122.88MHz 30.72MHz
PDF, Phase detector input frequency
with doubler on 245.76MHz 61.44MHz
Feedback divider 12 48
Suggest Charge pump current setting ~ 3.2ma (typical)
Suggest range setting
600ua to 6.4ma
~3.2ma (typical)
Suggest range setting
600ua to 6.4ma
Rs 100 Ohm
Suggest range
(100 to 1k Ohm)
400 Ohm
Suggest range
(100 to 1k Ohm)
Cs 100nF 100nF
Cp ~ 40pF ~ 40pF
Clock Input
CLK
nCLK
VCC=3.3V
R4
82.5
R2
82.5
R3
133
R1
133
VCC=3.3V
Zo = 50
Zo = 50
LVPECL Driv er
VCC=3.3V