R31UH0005EU0100 Rev.1.0
Page 6
Jun 3, 2021
8V19N49x Hardware Design Guide
N is effective feedback divider.
Fvco is vco frequency.
Fpd is the phase detector input frequency.
3. Calculate Cs.
Where,
α is ratio between loop bandwidth and the zero frequency at zero, α = fc / fz, recommend α to be greater than
3.
fz is frequency at zero.
4. Calculate Cp.
Where,
fp is frequency at pole.
β is ratio between frequency at pole and loop bandwidth, β = fp/fc, recommend β greater than 3.
5. Verify maximum Phase Margin, PM.
Where,
The PM should be greater than 50 degrees.
3.2
3
rd
Order Loop Filter
This section provides design guidelines for a 3rd order loop filter. A typical 3
rd
order loop filter is displayed in
.
Fpd
Fvco
N
)
*
2
1
arctan(
b
b
PM
