DMD2401 LB/ST L-Band Satellite Modem and ODU Driver
User Interfaces
TM075 - Rev. 1.3
4-73
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Latched Alarm 2
Latched Alarm 3
Latched Alarm 4
Latched Common
Alarm
Reserved
Error Counter
Test 2047 Error
Counter
Raw BER
Mantissa
Corrected BER
Mantissa
EbNo
Offset Frequency
Test 2047 BER
Mantissa
Bit 0 = Buffer Underflow
Bit 1 = Buffer Overflow
Bit 2 = Buffer Under 10%
Bit 3 = Buffer Over 90%
Bit 4 = Rx FPGA Configuration Fault
Bit 5 = Rx LNB Fault, LBST Only
Bits 6 - 7 = Spares
(0 = Pass, 1 = Fail)
Bit 0 = IF Synthesizer Lock Detect Fault
Bit 1 = Rx Oversample PLL Lock Detect Fault
Bit 2 = Buffer Clock PLL Lock Detect Fault
Bit 3 = Viterbi Decoder Lock Fault
Bit 4 = Sequential Decoder Lock Fault
Bit 5 = Rx 2047 Test Pattern Lock Fault
Bit 6 = External Reference PLL Lock Fault
Bit 7 = Frame Sync/Multiframe Sync Fault
(0 = Pass, 1 = Fail)
Bit 0 = Buffer Clock Activity Detect Fault
Bit 1 = External BNC Activity Detect Fault
Bit 2 = Rx Satellite Clock Activity Detect Fault
Bit 3 = External Reference PLL Activity Fault
Bits 4 - 7 = Spares
(0 = Pass, 1 = Fail)
Bit 0 = -12 V Alarm
Bit 1 = +12 V Alarm
Bit 2 = +5 V Alarm
Bit 3 = Temperature Fault
Bit 4 = Interface FPGA Fault
Bit 5 = Battery Fault
Bit 6 = RAM/ROM Fault
Bit 7 = Spare
(0 = Pass, 1 = Fail)
Ignore
Unsigned Binary Value
Unsigned Binary Value
Bytes 1 - 2 = Unsigned Binary Value Raw BER
Bytes 1 - 2 = Unsigned Binary Value Corrected BER
Unsigned Binary Value, 2 Decimal Places Implied
Unsigned Binary Value in Hz, Pos/Neg Indicated Below
Bytes 1 - 2 = Unsigned Binary Value Test 2047 BER
