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EPC

®

-6315 Hardware Reference

102

Reset switch

SW1 is a reset pushbutton switch. Pressing it results in a reset of all PMC sites. 
Connecting pins 1 and 2 of J40 has the same effect.

Interrrupts 

J30, J3, J31

Mouse (industry standard pinout)

J35, J2, J37

Keyboard (industry standard pinout)

J36

Secondary PCI bus V I/O (1–2 +5V, 2–3 +3.3V)

J16

Artbiter select (Does not function)

SW1

Pushbutton reset

JP1

(RadiSys only)

J40

Reset (1–2 reset, 2–3 no reset)

J38

Primary PCI bus V I/O (1–2 +5V, 2–3 +3.3V)

J20

PCI Bus clock select 1–2 33MHz, 2–3 66MHz

J41, J?

Monarch – non Monarch selection (1–2 Monarch, 2–3 non-Monarch)

Table H-2. Connector and jumper descriptions

Table H-3. PCI device configuration

Peripheral

IDSEL

Bus

INT

Arbitration

Site1

AD28 0

A

0

Site 2 

AD29

0

B

1

Site 3

AD30

0

C

2

SCSI

AD31

0

D

3

PCI bridge

AD27

0, 1

–

4

Site 4

AD17

1

B

From PCI bridge

Summary of Contents for EPS-6315

Page 1: ...007 01361 0005 April 2005 www radisys com EPC 6315 Hardware Reference ...

Page 2: ...irit and ValuePro are trademarks of RadiSys Corporation DAVID MAUI OS 9 OS 9000 and SoftStax are registered trademarks of RadiSys Microware Communications Software Division Inc FasTrak Hawk and UpLink are trademarks of RadiSys Microware Communications Software Division Inc All other trademarks registered trademarks service marks and trade names are the property of their respective owners ...

Page 3: ...ks operating systems on your EPC 6315 4 BIOS configuration Explains how to configure the BIOS using the built in BIOS setup menus 5 Theory of operation Describes how EPC 6315 components provide a CompactPCI bus compatible embedded computer with standard PC peripherals plus PCI and ISA interfaces A Message codes Maps the addresses used for I O and by the chipset registers B Interrupts Lists DMA cha...

Page 4: ...vides guidelines for designing a a full ATX sized four PMC site circuit board to begin production test and early development using the EPC 6315 Chapter appendix Description Notes indicate important information about the product Tips indicate alternate techniques or procedures that you can use to save time or better understand the product The globe indicates a World Wide Web address The book indica...

Page 5: ...ation of all requirements of a high performance Compact PCI Central Resource and Peripheral Bridge including the North Bridge South Bridge PCI to PCI Bridge and a selected set of Super I O functions targeted at embedded PC compatible systems It supports Intel Celeron Pentium II and Pentium III processors with 66MHz 100MHz and 133MHz system bus frequencies About related EPC 6315 components Processo...

Page 6: ...EPC 6315 Hardware Reference vi ...

Page 7: ...rrier card 8 Using the 3 pin connector 9 Maintaining and upgrading the EPC 6315 10 Disconnecting the EPC 6315 PMC from the carrier card 10 Chapter 3 Operating System Installation Installing Red Hat Linux 11 Installing Red Hat on a separate computer 11 Installing Red Hat 7 3 or later over the serial port 12 Installing MontaVista Linux 14 Configure the host to boot EPC 6315 over the network 14 Extra...

Page 8: ...52 Block diagram 52 Intel Tualatin LP 512K processor 52 Speed and voltages 53 Clocking 53 RadiSys 82600 system controller 54 Power up configuration 55 Host bridge 56 Memory subsystem 56 Memory map 56 BIOS flash support 57 Dual PCI bus architecture 58 Local PCI bus 59 PCI Ethernet controller 59 PCI interrupts 59 IDE controller flash disk 60 RTC 60 Serial port 60 Keyboard and mouse controller 60 Pow...

Page 9: ...r card design PrPMC connectors Jn1 and Jn2 85 General 85 Power 85 PCI 85 Jn1 86 Clocking 86 Arbitration 86 Jn2 86 Processor PMC 86 RadiSys defined PrPMC connector Jn4 86 IDE 86 Keyboard and mouse 86 Serial port 87 Clocking 87 Arbitration 87 RTC battery 87 Mechanical and thermal design 87 Power consumption 87 Airflow 87 Maximum ambient temperature 88 Carrier card schematic samples 88 Appendix H EPC...

Page 10: ...PC 6315 connectors 67 Figure E 1 Flash chip memory addresses 79 Figure F 1 Flash chip configuration 81 Figure F 2 Flash chip re programming process flow 82 Figure H 1 Block diagram 101 Tables Table 1 1 Environmental specifications 4 Table 1 2 Additional EPC 6315 specifications 5 Table 5 1 Power up configuration settings 55 Table 5 2 Memory map 56 Table 5 3 PCI device configuration 59 Table 5 4 Pow...

Page 11: ...z PSB and 133MHz memory bus For maximum flexibility the EPC 6315 leverages the dual mode PCI to PCI bridge capability of the RadiSys 82600 to automatically configure the bridge based on the strapping of the slot on the baseboard This capability allows the EPC 6315 to become a Monarch PrPMC and provide PCI bus enumeration and service interrupts on the PCI bus or a non Monarch PrPMC and function as ...

Page 12: ...us architecture Monarch and non Monarch capability on external PCI bus Memory controller with direct BIOS flash support Two 82C59 interrupt controllers 82C54 timer counter 74LS612 address mapper PS 2 compatible keyboard mouse port SMBus host interface Two 82C37 DMA controllers Real time clock COM port support with 16550 compatible UART Integrated watchdog timer Clock generator and SDRAM clock buff...

Page 13: ...BASE T Ethernet connector To simplify network connections this connector is available on the front panel Compact flash socket Accommodates a Type I compact flash card With the ability to accept a Type I Compact Flash device the EPC 6315 can be a completely self standing processor in any application Specifications Environmental The EPC 6315 meets the following environmental specifications The EPC 6...

Page 14: ...ycle Storage 0 04g2 Hz from 5 to1000 Hz random 10 min per sweep cycle Shock un packaged Operating 5g 11ms half sine Storage 15g 11ms half sine MTBF 309 298 hours at 50ºC using Bellcor Issue 6 Immunity ESD1 Operating All performance criteria from IEC 1000 4 2 EN61000 4 2 1995 8KV direct contact performance criteria B 15 KV air discharge performance criteria B Radiated1 Operating Performance criteri...

Page 15: ...analysis for the CPU board on this carrier Table 1 2 Additional EPC 6315 specifications Characteristic Value Mechanical Dimensions1 74 0 mm x 149 00 mm Height component side First 31mm Remainder 9 5mm 4 7mm maximum Height solder side2 3 5mm this includes the 1 6mm board thickness Thickness 1 6 mm Component surface to host component surface 10 mm Heat sink Provides sufficient cooling for the CPU wh...

Page 16: ...EPC 6315 Hardware Reference 6 ...

Page 17: ...on lock connector at the shelf s lower left Remove the blade from its antistatic bag only in a static free environment Avoid touching printed circuits connector pins and components Where possible hold the blade only by its edges or mounting hardware Make the least possible movement with your body to minimize electrostatic charges created by contact with clothing fibers carpet and furniture Keep on...

Page 18: ...n the carrier card as shown below To install a PMC module 1 Remove and save any blank faceplate from the PMC slot in the carrier card faceplate 2 Position the PMC bezel through the PMC slot on the front panel 3 Push the rear connectors into the carrier card 4 Insert and tighten the screws on the back of the carrier card Figure 2 1 Installing a PMC module 3 2 4 ...

Page 19: ... 3 pin connector 1 Attach the cable to the 3 pin connector and your terminal 2 Start a terminal emulation program such as Hyperterm or Telix using these settings Baud rate 115200 Parity None Data bits 8 Stop bits 1 Flow control None You can now access the BIOS setup program using the methods described in Chapter 4 BIOS configuration You must construct this cable RadiSys does not supply a cable for...

Page 20: ... following section describes how Disconnecting the EPC 6315 PMC from the carrier card To separate the EPC 6315 from the carrier card 1 Remove screws on the back of the carrier card 2 Pull the boards apart while keeping them parallel Continue applying force until the connectors completely disengage After performing maintenance and or upgrades replace the EPC 6315 as described in Installing the EPC ...

Page 21: ... Ensure that the hard drive is the master on the primary cable 2 Power on the system insert the Red Hat bootable CD and install Linux with the configuration you desire 3 Reboot the system and log in at the Linux command prompt as root For MV Linux LSPs contact MontaVista at this URL http www mvista com For VxWorks BSPs contact RadiSys or WindRiver http www windriver com http www radisys com For in...

Page 22: ...able CD ROM 3 Modify the BIOS settings to boot the EPC 6315 from the CD ROM A Press F2 to enter the BIOS Setup program see page 23 B Make the CD ROM the first device the EPC 6315 tries to boot from by moving the CD ROM to the top of the list in the Boot menu see page 46 File Instructions etc inittab 1 Change the first TTY configuration line to read 1 2345 respawn sbin mingetty ttyS0 115200 vt100 2...

Page 23: ... files 8 Write the changes to the master boot record by entering this command at the command prompt lilo 9 Reboot the system 10 Change the baud rate A During reboot press F2 to enter the BIOS Setup program see page 23 B Change the console and terminal baud rates to 115200 bps C Press F10 to save each change The system boots over the serial port at 115200 bps then displays the Linums login prompt F...

Page 24: ...lied LSP archive to a work area Configure DHCP To configure DHCP as root 1 Make sure a DHCP server is installed and that the following file exists If the file does not exist create an empty one using the Unix touch command 2 Edit the DHCP daemon configuration file A Add the following configuration into your etc dhcpd conf file allow bootp allow booting subnet SubAddress netmask NetAddress default ...

Page 25: ...s xx xx xx xx xx xx IPAddress The target s IP address consisting of four numbers from 0 255 separated by dots periods 3 Restart dhcpd by entering this command etc rc d init d dhcpd restart The DHCP daemon is required to service BOOTP requests when booting the target To run the DHCP daemon on the host on every boot enter this command chkconfig dhcpd on DHCP is now configured Configure TFTP To confi...

Page 26: ...estart 4 Stop any any TFTP daemons that have not timed out by entering this command killall in tftpd Configure NFS To configure NFS as root 1 Add this line in etc exports opt mvlcge devkit x86 pentium3 target rw no_root_squash no_all_squash 2 Stop then start the NFS daemon by entering these command etc rc d init d nfs stop etc rc d init d nfs start 3 Set the NFS daemon to run during every boot by ...

Page 27: ...t 5 Log in as root Install MontaVista Linux to a hard drive Creating a bootable hard drive or CompactFlash requires that you network boot a kernel and NFS a filesystem as described in the previous section You then attach a bootable media device prepare a filesystem on it and copy the filesystem over NFS 1 Prepare the bootable media A Attach a CompactFlash into the front panel slot or attach an IDE...

Page 28: ...mmands cp aR bin mnt cp aR boot mnt cp aR dev mnt cp aR etc mnt cp aR home mnt cp aR lib mnt cp aR opt mnt cp aR root mnt cp aR sbin mnt cp aR tmp mnt cp aR usr mnt cp aR var mnt mkdir mnt mnt mkdir mnt proc 3 On your host copy the bzImage kernel you created in step 2 of Network boot the kernel on page 16 to root On the EPC 6315 terminal copy this image to mnt boot 4 Change the current root to the...

Page 29: ... or hard drive Requirements To install a VxWorks BSP on an EPC 6315 you will need The EPC 6315 VxWorks BSP from RadiSys You can request it from RadiSys by sending email to support radisys com A DOS boot disk with fdisk and format utilities Two DOS formatted floppy diskettes A 10MB or greater CompactFlash or hard drive A CF to IDE standard hard drive connector adapter needed only if you plan to ins...

Page 30: ... command mkboot a bootrom_uncmp D Copy the vxsys com file to the floppy diskette Typically this file resides at c tornado host x86 win32 bin E Copy the VxWorks st image to the boot floppy by entering copy vxWorks st a If this file does not fit on the boot floppy copy vxWorks st to a different floppy F Label this as the EPC 6315 bootdisk 4 Prepare the device to be the boot device A On a separate co...

Page 31: ...ey to display a prompt then enter c to configure your system Set IP information to the values you desire To have VxWorks automatically initialize the on board Ethernet enter fei into the other field After you enter the parameters the configuration is saved automatically to flash C Boot VxWorks by entering Command Description vxsys c Installs the master boot record and initial bootloader copy bootr...

Page 32: ...EPC 6315 Hardware Reference 22 ...

Page 33: ... displays the Boot First pop up menu after POST completes You can use this menu to override for only this boot the boot options This menu includes the same options as the Boot Menu s top level For information about the options see Boot menu on page 46 BIOS setup screens BIOS Setup program The EPC 6315 s BIOS includes a setup program that displays and modifies the system configuration The EPC 6315 ...

Page 34: ... Advanced menu PCI Configuration sub menu PrPMC customizations sub menu PCI PNP ISA UMB Region Exclusion sub menu PCI PNP ISA IRQ Resource Exclusion sub menu Cache Memory sub menu Console Redirection sub menu I O Device Configuration sub menu Boot menu None Exit menu CMOS Save Restore sub menu To Do Display a menu Press the left or right cursor arrow keys and press the Enter key If you use the arr...

Page 35: ...e fields in each menu and sub menu are explained below Additional help information is available in the help area on the BIOS setup screen Field Description System Time System Date Sets the system time and date To change these values go to each field and enter the desired value Press the tab key to move from hour to minute to second or from month to day to year The default system time is 00 00 the ...

Page 36: ...oot process For more information see Boot menu on page 46 System memory Displays the amount of conventional memory below 1MB This field is not editable no user interaction is required Extended memory Displays the amount of extended memory above 1MB This field is not editable no user interaction is required Field Description ...

Page 37: ...up existing formatted disks Note that you must use the same parameters used when the disk originally was formatted You must select an option for the Type field then enter the specific cylinder head and sector information listed on the label attached to the drive at the factory Figure 4 2 Primary Master Slave sub menus Main F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu En...

Page 38: ...pact flash cards CD ROM Select this option if you have a CD ROM drive 1 39 Select this option to specify a pre determined hard disk drive type These drive types found in the FDPT Fixed Disk Parameter Table are seldom used RadiSys recommends that you avoid using this option Note For disks not supplied consult the product documentation When finished press the ESC key to return to the Main Setup menu...

Page 39: ...tains a value of User or 1 39 Autotyping may change this value if the hard disk reports that it supports block accesses LBA Mode Control Determines how the System BIOS references hard disk data You can use this option only if both the hard disk being configured and the operating system support LBA Logical Block Addressing Autotyping may change this value if the hard disk reports that it supports L...

Page 40: ...fer modes that the hard disk reports it supports The fast DMA modes take full advantage of the onboard bus mastering hard disk controller and should yield the highest performance when used in conjunction with multitasking operating systems that support it Note This field displays only when the Type field contains a value of None Ultra DMA Mode Selects the Ultra DMA Mode that the System BIOS uses t...

Page 41: ... Disk Access Mode DOS Local Bus IDE adapter Enabled Main Boot Exit PhoenixBIOS Setup Utility Advanced Tab Shift Tab or Enter selects field Item Specific Help Field Description Installed OS Identifies the OS you plan to use on this system Identifying the OS determines how much initialization the BIOS performs You can select one of these Other default The Plug and Play BIOS completes PCI initializat...

Page 42: ...se to redirect console output For more information see Console Redirection sub menu on page 43 I O Device Configuration sub menu Displays a menu that you use to configure peripheral devices For more information see I O Device Configuration sub menu on page 45 Large Disk Access Mode Specifies whether MS DOS systems can use hard disks up to 8GB 1024C x 255H x 63S without special drivers or LBA If th...

Page 43: ...Region Exclusion PCI PNP ISA ISA IRQ Resource Exclusion PCI Configuration Advanced Field Description PrPMC Customizations sub menu Displays a menu that you use to customize PrPMC options For more information see PrPMC customizations sub menu on page 34 PCI PNP ISA UMB Region Exclusion Displays a menu that you use to control the exclusion of PCI and ISA Upper Memory Block UMB regions For more infor...

Page 44: ...it 1 Use system BIOS Settings SCSI Controller Disabled PrPMC Customization Advanced Field Description Backplane I O Determines how the backplane implements I O You can select one of these Disabled default The local PCI bus services all I O accesses Enabled I O addresses pass through to the backplane PCI bus Backplane Ready Determines how resources are assigned during boot You can select one of the...

Page 45: ... default F100F000 F900F800 F300F200 FB00FA00 F500F400 F000A000 F700F600 SCSI Controller Determines the state of the SCSI controller on the carrier card You can select one of these Disabled default Disables the controller Enabled Enables the controller Note If the card does not have a SCSI controller this option has no effect Field Description ...

Page 46: ...Select Sub Menu F10 Save and Exit PhoenixBIOS Setup Utility Advanced Tab Shift Tab or Enter selects field Item Specific Help C800 CBFF Available CC00 CFFF Available D000 D3FF Available D400 D7FF Available D800 DBFF Available DC00 DFFF Available PCI PNP ISA UMB Region Exclusion Field Description Memory Regions Determines the use of each UMB region You can select one of these Available default Makes...

Page 47: ...nter selects field Item Specific Help IRQ 3 Available IRQ 4 Available IRQ 5 Available IRQ 7 Available IRQ 9 Available IRQ 10 Available IRQ 11 Available IRQ 12 Available IRQ 15 Available PCI PNP ISA IRQ Resource Exclusion Field Description Interrupts Determines the use of each interrupt You can select one of these Available default for IRQs 3 4 5 9 and 12 Makes the ISA IRQ available for PCI use Res...

Page 48: ...e Back Cache A000 AFFF Disabled Cache B000 BFFF Disabled Cache C800 CBFF Write Protect Cache CC00 CFFF Disabled Cache D000 D3FF Disabled Cache D400 D7FF Disabled Memory Cache Field Description Memory Cache Determines whether to use L2 memory caching You can select one of these Enabled default L2 memory caching occurs Disabled L2 memory caching does not occur Cache System BIOS Area Determines wheth...

Page 49: ...nes on all processors on the bus to be invalidated Speculative reads are allowed uncached The system does not cache memory Cache Extended Memory Area Determines how the system caches extended memory You can select one of these Write Back default Writes and reads to and from system memory are cached then written to system memory when you perform a write back operation Select this option to reduce b...

Page 50: ...en to system memory when you perform a write back operation Select this option to reduce bus traffic by eliminating unnecessary writes to system memory This option provides the best performance but requires that all devices that access system memory on the system bus be able to snoop memory accesses to ensure system memory and cache coherency Write Through Writes and reads to and from system memor...

Page 51: ...erformance but requires that all devices that access system memory on the system bus be able to snoop memory accesses to ensure system memory and cache coherency Write Through Writes and reads to and from system memory are cached Select this option for frame buffers or when there are devices on the system bus that access system memory but do not perform snooping of memory accesses Write Protect Re...

Page 52: ... back operation Select this option to reduce bus traffic by eliminating unnecessary writes to system memory This option provides the best performance but requires that all devices that access system memory on the system bus be able to snoop memory accesses to ensure system memory and cache coherency Write Through Writes and reads to and from system memory are cached Select this option for frame bu...

Page 53: ...ne Console connection Direct Continue C R after POST On Console Redirection Advanced Field Description Com Port Address Specifies the serial port to use for console redirection You can select one of these On board COM A default The system uses COM A for rediretion Disabled The system does not redirect input Baud Rate Specifies the baud rate at which the COM port operates You can select one of thes...

Page 54: ...onsole directly to the system Via modem Connects the console to the system via a modem Continue C R after POST Determines whether console redirection occurs after BIOS hands off to the OS You can select one of these On default Console redirection continues as and after the OS loads Off Console redirection stops when the OS starts to load Field Description ...

Page 55: ...eld Item Specific Help Serial port A Auto I O Device Configuration Advanced Field Description Serial Port A Configures the selected serial port You can select one of these Auto default Either the BIOS or OS configures the serial port Disabled The serial port COM A is not configured If you select this option you must also set the Com Port Address option on the Console Redirection sub menu to On boa...

Page 56: ...ot device sub menus under all respective device types press the Ctrl and Enter keys at the same time To display a sub menu that lists all devices of a specified type available on the system highlight the device type and press the Enter key If more than one device of that type exists use the and keys to change the boot order within the given device type When two devices appear in a class only the t...

Page 57: ...xclamation point displays to the left of enabled devices To disable a device highlight the device then press the Shift and 1 keys again Field Description Boot order Determines the boot order of boot devices This is the default boot order 1 Removable Devices 2 Hard Drive 3 ATAPI CD ROM Drive 4 MBA UNDI Bus 0 Slot 14 ...

Page 58: ... entered and exits the Setup program The new values load and the system reboots Exit Discarding Changes Discards the changes you just made and reverts to the BIOS as it was before you entered the BIOS Setup program The system boots with the old values Load Setup Values Resets the BIOS values to the original default values set at the factory before any suppliers or other end users made changes Disc...

Page 59: ...tion CMOS Restore Condition Determines the conditions under which the BIOS restores CMOS RAM from the FBD when booting You can select one of these CMOS Corruption Never default Always Select this option if your system does not have battery backup Save CMOS to Flash Immediately saves current settings in the Setup program to CMOS RAM and into the FBD This process may take several seconds to complete...

Page 60: ...EPC 6315 Hardware Reference 50 ...

Page 61: ...an run DOS 6 22 VxWorks 5 4 and MontaVista Linux Carrier Grade Edition 2 1 operating systems The design for the external interface PCI bus is compatible with the PCI Specification Revision 2 2 When reading this file online you can immediately view information about any EPC 6315 topic by placing the mouse cursor over the topic name and clicking For MV Linux LSPs contact MontaVista at this URL http ...

Page 62: ...essor offers high performance and low power consumption The processor s internal speed is 800 MHz with a 133 MHz system bus frequency at 1 15 V core voltage Front panel RTC battery Figure 5 1 EPC 6315 block diagram Intel Tualatin LP 512K processor IDE CompactFlash socket Ethernet port Backplane PCI Keyboard mouse arbitration PCI Ethernet controller Host bus PCI clock Keyboard mouse reflash COM1 he...

Page 63: ...ds the AGTL termination voltage This is accomplished using a resistor divider A high efficiency switching regulator produces the appropriate processor VCore and Vcct required Maximum power draw for the EPC 6315 on an 800 MHz Tualatin 512K LP processor is 17 0W EPC 6315 power consumption varies with activities the EPC 6315 performs Clocking Clock synthesizer The EPC 6315 uses an AMI clock generator...

Page 64: ...endent local and backplane PCI buses with integrated virtual PCI to PCI bridge Provides isolation between local and backplane peripherals Asynchronous operation of both PCI buses Supports concurrent EPC 6315 local PCI and backplane PCI transactions Local PCI bus 33MHz interface 3 3V and 5V PCI 2 2 compliant 5 BREQ BGNT pairs Backplane PCI BPCI bus PCI Rev 2 2 3 3V and 5V 33 66MHz interface complia...

Page 65: ... down General purpose I O pins are used for bus arbitration signals BREQ 6 3 and BGNT 6 3 Default GPIO ADDR2 and ADDR5 Combination determines Monarch non Monarch mode as shown below ADDR2 ADDR5 Mode 0 0 Central resource with arbiter 1 1 0 Peripheral non Monarch 0 1 Central resource without arbiter Monarch 1 1 Not allowed ADDR3 10K pull down The Real Time Clock RTC is enabled Default Enable ADDR4 1...

Page 66: ... the 82600 SMBus To determine the computer s memory configuration BIOS queries the SPD during POST SPD in the system with 256 MB or 512 MB memory is assigned to address 010 I2C Memory map Physical address space for the system is managed by the 82600 as set up by the System BIOS That configuration is defined in the following table 1 Applies to systems with 256M memory the EPC6315 800 256 2 Applies ...

Page 67: ...ip see Appendix F Re programming the flash chip The BIOS Setup program can save and restore a CMOS configuration using storage in the FBD This feature is useful because the EPC 6315 does not have battery on board A battery could be installed on the carrier card and connected to the EPC 6315 via pin 62 of the optional JN4 connector The BIOS CSR function automatically saves and restores CMOS RAM con...

Page 68: ...mode it is possible to configure the EPC 6315 to present some or all of its local memory to the BPCI bus The System BIOS BIOS Setup program provides Access to memory remapping registers within the 82600 These Setup tokens are visible in both Monarch and non Monarch modes but are ignored by the BIOS in Monarch mode In the Setup program you can use either the default BIOS settings or any of several ...

Page 69: ... front panel RJ45 connector The controller uses local PCI interrupt A REQ0 GNT0 arbitration pairs and has a standard PCI 2 1 compliant configuration space allowing system identification and configuration The PHY enables direct connection to the network media using a 25 MHz 25 ppm crystal to derive its internal transmit digital clocks An Intel defined magnetics interfaces the PHY with the RJ45 conn...

Page 70: ...b menu on page 49 Serial port The 82600 includes two 16C550 UARTs You can enable one as COM1 and the other as COM2 You can configure the COM1 port to support IRDA at data rates up to 115Kbaud As in a standard PC COM1 is accessed in the I O address space at 0x3f8 3ff and signals interrupts on IRQ4 The configurable port shares eight pins with the SDRAM ECC pins The COM2 port pins are not available e...

Page 71: ...de up to 25A output current per channel The current limit is set to 15 A for VCORE and to 5 A for VCCT The expected maximum load current is 7A for VCORE A precision voltage reference in conjunction with a voltage comparator provides monitoring of the 5V and 3 3V supplies The outputs of the comparators connect directly to the soft start inputs for the switching regulator that creates VCORE and VCCT...

Page 72: ...yte chunk needs to require at least 2 host addresses to complete the single PCI write in the host domain for example a 24 byte write that starts at address 0x80 would require two host bus writes a 16 byte starting at 0x80 and an 8 byte starting at 0x90 the host bus doesn t support 24 byte writes 5 I O queue depth I O queue depth must be set to 1 or 8 6 L2 Disabling L2 makes it more difficult to ex...

Page 73: ...ERR_EXT_MEM_FAIL ERR_MEM_TYPE_MIX ERR_MEM_ECC_SINGLE ERR_MEM_ECC_MULTIPLE ERR_MEM_DECREASED ERR_DMI_MEM_FAIL POS timeout errors 240h ERR_POS CMOS errors 250h 251h ERR_CMOS_BATTERY ERR_CMOS_CHECKSUM Timer errors 260h ERR_TIMER_FAILED Real time clock errors are x70h 270h ERR_RTC_FAILED Invalid date time 271h ERR_RTC_INV_DATE_TIME Configuration errors 280h 281h ERR_CONFIG_FAILED ERR_CONFIG_MEMORY NVR...

Page 74: ...1h 2E2h 2E3h 2E4h 2E5h 2E6h 2E7h 2F0h 2F1h 2F2h 2F3h 2F4h 2F5h 2F6h 2F7h ERR_IO_ADDRESS ERR_IO_COM ERR_IO_LPT ERR_IO_CONFLICT ERR_IO_UNSUPPORTED ERR_IO_IRQ ERR_IO_IDE ERR_IO_FDD ERR_OTHER_CPUID ERR_OTHER_BIST ERR_OTHER_BSP ERR_OTHER_AP RR_OTHER_CMOS ERR_OTHER_DMA ERR_OTHER_NMI ERR_OTHER_FAILSAFE Class Number Name ...

Page 75: ...IRQ41 2 COM1 internal connection IRQ52 IRQ6 IRQ7 IRQ81 Real time clock internal connection IRQ91 2 SMBus reset switches power management DMA BIST via Serial IRQ IRQ102 Soft reset is imminent via serial IRQ from Watchdog IRQ112 IRQ121 2 PS 2 mouse internal connection IRQ13 Numeric coprocessor FERR internal connection IRQ141 Primary IDE channel IRQ152 NMI1 When SERR or IOCHK is asserted software con...

Page 76: ...EPC 6315 Hardware Reference 66 ...

Page 77: ...s page Connector locations 67 CompactPCI connector 68 J1 connector 68 PMC connectors 69 Jn1 connector 69 Jn2 connector 70 Jn4 connector 71 Ethernet port 75 CompactFlash socket 75 3 pin connector 76 3 pin connector 76 Figure C 1 EPC 6315 connectors Ethernet port Jn4 Jn2 Jn1 CompactFlash socket 3 pin connector Signals used for a purpose other than that identified in the appropriate specification are...

Page 78: ...5 BRSV11 BRSV11 RST GND GNT GND 6 REQ GND 3 3V CLK AD 31 GND 7 AD 30 AD 29 AD 28 GND AD 27 GND 8 AD 26 GND V I O AD 25 AD 24 GND 9 C BE 3 IDSEL AD 23 GND AD 22 GND 10 AD 21 GND 3 3V AD 20 AD 19 GND 11 AD 18 AD 17 AD 16 GND C BE 2 GND 12 14 Key area 15 3 3V FRAME IRDY BD_SEL7 TRDY GND 16 DEVSEL GND V I O 2 6 STOP LOCK GND 17 3 3V IPMB_CLK IPMB_DAT GND PERR GND 18 SERR GND 3 3V PAR C BE 1 GND 19 3 3...

Page 79: ... C 2 Jn1 connector pin definitions Pin Signal Signal Pin 1 TCK 12V 2 3 GND INTA 4 5 INTB INTC 6 7 Busmode1 5V 8 9 INTD PCI Reserved 10 11 GND 3 3V 12 13 PCICLK GND 14 15 GND GNT0 16 17 REQ0 5V 18 19 V I O AD 31 20 21 AD 28 AD 27 22 23 AD 25 GND 24 25 GND C BE 3 26 27 AD 22 AD 21 28 29 AD 19 5V 30 31 V I O AD 17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK NC 40 41 Sdone NC SBO NC ...

Page 80: ... Busmode4 NC 16 17 PME GND 18 19 AD 30 AD 29 20 21 GND AD 26 22 23 AD 24 3 3V 24 25 IDSEL AD 23 26 27 3 3V AD 20 28 29 AD 18 GND 30 31 AD 16 C BE 2 32 33 GND IDSELB NC 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR NC 42 43 C BE 1 GND 44 45 AD 14 AD 13 46 47 M66EN AD 10 48 49 AD 08 3 3V 50 51 AD 07 GNT2 NC 52 53 3 3V REQ2 NC 54 55 PMC Reserved GND 56 57 PMC Reserved ENUM NC 58 59 GN...

Page 81: ... Pin 1 RST D8 2 3 D7 D9 4 5 D6 D10 6 7 D5 D11 8 9 D4 D12 10 11 D3 D13 12 13 D2 D14 14 15 D1 D15 16 17 D0 GND 18 19 GND CS0 20 21 IOW CS1 22 23 IOR A0 24 25 IORDY A1 26 27 IRQ14 A2 28 29 GND GND 30 31 USBP1 USBP0 32 33 USBP1 USBP0 34 35 GND GND 36 37 KCLK KDATA 38 39 COM DTR COM DSR 40 41 COM DCD COM RxD 42 43 COM TxD COM CTS 44 45 COM RTS COM RI 46 47 5V MDATA 48 49 GNT3 REQ3 50 51 GNT4 REQ4 52 53...

Page 82: ...onding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector During reset High After reset High During POS High CS1 O Primary disk chip select for 3F0 3F7 range For ATA control register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the cor...

Page 83: ... signals are configured for Primary Master and Primary Slave this signal is used for the Primary master connector GNT 6 3 O PCI bus grant Active los assertion indicates that the PCI bus is granted to a particular device IOR O Primary disk to read In normal IDE this is the command to the IDE device that is may drive data onto the PDD 15 0 lines Data is latched by PIIX4 on the negation edge of PDIOR...

Page 84: ...ite cycle this signal is used as the DMARDY signal which is negated by the drive to pause Ultra DMA 33 transfers If IDE signals are configured for Primary and Secondary this signal connects to the Primary IDE connector s corresponding signal If the IDE signals are configured for Primary Master and Primary Slave thie signal is used for the Primary Master connector This is a Schmitt triggered input ...

Page 85: ... TERM 3 Receive 8 TERM 4 TERM 9 Shield 5 TERM 10 Shield Table C 7 Compact Flash socket pin definitions Pin Signal Pin Signal 26 CD1 GND 1 GND 27 D11 2 D03 28 D12 3 D04 29 D13 4 D05 30 D14 5 D06 31 D15 6 D07 32 CE2 7 CE1 33 VS1 NC 8 A10 GND 34 IORD 9 OE GND 35 IOWR 10 A09 GND 36 WE 3 3V 11 A08 GND 37 RDY_BSY IRQ 12 A07 GND 38 3 3V 13 3 3V 39 MASTER 14 A06 GND 40 VS2 NC 15 A05 GND 41 RESET 16 A04 GN...

Page 86: ...XD 2 COM1 RXD 3 GND 1 3 Item Part number 3 pin connector Molex receptacle 51021 0300 Female crimp terminal Molex 50058 8100 RS232 connector Standard RS323 female DB 9 serial connector Recommended cable Belden 8643 Round 3 Conductor 30 Gage or Molex Series 6800 Flat 3 Conductor 28 Gage cut to desired length i e 8 16 inches EPC 6315 EPC 6315 Molex housing with LRamp PN 51021 0300 Molex termination p...

Page 87: ... 0 failed 4 Diskette error Floppy type does not match setup 5 I O chip error I O conflicts exist for serial and parallel ports floppy hard disk any or all 6 Other error IRQ conflict unsupported COM port configuration keyboard locked Pentium cooling fan has failed The System BIOS prints an error message but does not halt when it encounters the following error conditions Configuration error Previous...

Page 88: ...EPC 6315 Hardware Reference 78 ...

Page 89: ...dress Offset 0x0000 0000 0xFFFE 0000 128 Kbyte BLOCK 31 BIOS 3E0000 0xFFFC 0000 128 Kbyte BLOCK 30 BIOS 3C0000 0xFFFA 0000 128Kbyte BLOCK 29 BIOS 3A0000 0xFFF8 0000 128 Kbyte BLOCK 28 ESCD 380000 0xFFF6 0000 128 Kbyte BLOCK 27 CSR 360000 0xFFF5 FFFF 0xFFC0 0000 63 128 Kbyte BLOCKs1 35FFFF 0000 0000 For information about re programming the flash chip s contents see Appendix F Re programming the fla...

Page 90: ...EPC 6315 Hardware Reference 80 ...

Page 91: ...and clicking About the flash chip The EPC 6315 flash chip contains these major sections For information about Go to this page About the flash chip 81 About re programming the flash chip 82 Before you begin 82 Creating a Flash Boot diskette 83 Using phlash exe to re program the flash chip 84 Figure F 1 Flash chip configuration Initializes the hardware and finds a device from which to bootload You u...

Page 92: ...cess The rest of this chapter includes detailed instructions for each task Before you begin Ensure that you have the following Minimum 2 MB of DRAM to run the re flash program A 3 5 1 44 MB hard drive attached to or installed in the system Access to the RadiSys web site Use extreme caution when re programming the flash chip Perform on any machine Figure F 2 Flash chip re programming process flow D...

Page 93: ...a directory on your hard drive When unzipped verify that these files required to re program the flash chip are copied successfully to your hard drive Filename Description readme txt Describes the transmittal and includes instructions and issues that arose too late to include in other documentation bios rom A binary file that contains the BIOS image and Boot Block phlash exe The program that re pro...

Page 94: ...e system 3 Start the re programming process For example c phlash When finished the phlash program displays a message then automatically reboots the system For detailed information about creating a Flash Boot diskette see Before you begin on page 82 If using only console redirection messages do not display You must wait approximately three minutes for the reflash to complete ...

Page 95: ...in 12 and 12V are not used on the board and only require the high frequency decoupling cap VI O requires a a high frequency decoupling cap on each pin VI O can be either 5V or 3 3V PCI Design interrupt and IDSEL routing to match the PCI to PCI Bridge Architecture Specification Revision 1 1 The LOCK SDONE and SBO signals are not used you can leave them unconnected Tie JTAG signals to an inactive st...

Page 96: ... For more information see the Jn4 arbitration section The The EPC 6315 does not use the RSTOUT NC signal However RadiSys recommends that you bus this signal to all PrPMC sites The RadiSys PrPMC does not use the serial interrupt mechanism However RadiSys recommends tying SERIRQ signal through a resistor to VI O RadiSys defined PrPMC connector Jn4 IDE RadiSys recommends placing series termination re...

Page 97: ... from the 3V power supply with a low leakage Schottky diode RadiSys provides this series resistor and a low leakage Schottky resistor on the EPC 6315 Mechanical and thermal design The two mounting holes for the front panel are electrically isolated from the rest of the board The back mounting holes near Jn1 and Jn4 are connected to logic ground The reference schematics do not show this properly co...

Page 98: ... card If this conflict with your carrier card s requirements contact RadiSys Maximum ambient temperature Maximum ambient temperature is 50 C at the EPC 6315 Carrier card schematic samples The remainder of this appendix includes sample schematics that you can use as reference when designing a carrier card These schematics Include a series resistor and diode between the battery and the Jn4 of the PM...

Page 99: ...Appendix G Carrier card design 89 ...

Page 100: ...o not install are not to be included in any bill of materials for any of the variants unless specifically noted below 3 Add 5 shunts to all BOM s 40 0039 00 4 Add 4 batteries to all BOM s 17 0025 00 1 2 74K pullup resistors to VIO on arbitration signals to all Jn1 signals 2 Jn4 diode and series resistor should be removed Connect battery directly to pin 3 The ground scheme is incorrect at the back ...

Page 101: ...E2 3 4 5 6 PCI STOP 3 4 5 6 8 PCI LOCK 3 4 6 8 PCI C BE1 3 4 5 6 PCI C BE3 3 4 5 6 PCI IRDY 3 4 5 6 8 PCI PERR 3 4 5 6 8 PCI SERR 3 4 5 6 8 PCI ACK64 3 4 8 PCI REQ64 3 4 8 PCI M66EN 3 4 8 PMC RSTOUT 3 4 7 PCI RST 3 4 5 6 8 9 12 3 4 7 9 VCC 3 3 3 3 3 3 VCC VCC VCC 3 3 VCC VCC VCC 3 3 VCC VCC VCC VCC 3 3 3 3 SHIELD SHIELD SHIELD SHIELD VCC R68 33 2 0603 R66 R90 221 0603 R8 PMC JN1 J6 BRDBRD 2X32 F 1...

Page 102: ...5 6 8 PCI LOCK 2 4 6 8 PCI C BE0 2 4 5 6 12 2 4 7 9 PCI DEVSEL 2 4 5 6 8 PCI REQ1 8 PCI PAR 2 4 5 6 PCI GNT1 8 PMC RSTOUT 2 4 7 PCI TRDY 2 4 5 6 8 PCI AD 0 31 2 4 5 6 VIO 2 4 8 PCI RST 2 4 5 6 8 9 12 2 4 7 9 3 3 VCC 3 3 3 3 VCC VCC VCC VCC VCC VCC VCC 3 3 SHIELD SHIELD SHIELD SHIELD VCC 3 3 3 3 R190 L51 L7 PMC JN1 J31 BRDBRD 2X32 F 1MM 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 4...

Page 103: ...3 5 6 8 9 VIO 2 3 8 12 2 3 7 9 3 3 3 3 VCC VCC 3 3 C165 0603 0 1UF PMC JN1 J30 BRDBRD 2X32 F 1MM 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 51 53 55 57 59 61 63 52 54 56 58 60 62 64 TCK GND1 INTB BUSMODE1 INTD GND2 CLK GND3 REQ V I O 1 AD 28 AD 25 GND4 AD 22 AD 19 V I O 2 FRAME GND5 DEVSEL GND6 SDONE ...

Page 104: ...0 SD 11 SD 12 SD 13 SD 14 SD 15 SD 0 SD 1 SD 2 SD 3 SD 4 SD 5 SD 6 SD 7 SD 8 SD 9 SD 10 SD 11 SD 12 SD 13 SD 14 SD 15 SDP 0 SDP 0 SDP 1 SDP 1 SRST SRST SSEL SSEL SBSY SBSY SREQ SREQ SIO SIO SCD SCD SMSG SMSG SATN SATN SACK SACK RBIAS RBIAS MCE MOE MWE MAS0 MAS1 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 GPIO2 IRQ REQ DIFFSENS GPIO0 FETCH GPIO1 MASTER GPIO3 GPIO4 VSS_J10 VSS_K10 VSS_L10 VSS_M10 VSS_J1...

Page 105: ... IRDY 2 3 4 5 8 PCI PAR 2 3 4 5 PCI TRDY 2 3 4 5 8 PCI PERR 2 3 4 5 8 PCI LOCK 2 3 4 8 PCI REQ4 8 SPCI GNT0 7 SPCI C BE0 7 SPCI PAR 7 SPCI IRDY 7 SPCI TRDY 7 SPCI DEVSEL 7 SPCI STOP 7 SPCI PERR 7 SPCI SERR 7 SPCI RST 7 CLK SPCI0 7 SPCI REQ0 7 SPCI FRAME 7 SPCI C BE1 7 SPCI C BE2 7 SPCI C BE3 7 SPCI AD 0 31 7 SVIO 7 SPCI LOCK 7 3 3 3 3 VCC 3 3 3 3 3 3 VCC 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 E30...

Page 106: ...OUT 2 3 4 SPCI TRDY 6 SPCI AD 0 31 6 SVIO 6 SPCI RST 6 PCI INTC 2 3 4 8 PCI INTB 2 3 4 8 PCI INTA 2 3 4 8 PCI INTD 2 3 4 5 8 12 2 3 4 9 3 3 VCC 3 3 3 3 3 3 VCC 3 3 VCC VCC VCC 3 3 VCC VCC VCC 3 3 SHIELD VCC SHIELD SHIELD SHIELD VCC R171 L41 C196 0603 0 1UF R251 10K 0603 C108 10PF 0603 E8 L34 R196 C181 0603 0 1UF L47 D6 SOT23 SHT 30V 100MA 78 0239 00 1 3 2 R165 C17 37 0109 00 100UF TAN D 1 2 L22 12...

Page 107: ... CLK PCI2 4 CLK PCI5 CLK PCI3 5 CLK PCI4 6 VIO 2 3 4 PCI REQ64 2 3 4 PCI INTA 2 3 4 7 PCI LOCK 2 3 4 6 PCI INTD 2 3 4 5 7 PCI PERR 2 3 4 5 6 PCI SERR 2 3 4 5 6 PCI INTB 2 3 4 7 PCI INTC 2 3 4 7 PCI ACK64 2 3 4 PCI M66EN 2 3 4 PCI IRDY 2 3 4 5 6 PCI FRAME 2 3 4 5 6 PCI STOP 2 3 4 5 6 PCI DEVSEL 2 3 4 5 6 PCI REQ0 2 PCI GNT0 2 PCI GNT1 3 PCI GNT2 4 PCI GNT3 5 PCI GNT4 6 PCI REQ1 3 PCI REQ2 4 PCI REQ...

Page 108: ...ey Shield Shield GND GND PMC SITE Y7 CMC ON HOST 4 5 6 1 2 3 Shield1 Shield2 3VKEY NC 5VKEY NC GND1 GND2 3V key 5V key Shield Shield GND GND PMC SITE Y5 CMC ON HOST 4 5 6 1 2 3 Shield1 Shield2 3VKEY NC 5VKEY NC GND1 GND2 Y8 BARCODE Y12 FIDUCIALOSP PS 1 C38 1 2 C3 1 2 SW1 SPST THM MOM P RA 1 2 3 4 C12 1 2 C30 1 2 R270 0 0603 C21 1 2 C27 1 2 R275 221 0603 D10 RED 16 20 MA STR 2MM LED 2 1 C212 0603 0...

Page 109: ...ch selection between sites 1 and 2 Keyboard mouse serial port DB9 IDE 40 and 44 pin and battery interfaces PMC standard Jn1 Jn2 and Jn4 connectors Site 3 Clock speeds of 33MHz or 66MHz Non Monarch site PMC standard Jn1 and Jn2 interfaces no Jn4 interface LSI 53C895 SCSI Controller SCSI active termination Industry standard 68ppin SCSI connector 33MHz operation only PCI PCI bridge Provides a PMC sit...

Page 110: ...ors 1 2 4 1 ea DB9 serial port with full modem signals 1 2 4 2 ea 6 pin mini DIN keyboard and mouse connectors 1 2 4 1 Battery in a socket sites 1 2 and 4 2 3 pin jumpers for primary and secondary V I O voltage selections 5V or 3 3V 1 3 pin jumper for clock speed selection 33MHz or 66MHz Selecting 66MHz automatically disables SCSI PCI to PCI bridge and Site 4 1 2 2 3 pin jumpers for Monarch or non...

Page 111: ...bitration Power and reset Code generation and arbitration Physical interfaces The keyboard mouse serial port and IDE connectors are all common industry standard pinouts Connectors and jumpers The following table contains the list of all connectors and jumpers on the board and a description for each jumper Table H 2 Connector and jumper descriptions Item Description J43 ATX power connector industry...

Page 112: ...5V 2 3 3 3V J16 Artbiter select Does not function SW1 Pushbutton reset JP1 RadiSys only J40 Reset 1 2 reset 2 3 no reset J38 Primary PCI bus V I O 1 2 5V 2 3 3 3V J20 PCI Bus clock select 1 2 33MHz 2 3 66MHz J41 J Monarch non Monarch selection 1 2 Monarch 2 3 non Monarch Table H 2 Connector and jumper descriptions Table H 3 PCI device configuration Peripheral IDSEL Bus INT Arbitration Site1 AD28 0...

Page 113: ...here it is used to automatically configure the drive controller BDA BIOS Data Area BIOS Data Area A 256 byte block of DRAM starting at address 400H that contains data initialized and used by the System BIOS detailing the system configuration and errors encountered during POST BIOS Basic Input Output System Firmware in a PC compatible computer that runs when the computer is powered up The BIOS init...

Page 114: ...computer The chipset typically implements a DRAM controller bus interface logic and PC peripheral devices CHS Cylinders Heads Sectors A specification of disk drive operating parameters consisting of the number of disk cylinders disk drive read write heads and disk sectors CMOS Complimentary Metal Oxide Semiconductor A fast low power semiconductor RAM used to store system configuration data COM por...

Page 115: ... Mode DRAM EEPROM Electrically Erasable Programmable ROM Specifically those EPROMs which may be erased electrically as compared to other erasing methods error checking and correction A feature of the T2 chipset that enables it to detect single or multi bit errors in DRAM reads and correct single bit errors This feature requires that all banks of DRAM use x36 parity SO DIMMs ESCD Extended System Co...

Page 116: ...tion interface between system components and between the system and connected peripherals IDE Integrated Drive Electronics A hard disk drive controller interface standard IDE drives contain the controller circuitry at the drive itself as compared to the location of this circuitry on the computer motherboard in non IDE systems IDE drives typically connect to the system bus with a simple adapter car...

Page 117: ...a can be retrieved A typical computer system has more than one memory area See conventional memory and extended memory memory shadowing Copying information from an extension ROM into DRAM and accessing it in this alternate memory location Monarch mode A Processor PMC that acts as the main processing element In this mode the PPMC performs PCI bus enumeration at power up and handles interrupts from ...

Page 118: ...oard interface PQFP Plastic Quad Flat Pack A popular package design for integrated circuits of high complexity program A set of instructions a computer follows to perform specific functions relative to user need or system requirements In a broad sense a program is also referred to as a software application which can actually contain many related individual programs PS 2 Personal System 2 Computers...

Page 119: ...C is typically receives power from a small battery to retain the current time of day when the computer is powered down RS 232 A popular asynchronous bi directional serial communication protocol Among other things the RS 232 standard defines the interface cabling and electrical characteristics and the pin arrangement for cable connectors segment A section or portion of addressable memory serving to...

Page 120: ...ytes 2 40 1 099 511 627 776 bytes exactly UED User Editable Drive A feature of the NY1210 s Phoenix NuBIOS When a User type hard disk drive setting shows in the IDE Adapter Sub Menu the BIOS queries the hard disk drive for the purpose of retrieving disk geometry If the hard disk drive is capable of providing this information the BIOS uses it to automatically set up the drive for use with the syste...

Page 121: ...38 carrier card design guidelines 85 disconnecting EPC 6315 10 chipset defined 104 CMOS RAM 23 configuration byte defined 104 I O device 32 PCI 32 connectors PMC PMC Jn1 69 PMC Jn2 70 PMC Jn4 71 serial port cable 76 console redirection 34 43 Console Redirection sub menu 32 conventional memory defined 104 conventions notational iv Cylinders Heads Sectors CHS defined 104 D data area defined 103 desi...

Page 122: ...defined 107 M main menu BIOS setup 25 memory conventional defined 104 extended defined 105 flash addresses 79 random access defined 108 system defined 110 Memory Cache sub menu 25 32 Multi Sector Transfers 29 N notational conventions iv O offset defined 107 operating system OS installed 31 operating system defined 107 P PCI configuration 32 PCI PNP ISA IRQ Region Exclusion Sub Menu 37 PCI PNP ISA ...

Page 123: ...ly Addressable SIMM defined 110 system BIOS caching 38 memory amount displayed 26 system memory defined 110 T technical support iv time access 103 transfer mode hard disk 30 troubleshooting iv type disk 28 U UED term defined 110 updates BIOS defined 104 flash defined 106 URLs MontaVista v 11 51 RadiSys v 11 51 WindRiver v 11 51 User Editable Drive UED defined 110 V VGA BIOS 38 defined 110 W World ...

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