RadiSys EPS-6315, Hardware Reference Manual, Page: 107 / 123

Appendix G: Carrier card design
97
sheet 8
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
Only need 100uF tantalum cap next to the ferrite beads.
Inserting this resistor causes spread spectrum mode to be entered at power up. Remove the pullup on this resistor if this one is inserted.
Crystal Design Rules 1
.
A
v
o
id
h
ig
h
s
p
e
e
d signals near crystal pads. Do not route within 0.050" on
a
d
ja
c
ent layers or near any vias needed.
2
.
P
la
c
e
crystal as close as possible to PLL pins.
3
. Use wide, short crystal traces.
4
.
P
la
c
e
c
a
p
s
c
lo
s
e
t
o
t
h
e crystal pads, routing through the cap pads to the
crystal to the part if possible.
For EMI reductio
n,
if neces
sa
ry
VDD Design Rules 1
.
L
o
c
a
te
a
0
.1
u
F
c
a
p
n
e
x
t
to
e
a
c
h VDD pin routing wide power traces through the cap pad before the
pin. 2
.
K
e
ep VDD traces as short and as wide as possible.
3
.
P
la
c
e
T
A
N
cap as close to ferrite beads as possible.
CK100M
Clock Routing and Delay Rules All Clocks (where no other guidance is given) 1
. Ro
u
te
a
ll
cl
o
cks o
n
i
n
n
e
r
layers adjacent to solid ground or power planes at 10 mil widths.
2. Place the EMI caps at the load. 3
.
C
lo
c
k
s
p
a
c
in
g
1
4
m
il
s
c
lock to trace, 18 mils between same clock loops.
4. Shared clocks must be the same length CPU Clocks 1
.
M
a
x
.
c
apacitance for clocks: CPUCLK - 20pF.
PCI Clocks 1
.
T
h
e
P
C
B
P
C
IC
L
K
t
o
P
C
IC
L
K
s
k
e
w
i
s
1
.5
n
s
m
a
x
. Match lengths to within 4.5" of the length of the PCI
c
lo
ck to the BX. Clock chip is 500ps max. skew.
2
.
M
a
x
.
capacitance for clocks: PCICLK - 30pF.
SCSI
For loading,
if
re
quired
66MHz Selection 1-2: 33 MHz 2-3: 66 MHz
PMC Site 1 PMC Site 2 PMC Site 3
P2P Bridge SCSI
25
EPM7256A
E
C
T
10
0
50
1*
7
5
100
Arbiter (same page, below left) PMC Site 2 PMC Site 3 PCI-PCI Bridge PMC Site 1
SCSI P2P Bridge
PMC Site 3 PMC Site 2 PMC Site 1
F
ro
m
s
a
m
e
p
a
g
e
, a
bov
e
ri
ght.
JTAG Programming header
+2.5V
Wide fat trace, suggest 100mils.
E
rr
ata: 2.74K
pul
lu
p
re
sist
o
rs t
o
VI
O
o
n
ar
bi
tr
ati
on s
ignal
s
to al
l
Jn
1
sig
n
a
ls
.
PCI Central Resource
Hillsbor, Oregon
HobbitTest
C
:\
M
Y
D
O
C
S
\P
R
O
J
E
C
T
S
\P
R
P
M
C
\H
OBBI
T
T
EST
\H
OBBI
T
T
EST
.D
SN
C Monday, June 24, 200
2
T
H
-1025-00
89
www.radisys.com
0
<Variant Name>
/ Page Title: Schematic Title:
R
a
d
iS
ys
C
onfidential
Doc Number: Size: Date:
Sheet
of
Sheet Rev:
Hierarchy Path:
$CLK:RPCI0 $CLK:RUSB $CLK:R48M $CLK:RHCLK1 $CLK:RPIXOSC
PLL
XT
AL2
$CLK:RHCLK0
$~RCPU_STP
PLL
XT
AL1
$~RPCI_STP
$CK100
$CK100VDD
$~PWRDOWN
$CLK:R14M $CLK:RPCI1 $CLK:RPCI2 $CLK:RPCI3 $CLK:RPCI4 $CLK:RPCI5
$FPGA:PU1 $FPGA:PU2 $FPGA:TP1 $FPGA:TP3 $FPGA:TP4 $FPGA:TP2 $FPGA:TP5 $FPGA:TP6 $FPGA:TP7 $FPGA:TP8 $FPGA:TP10 $FPGA:TP11 $FPGA:TP12 $FPGA:TP13 $FPGA:TP14 $FPGA:TP15 $FPGA:TP16 $FPGA:TP17 $FPGA:TP19 $FPGA:TP20 $FPGA:TP21 $FPGA:TP22 $FPGA:TP23 $FPGA:TP24 $FPGA:TP25 $FPGA:TP26 $FPGA:TP27 $FPGA:TP28 $FPGA:TP29 $FPGA:TP30 $FPGA:TP31 $FPGA:TP32 $FPGA:TP33 $FPGA:TP34 $FPGA:TP35 $FPGA:TP36 $FPGA:TP37 $FPGA:TP38
$FPGA:TP39 $FPGA:TP40 $FPGA:TP41 $FPGA:TP42 $FPGA:TP43 $FPGA:TP44 $FPGA:TP45 $FPGA:TP46 $FPGA:TP47 $FPGA:TP48 $FPGA:TP49 $FPGA:TP50 $FPGA:TP51 $FPGA:TP52 $FPGA:TP53 $FPGA:TP54 $FPGA:TP55 $FPGA:TP56 $FPGA:TP57 $FPGA:TP58 $FPGA:TP59 $FPGA:TP60 $FPGA:TP61
$FPGA:TP9 $FPGA:TP18
JT:TCK JT:TDI JT:TDO JT:TMS
2.5:VADJ
+2.5V
$CLK:PCI1
3
$CLK:PCI0
2
$CLK:PCI6 $CLK:PCI2
4
$CLK:PCI5 $CLK:PCI3
5
$CLK:PCI4
6
VIO
2,3,4
$PCI:~REQ64
2,3,4
$PCI:~INTA
2,3,4,7
$PCI:~LOCK
2,3,4,6
$PCI:~INTD
2,3,4,5,7
$PCI:~PERR
2,3,4,5,6
$PCI:~SERR
2,3,4,5,6
$PCI:~INTB
2,3,4,7
$PCI:~INTC
2,3,4,7
$PCI:~ACK64
2,3,4
$PCI:M66EN
2,3,4
$PCI:~IRDY
2,3,4,5,6
$PCI:~FRAME
2,3,4,5,6
$PCI:~STOP
2,3,4,5,6
$PCI:~DEVSEL
2,3,4,5,6
$PCI:~REQ0
2
$PCI:~GNT0
2
$PCI:~GNT1
3
$PCI:~GNT2
4
$PCI:~GNT3
5
$PCI:~GNT4
6
$PCI:~REQ1
3
$PCI:~REQ2
4
$PCI:~REQ3
5
$PCI:~REQ4
6
$CLK:PCI5 $PCI:~RST
2,3,4,5,6,9
$PCI:~TRDY
2,3,4,5,6
+3.3
+3.3
+3.3
+3.3
+3.3
+3.3
+3.3
VCC
+3.3
VCC
+3.3
+3.3
E58
R79
R29 221 0603
E33
C93
JP1 HDR M 2X5 0.100"
1 3 5
6 4 2
7 9
8
10
1 3 5
6 4 2
7 9
8 10
C47 120
6
1UF
E69
R34 0603 4.75K
X1
14.31818MHZ FPX 79-0082-0
0
1 2
3 4
R25
0
E51 E67
E25
R35 060
3
4.75K DNI
C51 22PF 0603
R148
R26
R129
2.74K 060
3
R7 2.74K 0603
E76
E35
R21 0603 4.75K
E57
C78 4.7UF 1206
E78
E87 E49
E20 E24
C75 120
6
1UF
R22
E70
R154 4.75K 060
3
L1
E21
E40 R18 10K 0603
R27 10K 060
3
E64
C50
R20
E56
R28 10K 0603
R3 2.74K 060
3
E65
C83 0.1UF 060
3
E54
C90
C121 060
3
0.1UF
R72
C74 0.1UF 060
3
E37
C80 4.7UF 1206
C89 060
3
10PF
C122 0603 0.1UF
E71
R73
R231 2.74K 0603
E77
C82 0.1UF 060
3
C49
E82
R75
C81 0.1UF 0603
R91 060
3
10K
E55
R74
R16 2.74K 0603
R37 221 0603
R76
E45 E53
C72 0.1UF 0603
C143 0603 0.1UF
E63
C91
E74
C71 0.1UF 060
3
R78
R263 2.74K 060
3
E46
E72 E50
C96
R23
C77 0.1UF 060
3
E62
C97
C87 10PF 060
3
TQFP 100 EPM7128B
LAB
B
LAB C LAB D LAB
E
LAB E LAB F LAB G LAB H LAB A
LAB
A
4ns
U10 75-2173-
00
EPM71
28B
TQFP100
1 2
3
4
5 6 7 8 9
10
11
12 13 14
15
16 17 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 40 41 42 44 45 46 47 48
49 50 52 53 54 55 56 57 58 60 61 63 64 65 67 68 69 70 71 72 75 76 77 78 79 80 81 83 84 85 92 93 94 96 97 98 99 100
87 90 89 88
62 73
26
38
43
59
74
86
95
18
34
51
66
82
39
91
IO1 IO2
VCCIO 1
TDI
IO3 IO4 IO5 IO6 IO7 IO8
GND1
IO9 IO10 IO11
TMS
IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO34 IO35 IO36 IO37 IO38
IO39 IO40 IO41 IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 IO58 IO59 IO60 IO61 IO62 IO63 IO64 IO65 IO66 IO67 IO68 IO69 IO70 IO71 IO72 IO73 IO74 IO75 IO76
IN/GCLK1 IN/OE2/GCLK2 IN/GCLRn IN/OE1
TCK TDO
GND2
GND3
GND4
GND5
GND6
GND7
GND8
VCCIO 2
VCCIO 3
VCCIO 4
VCCIO 5
VCCIO 6
VCCINT1
VCCINT2
C95
R6 2.74K 060
3
R15 2.74K 060
3
E85 E80
C48
E52 E47
R24
060
3
22.1
C86 10PF 060
3
R17 2.74K 0603
E83 E42
C65 0.1UF 0603
U6
SSOP28 CK100-SS CK100 75-1754-0
1
2 3
16 18 17
19
8
13
28
12
1
7
15
21
23 24 4 5 6 9 10 11 26 14
25
27
20
22
XTAL_IN XTAL_OUT SEL100/66# CPU_STOP# PWRDWN#
VDDCO RE
VDDP CI
48MHz
VDDRE F
VDD4 8
VSSREF
VSSPCI
VSS48
VSSCOR E
CPUCLK1 CPUCLK0 PCICLK_F
PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5
REF0CLK/#SPREAD
48MHz/24MHz
VDDCP U
REF1CLK/#SEL48
PCI_STOP#
VSSCPU
C128 0603 0.1UF
C79 0.1UF 0603
R50 2.74K 060
3
E48
C139 060
3
0.1UF
C151 0603 0.1UF
E34
E61
E36
C94
E32
E66
R77
E43
L2
120 OHM@100MHZ 0603
R5 2.74K 0603
E75
C6 37-0109-
00
100UF TAN/D
1 2
R33 2.74K 060
3
R258 2.74K 060
3
E73
E79 E23
E59
R143
10K 060
3
C129 060
3
0.1UF
E60 E81
C73 1000PF 0603
E44
R260 2.74K 060
3
C150 0603 0.1UF
J17 HDR 1X3 M 0.100" 40-0025-0
0
1 2 3
1 2 3
U1 LM31
7
SOT22
3
75-1998-0
0
3
1
2 4
VIN
VADJ
VOUT_2 VOUT_4
E68 E84
E22
E41
E38
E86
R264 2.74K 0603
R125
R80
C92 10PF 060
3