Programming Adapter Kit User’s Guide
QF4A512-PA
Rev A4, Feb 09
7
www.quickfiltertech.com
Designer’s note
– The allowable input range is 5 MHz to 200 MHz.
The clock input on Pin 22 to the phase lock loop is a 1.8 Volt level. Therefore the amplitude
of the incoming clock source should be 1.62 to 1.98 Volts Peak to peak. Since the input is
AC coupled, a DC offset can exist. The clock can be a sine wave, or square wave.
9) List of Test Point Definitions:
TP1 = +5V from DC wall adapter.
TP2 = +3.3V from on board regulator.
TP3 = +1.8V from on board regulator.
TP22 = External clock input.
GND = Ground point for external clock and voltage measurement.
10) Schematics:
The following are the full schematics for the QF4A512 Programming Adapter Board.
C9
18 pF
0805
R17 0
TP5
R10 0
CH 1
C16
0.1uF
0805
DOUT
TP8
C17
0.1uF
0805
3V3
C18
0.1 uF
0603
CH 2
C6
0.1uF
0805
R7 100
CH 3
C11
0.1uF
0805
3V3
C5
0.1uF
0805
R11 100
R5
1Meg
C21
0.1uF
0805
CS1
J1
CONN PLUG 3x2
2
4
6
1
3
5
R3 0
R8 0
R21 0
CH 4
RESET
CS2
R1 0
1V8
TP9
TP1
C8
0.1uF
0603
C15
0.1uF
0603
Optional
for orginal
CS1
C23
0.1uF
0603
1V8
DRDY
TP12
R6 0
R13 100
R18 100
J3
CONN PLUG 3x2
2
4
6
1
3
5
NO STUFF
ON CAPS
R12 0
TP13
TP22
1
J2
CONN PLUG 3x2
2
4
6
1
3
5
1V8
R4 100
C19
0.1uF
0603
C13
0.1uF
0603
DIN
NO STUFF
ON CAPS
R15 100
R2 100
SCLK
TP16
J4
CONN PLUG 3x2
2
4
6
1
3
5
R14 0
C22
0.1 uF
0603
1V8
U1
QF4A512
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
24
25
26
27
28
29
30
31
32
A1N
A1P
A2N
A2P
A3N
A3P
A4N
A4P
DV
DD1
8
DG
ND
DG
ND
CS
N
DRDY
/S
E
L
SD
O
SD
I
SC
L
K
RSTN
DGND
DVDD18
DVDD33
XVDD18
XOUT
XIN
XGND
PG
N
D
PV
D
D
1
8
AG
N
D
AV
D
D
1
8
AV
D
D
1
8
AG
N
D
AG
N
D
AV
D
D
3
3
C12
0.1uF
0805
NO STUFF
ON CAPS
C7
18 pF
0805
R9 100
R19 0
1V8
X1
20.000 MHz
1
2
TP4
NO STUFF
ON CAPS
C20
0.1uF
0805
