Quectel QuecOpen AG525R-GL, Hardware Design

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Automotive Module Series
AG525R-GL QuecOpen Hardware Design
AG525R-GL_QuecOpen_Hardware_Design 64 / 104
 Spacing to all other signals is larger than three times of line width.
 Resistors R7–R12 should be placed near the module. Resistor R1–R6 should be placed near the
Ethernet PHY. The value of R1–R16 varies with the selection of PHY.
3.16. WLAN and BT Interfaces*
The module provides a PCIe interface for WLAN function and UART & PCM interfaces for BT function.
Table 23: Pin Definition of WLAN and BT Interfaces
Pin Name Pin No. I/O Description Comment
PCIe Interface
PCIE_REFCLK_P 40 AO PCIe reference clock (+)
Require differential
impedance of 95
Ω .
PCIE_REFCLK_M 38 AO PCIe reference clock (-)
PCIE_TX_M 44 AO PCIe transmit (-)
PCIE_TX_P 46 AO PCIe transmit (+)
PCIE_RX_M 32 AI PCIe receive (-)
PCIE_RX_P 34 AI PCIe receive (+)
PCIE_CLKREQ 36
DI
O
PCIe clock request
1.8 V power domain.
PCIE_RST 39 DO PCIe reset
PCIE_WAKE 30 DI PCIe wakeup
Coexistence Interface
COEX_UART_
RXD
67 DI
LTE&WLAN/BT
coexistence receive
1.8 V power domain.
COEX_UART_
TXD
69 DO
LTE&WLAN/BT
coexistence transmit
BT Interface
BT_UART_TXD 59 DO BT UART transmit
BT_UART_RXD 63 DI BT UART receive