Quectel QuecOpen AG525R-GL Hardware Design Download Page 5

Page: 5 / 107

Automotive Module Series

AG525R-GL QuecOpen

Hardware Design

AG525R-GL_QuecOpen_Hardware_Design 4 / 104

Contents

About the Document ................................................................................................................................ 3

Contents .................................................................................................................................................... 4

Table Index ............................................................................................................................................... 6

Figure Index .............................................................................................................................................. 8

Introduction ..................................................................................................................................... 10

1.1.

Safety Information .................................................................................................................. 13

Product Concept ............................................................................................................................. 14

2.1.

General Description ................................................................................................................ 14

2.2.

Key Features .......................................................................................................................... 17

2.3.

Functional Diagram ................................................................................................................ 19

2.4.

Evaluation Board .................................................................................................................... 20

Application Interfaces ..................................................................................................................... 21

3.1.

General Description ................................................................................................................ 21

3.2.

Pin Assignment ....................................................................................................................... 22

3.3.

Pin Description ....................................................................................................................... 23

3.4.

Operating Modes .................................................................................................................... 39

3.5.

Power Saving ......................................................................................................................... 39

3.5.1.

Sleep Mode.................................................................................................................. 39

3.5.1.1.

USB Application with USB Remote Wakeup Function ...................................... 40

3.5.1.2.

USB Application without USB Remote Wakeup Function ................................. 41

3.5.1.3.

USB Application without USB Suspend Function .............................................. 41

3.5.2.

Airplane Mode .............................................................................................................. 42

3.6.

Power Supply ......................................................................................................................... 42

3.6.1.

Power Supply Pins ....................................................................................................... 42

3.6.2.

Decrease Voltage Drop ................................................................................................ 43

3.6.3.

Reference Design for Power Supply ............................................................................ 44

3.6.4.

Monitor the Power Supply ............................................................................................ 45

3.7.

Power on and off Scenarios ................................................................................................... 45

3.7.1.

Turn on Module with PWRKEY .................................................................................... 45

3.7.2.

Turn on Module with PON_1 ........................................................................................ 47

3.7.3.

Turn off Module ............................................................................................................ 47

3.7.3.1.

Turn off Module Using PWRKEY ...................................................................... 47

3.7.3.2.

Turn off Module Using API Interface ................................................................. 48

3.8.

Reset the Module ................................................................................................................... 48

3.9.

(U)SIM Interfaces ................................................................................................................... 50

3.10.

USB Interfaces ....................................................................................................................... 52

3.11.

UART Interfaces ..................................................................................................................... 54

3.12.

I2S and I2C Interfaces ............................................................................................................ 57

Summary of Contents for QuecOpen AG525R-GL

Page 1: ...AG525R GL QuecOpen Hardware Design Automotive Module Series Version 1 0 0 Date 2020 10 13 Status Preliminary www quectel com ...

Page 2: ... without prior notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain errors inaccuracies and omissions Unless otherwise provided by valid agreement Quectel makes no warranties of any kind implied or express with respect to the use of features and functions unde...

Page 3: ... Quectel Wireless Solutions Co Ltd Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights are reserved in the event of a patent grant or registration of a utility model or design Copyright Quectel Wireless Solutions Co Ltd 2020 All rights reserved ...

Page 4: ...Design AG525R GL_QuecOpen_Hardware_Design 3 104 About the Document Revision History Version Date Author Description 2020 04 04 Leon HUANG Alex ZHANG Evan SHEN Creation of the document 1 0 2020 10 13 Leon HUANG Alex ZHANG Evan SHEN Thomas ZHANG Preliminary ...

Page 5: ...3 5 1 1 USB Application with USB Remote Wakeup Function 40 3 5 1 2 USB Application without USB Remote Wakeup Function 41 3 5 1 3 USB Application without USB Suspend Function 41 3 5 2 Airplane Mode 42 3 6 Power Supply 42 3 6 1 Power Supply Pins 42 3 6 2 Decrease Voltage Drop 43 3 6 3 Reference Design for Power Supply 44 3 6 4 Monitor the Power Supply 45 3 7 Power on and off Scenarios 45 3 7 1 Turn ...

Page 6: ...s 75 4 2 2 Recommended RF Connector for Antenna Installation 76 5 Reliability Radio and Electrical Characteristics 77 5 1 Absolute Maximum Ratings 77 5 2 Power Supply Ratings 78 5 3 Operation and Storage Temperatures 78 5 4 Current Consumption 79 5 5 RF Output Power 84 5 6 RF Receiving Sensitivity 86 5 7 Electrostatic Discharge 88 5 8 Thermal Consideration 89 6 Mechanical Dimensions 91 6 1 Mechani...

Page 7: ...rface 57 Table 19 Pin Definition of SDIO Interface 58 Table 20 Pin Definition of SPI Interfaces 60 Table 21 Parameters of SPI Interface Timing 61 Table 22 Pin Definition of RGMII Interface 61 Table 23 Pin Definition of WLAN and BT Interfaces 64 Table 24 Pin Definition of ADC Interfaces 67 Table 25 Characteristic of ADC Interface 67 Table 26 Pin Definition of USB_BOOT Interface 68 Table 27 Pin Defi...

Page 8: ...Automotive Module Series AG525R GL QuecOpen Hardware Design AG525R GL_QuecOpen_Hardware_Design 7 104 Table 42 GPRS Multi slot Classes 104 Table 43 EDGE Modulation and Coding Schemes 106 ...

Page 9: ...nnector 51 Figure 20 Reference Circuit of USB 2 0 Application 53 Figure 21 Reference Circuit of USB 3 0 Application 53 Figure 22 Reference Circuit with Translator Chip 56 Figure 23 Reference Circuit with Transistor Circuit 56 Figure 24 Reference Circuit of I2S and I2C Application with Audio Codec 57 Figure 25 Reference Design of SDIO Interface for eMMC Application 59 Figure 26 SPI Timing 60 Figure...

Page 10: ...are Design AG525R GL_QuecOpen_Hardware_Design 9 104 Figure 42 Top View of the Module 94 Figure 43 Bottom View of the Module 94 Figure 44 Recommended Reflow Soldering Thermal Profile 96 Figure 45 Tape Specifications 98 Figure 46 Reel Specifications 98 ...

Page 11: ...ce specifications electrical and mechanical details as well as other related information of the module With the application notes and user guides provided separately you can easily use the module to design and set up mobile applications FCC Certification Requirements According to the definition of mobile and fixed device is described in Part 2 1091 b this device is a mobile device And the followin...

Page 12: ... label if 1 the module s FCC ID is not visible when installed in the host or 2 if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible then an additional permanent label referring to the enclosed module Contains Transmitter Module FCC ID XMR2020AG525RGL or Contains FCC ID XMR2020AG525RGL...

Page 13: ...ure to RF radiation maximum antenna gain including cable loss must not exceed GSM850 8 446dBi GSM1900 10 030dBi WCDMA II LTE Band 2 7 25 38 41 8 000dBi WCDMA IV LTE Band 4 66 5 000dBi WCDMA V LTE Band 5 9 416dBi LTE Band 12 8 734dBi LTE Band 13 9 173dBi LTE Band 26 9 337dBi LTE Band 71 8 447dBi The host product shall be properly labelled to identify the modules within the host product The Innovati...

Page 14: ...Wireless devices may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions such as when the mobile bill is unpaid or the U SIM card is invalid W...

Page 15: ...meet the demanding requirements in automotive applications and other harsh operating conditions the module offers a premium solution for high performance automotive and intelligent transportation system ITS applications such as fleet management onboard vehicle telematics in car entertainment systems emergency calling and roadside assistance With a compact profile of 38 0 mm 42 0 mm 2 65 mm the mod...

Page 16: ...B5 B66 B7 B66 B66 B71 B7 B12 B20 B28 B32 B66 B7 B8 B8 B11 B32 B38 B39 B40 B41 B8 3CA DL B12 B66 B66 B12 B12 B66 B13 B66 B66 B1 B1 B28 B3 B5 B7 B41 B8 B1 B3 B18 B19 B20 B28 B38 B3 B40 B41 B5 B7 B8 B1 B40 B40 B1 B41 B41 B1 B5 B40 B7 B1 B7 B20 B28 B7 B8 B1 B8 B38 B40 B20 B38 B38 B20 B40 B40 B25 B25 B25 B2 B28 B40 B40 B28 B41 B41 B29 B30 B66 B29 B66 B66 B2 B12 B12 B30 B66 B2 B13 B66 B2 B29 B30 B66 B2 ...

Page 17: ... B41 B41 B3 B5 B40 B7 B3 B7 B20 B28 B7 B8 B3 B8 B38 B40 B40 B40 B40 B41 B41 B41 B4 B12 B12 B30 B4 B29 B30 B4 B4 B12 B13 B29 B30 B5 B71 B7 B4 B5 B30 B5 B4 B7 B12 B7 B5 B30 B66 B5 B40 B40 B5 B5 B66 B30 B5 B66 B66 B5 B7 B7 B66 B66 B66 B71 B7 B12 B66 B12 B7 B20 B32 B7 B66 B66 B7 B7 B8 B28 B20 B66 B8 B39 B39 B8 B40 B40 B8 B41 B41 B8 B8 B39 B41 WCDMA with Rx diversity B1 B2 B3 B4 B5 B8 B19 GSM 850 900 1...

Page 18: ...D and TDD Support 1 4 3 5 10 15 20 MHz RF bandwidth Support 2 2 MIMO in DL direction LTE FDD Max 600 Mbps DL 75 Mbps UL LTE TDD Max 467 Mbps DL 45 Mbps UL UMTS Features Support 3GPP R8 DC HSDPA HSPA HSDPA HSUPA WCDMA Support QPSK 16 QAM and 64 QAM modulation DC HSDPA Max 42 Mbps DL HSUPA Max 5 76 Mbps UL WCDMA Max 384 kbps DL 384 kbps UL GSM Features GPRS Support GPRS multi slot class 33 33 by def...

Page 19: ... maximum transmission rates up to 5 Gbps on USB 3 0 and 480 Mbps on USB 2 0 Used for AT command communication data transmission firmware upgrade software debugging and voice over USB Support USB serial drivers for Windows 7 8 8 1 10 Linux 2 6 5 4 and Android 4 x 5 x 6 x 7 x 8 x 9 x UART Interfaces UART1 Baud rate reach up to 921600 bps 115200 bps by default Support RTS and CTS hardware flow contro...

Page 20: ...he ability to establish and maintain functions such as voice SMS data transmission and emergency call without any unrecoverable malfunction Radio spectrum and radio network will not be influenced while one or more specifications such as Pout may undergo a reduction in value exceeding the specified tolerances of 3GPP When the temperature returns to the normal operating temperature level the module ...

Page 21: ...MII U SIM x2 GPIOs I2S MMPA QDM M HB Diplexer Duplexers SAWs and Qualplexers 2G PA DP16T Diplexer QLNA 2 ANT_DIV ANT_MAIN VBAT_RF APT QDM LB Figure 1 Functional Diagram for AG525R GL QuecOpen 2 4 Evaluation Board To help you develop applications conveniently with the module Quectel supplies the evaluation board EVB USB data cables a pair of earphones antennas and other peripherals to control or te...

Page 22: ... 400 LGA pins that can be connected to cellular application platforms Module interfaces are described in detail in the following sub chapters Power supply U SIM interfaces USB 2 0 3 0 interface UART interfaces I2S and I2C interfaces SDIO interface SPI interfaces RGMII interface WLAN and BT interfaces ADC interfaces USB_BOOT interface GPIO interfaces means under development NOTE ...

Page 23: ...2 RGMII_TX_1 23 RGMII_TX_2 24 RGMII_CK_TX 25 RGMII_TX_3 GND 26 GND 27 RGMII_PW R_EN 28 RGMII_PW R_IN 29 RGMII_INT 30 PCI E _WA KE 31 RGMII_RST RGMII_RST 32 PCI E _RX_M 33 GND 34 PCI E _RX_P 35 RES ERVED 36 PCI E _CL KREQ 37 RES ERVED 38 PCI E _REF CL K_M 39 PCI E _RST 40 PCI E _REF CL K_M 41 RES ERVED 42 GND 43 RES ERVED 44 PCI E _TX _M 45 EMMC_PW R_EN 46 PCI E _TX _P 47 SDC 1_CL K 47 SDC 1_CL K 4...

Page 24: ...n The following tables show the pin definition of the module and the alternate functions of multiplexing pins Table 3 I O Parameters Definition Type Description AI Analog input AO Analog output B Bidirectional digital with CMOS input DI Digital input DO Digital output H High level IO Bidirectional L Low level OD Open drain PD Pull down PI Power input PO Power output PU Pull up R Slew rate limited ...

Page 25: ...Wi Fi Vnorm 1 95 V If unused keep it open GND 12 18 26 33 42 86 92 98 115 117 118 120 121 124 131 133 135 137 138 140 141 144 151 153 155 156 158 159 160 162 164 165 167 168 171 174 176 177 180 182 183 185 186 189 191 192 194 195 198 199 201 203 206 208 209 211 212 215 217 218 220 221 230 232 233 234 237 240 307 400 Turn on off Pin Name Pin No I O Description DC Characteristics Comment PWRKEY 7 DI...

Page 26: ...0 V U SIM VOLmax 0 4 V VOHmin 2 28 V If unused keep it open USIM1_RST 250 DO U SIM1 card reset For 1 8 V U SIM VOLmax 0 4 V VOHmin 1 44 V For 3 0 V U SIM VOLmax 0 4 V VOHmin 2 28 V If unused keep it open USIM1_DET 255 DI U SIM1 card hot plug detect VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep it open USIM2_VDD 256 PO U SIM2 card power supply For 1 8 V U S...

Page 27: ... VOHmin 2 28 V If unused keep it open USIM2_DET 258 DI U SIM2 card hot plug detect VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep it open USB Interfaces Pin Name Pin No I O Description DC Characteristics Comment USB_VBUS 84 DI USB connection detect Vmax 5 25 V Vmin 3 0 V Vnorm 5 0 V USB_DP 85 AI AO USB differential data bus Compliant with USB 2 0 standard s...

Page 28: ...ut output GPIO3 102 IO General purpose input output GPIO4 104 IO General purpose input output GPIO5 116 IO General purpose input output GPIO6 243 IO General purpose input output GPIO7 246 IO General purpose input output GPIO8 249 DO General purpose output VILmin TBD VILmax 0 63 V VIHmin 0 9 V VIHmax TBD VOLmax 0 36 V VOHmin 1 44 V GPIO9 264 IO General purpose input output VILmin 0 3 V VILmax 0 63 ...

Page 29: ...in 1 35 V 1 8 V power domain Can be configured to GPIO If unused keep them open BT_UART_RXD 63 DI BT UART receive VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V BT_UART_RTS 61 DI BT UART request to send VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V BT_UART_CTS 62 DO BT UART clear to send VOLmax 0 45 V VOHmin 1 35 V Debug UART Interface Pin Name Pin No I O Description DC Characterist...

Page 30: ...max 0 45 V VOHmin 1 35 V I2S_WS 73 IO I2S word select VOLmax 0 45 V VOHmin 1 35 V VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V I2S_SCK 75 DO I2S clock VOLmax 0 45 V VOHmin 1 35 V I2S_DIN 76 DI I2S data in VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V I2S_DOUT 78 DO I2S data out VOLmax 0 45 V VOHmin 1 35 V PCM Interface Pin Name Pin No I O Description DC Characteristics Comment PCM...

Page 31: ...4 AO PCIe transmit PCIE_TX_P 46 AO PCIe transmit PCIE_RX_M 32 AI PCIe receive PCIE_RX_P 34 AI PCIe receive PCIE_CLKREQ 36 IO PCIe clock request VOLmax 0 45 V VOHmin 1 35 V VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep them open PCIE_RST 39 DO PCIe reset VOLmax 0 45 V VOHmin 1 35 V PCIE_WAKE 30 DI PCIe wakeup VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax ...

Page 32: ...GMII transmit clock RGMII_TX_3 25 DO RGMII transmit data bit 3 RGMII_PWR_ EN 27 DO Enable external LDO to supply power to RGMII_PWR_IN VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep it open RGMII_PWR_IN 28 PI Power input for internal RGMII circuit 1 8 2 5 V power supply input If RGMII is not be used connect it to VDD_EXT RGMII_INT 29 DI RGMII PHY interrupt output VILmin 0 3 V VILmax...

Page 33: ...a bit 6 SDC1_DATA_7 58 IO SDIO data bit 7 SDC1_CLK 47 DO SDIO clock VOLmax 0 45 V VOHmin 1 4 V 1 8 V power domain for eMMC applications If unused keep it open EMMC_RST 54 DO eMMC reset VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep it open EMMC_PWR_ EN 45 DO eMMC power supply enable control VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep it open SPI Interfaces Pin Name...

Page 34: ...I General purpose ADC interface Voltage Range 0 1 875 V If unused keep it open Other Interface Pins Pin Name Pin No I O Description DC Characteristics Comment USB_BOOT 83 DI Force the module into emergency download mode 1 8 V power domain If unused keep it open BT_EN 66 DO BT function enable control VOLmax 0 45 V VOHmin 1 35 V DR_SYNC 95 DO Navigation 1PPS time sync output VOLmax 0 45 V VOHmin 1 3...

Page 35: ..._UART_ RXD 67 DI LTE WLAN BT coexistence receive VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V COEX_UART_ TXD 69 DO LTE WLAN BT coexistence transmit VOLmax 0 45 V VOHmin 1 35 V WLAN_SLP_ CLK 231 DO WLAN sleep clock VOLmax 0 45 V VOHmin 1 35 V RF Antenna Interfaces Pin Name Pin No I O Description DC Characteristics Comment ANT_MAIN 143 AI AO Main antenna interface 50 Ω impedance ANT_DIV 170...

Page 36: ...E PCIe BS PD L Y 1 8 V 36 PCIE_CLKREQ BS PD L Y 1 8 V 39 PCIE_RST BS PD L Y 1 8 V 45 EMMC_PWR_EN SDIO BS PD L Y 1 8 V 53 SDC1_DATA_4 GPIO_92 BSH PD L N 1 8 V 54 EMMC_RST BS PD L Y 1 8 V 55 SDC1_DATA_5 GPIO_93 BSH PD L Y 1 8 V 56 SDC1_DATA_6 GPIO_94 BSH PD L Y 1 8 V 58 SDC1_DATA_7 GPIO_95 BSH PD L Y 1 8 V 59 BT_UART_TXD UART GPIO_63 BS PD L N 1 8 V 61 BT_UART_RTS GPIO_65 BS PD L Y 1 8 V 62 BT_UART_...

Page 37: ..._IN I2S_DIN GPIO_13 BS PD L Y 1 8 V 261 PCM_OUT I2S_DOUT GPIO_14 BS PD L Y 1 8 V 77 CDC_RST I2S GPIO_86 BS PD L Y 1 8 V 81 I2S_MCLK GPIO_62 BS PD L N 1 8 V 78 I2S_DOUT PCM_OUT GPIO_18 BS PD L Y 1 8 V 75 I2S_SCK PCM_CLK GPIO_19 BS PD L Y 1 8 V 76 I2S_DIN PCM_IN GPIO_17 BS PD L Y 1 8 V 73 I2S_WS PCM_SYNC GPIO_16 BS PD L Y 1 8 V 79 I2C1_SCL I2C BSR PD L Y 1 8 V 80 I2C1_SDA BSR PD L Y 1 8 V 250 USIM1_...

Page 38: ... SPI1_MISO GPIO_73 BS PD L N 1 8 V 108 SPI2_MOSI GPIO_4 BS PD L N 1 8 V 105 SPI2_CS GPIO_6 BS PD L Y 1 8 V 103 SPI2_CLK GPIO_7 BS PD L N 1 8 V 106 SPI2_MISO GPIO_5 BS PD L Y 1 8 V 66 BT_EN Others BS PD L Y 1 8 V 83 USB_BOOT BS PD L N 1 8 V 95 DR_SYNC BS PD L Y 1 8 V 169 IMU_INT1 GPIO_88 BS PD L Y 1 8 V 181 IMU_PWR_EN GPIO_91 BS PD L N 1 8 V 187 IMU_INT2 GPIO_82 BS PD L Y 1 8 V 222 WLAN_PWR_EN1 BS ...

Page 39: ...upt function are configured as interrupt GPIOs power consumption of the module will be increased Y means interrupt function supported N means interrupt function not supported 4 Pins 69 and 83 cannot be pulled up before power up 102 GPIO3 GPIO BS PD L N 1 8 V 104 GPIO4 BS PD L N 1 8 V 116 GPIO5 BS PD L N 1 8 V 243 GPIO6 BS PD L N 1 8 V 246 GPIO7 BS PD L Y 1 8 V 249 GPIO8 L N 1 8 V 264 GPIO9 BS PD L...

Page 40: ...F function and U SIM card will be invalid Airplane Mode AT CFUN 4 can set the module into airplane mode In this case RF function will be invalid Sleep Mode In this mode the current consumption of the module will be reduced to the minimal level During this mode the module can still receive paging message SMS voice call and TCP UDP data from the network normally Power Down Mode In this mode the powe...

Page 41: ...st supports USB suspend resume and remote wakeup function the following three preconditions must be met to let the module enter sleep mode Use sleep API to enable the sleep mode Ensure the level of pins that configured as wake up interrupt in Table 5 are under non wakeup status The host s USB bus which is connected with the module s USB interface enters suspended state The following figure shows t...

Page 42: ...configured as wake up interrupt in Table 5 are under non wakeup status The host s USB bus which is connected with the module s USB interface enters suspended state The following figure shows the connection between the module and the host Figure 5 Sleep Mode Application without USB Remote Wakeup Sending data to the module through USB will wake up the module When the module has URC to report the mod...

Page 43: ...the module enters airplane mode the RF function does not work and all AT commands correlative with RF function will be inaccessible The mode can be set via AT CFUN fun command The parameter fun indicates the module s functionality levels as shown below AT CFUN 0 Minimum functionality mode Both U SIM and RF functions are disabled AT CFUN 1 Full functionality mode by default AT CFUN 4 Airplane mode ...

Page 44: ...st transmission in 2G network The voltage drop will be less in 3G and 4G networks Figure 7 Power Supply Limits during Burst Transmission To decrease voltage drop a bypass capacitor of about 100 µF with low ESR should be used and a multi layer ceramic chip capacitor MLCC array should also be reserved due to its low ESR It is recommended to use three ceramic capacitors 100 nF 33 pF 10 pF for composi...

Page 45: ...ltage difference between the input source and the desired output VBAT a buck converter is preferred to be used as the power supply The following figure shows a reference design for 12 24 V input power source The designed output for the power supply is about 3 8 V and the maximum rated current is 5 A 2 4 1 3 6 7 8 182K NM 100K 10 pF 100 pF 100 nF 10 µF 470 µF 100 nF 100 nF DC_IN 100 µH 5V_EN 100 nF...

Page 46: ...wer domain Pulled up internally Active low When the module is in power off mode it can be turned on by driving PWRKEY low for at least 500 ms It is recommended to use an open drain collector driver to control the PWRKEY A simple reference circuit is illustrated in the following figure Turn on pulse PWRKEY 4 7K 47K 500 ms Figure 10 Turn on the Module Using Driving Circuit Another way to control the...

Page 47: ...igure 11 Turn on the Module Using Keystroke The power on scenario is illustrated in the following figure Figure 12 Power on Timing 1 Please make sure that VBAT is stable for at least 30 ms before pulling down PWRKEY pin 2 It is recommended to use an external OD OC circuit to control the PWRKEY pin NOTES ...

Page 48: ...cuit is illustrated in the following figure PVIN SS TR Module PON_1 10K 0 78 1 89 V Figure 13 Turn on the Module using PON_1 If PON_1 is not used it is recommended to connect it to the ground 3 7 3 Turn off Module Either of the following methods can be used to turn off the module Normal power down procedure Turn off the module using the PWRKEY pin Normal power down procedure Turn off the module us...

Page 49: ...aging the internal flash please do not switch off the power supply when the module works normally Only after the module is shut down by PWRKEY or API interface the power supply can be cut off 2 When turn off module with API please keep PWRKEY at high level after the execution of power off command Otherwise the module will be turned on again after successfully turn off 3 8 Reset the Module RESET ca...

Page 50: ... the module VIHmax 1 89 V VIHmin 1 17 V VILmax 0 63 V The recommended circuit is similar to the PWRKEY control circuit An open drain collector driver or button can be used to control the RESET Reset pulse RESET 4 7K 47K 370 620 ms Figure 15 Reference Circuit of RESET by Using Driving Circuit Figure 16 Reference Circuit of RESET by Using Button The reset scenario is illustrated in the following fig...

Page 51: ...0 V U SIM cards are supported Table 11 Pin Definition of U SIM Interface Pin Name Pin No I O Description Comment USIM1_VDD 251 PO U SIM1 card power supply Either 1 8 V or 3 0 V is supported by the module automatically USIM1_DATA 254 IO U SIM1 card data USIM1_CLK 253 DO U SIM1 card clock USIM1_RST 250 DO U SIM1 card reset USIM1_DET 255 DI U SIM1 card hot plug detect USIM2_VDD 256 PO U SIM2 card pow...

Page 52: ...IM_DATA USIM_DET 22R 22R 22R VDD_EXT 470K 100 nF U SIM Card Connector GND GND VCC RST CLK IO VPP GND USIM_VDD 10K 33 pF 33 pF33 pF CD1 CD2 Figure 18 Reference Circuit of U SIM Interface with an 8 Pin U SIM Card Connector If U SIM card detection function is not needed keep USIM_DET disconnected A reference circuit for U SIM interface with a 6 pin U SIM card connector is illustrated in the following...

Page 53: ... the module and the U SIM card connector so as to suppress EMI spurious transmission and enhance ESD protection The 33 pF capacitors are used for filtering interference of EGSM900 Please note that the U SIM peripheral circuit should be close to the U SIM card connector The pull up resistor on USIM_DATA line can improve anti jamming capability when long layout trace and sensitive occasions are appl...

Page 54: ... speed transmit USB_SS_RX_P 90 AI USB 3 0 super speed receive USB_SS_RX_M 88 AI USB 3 0 super speed receive It is recommended to reserve USB 2 0 for firmware upgrade in application design and reserve test points for debugging purpose The following are the reference circuits of USB 3 0 and 2 0 interfaces Figure 20 Reference Circuit of USB 2 0 Application C1 100 nF C2 100 nF C3 100 nF C4 100 nF USB_...

Page 55: ...ial data pair matching should be less than 0 7 mm 5 ps Do not route signal traces under crystals oscillators magnetic devices PCIe and RF signal traces It is important to route the USB differential traces in inner layer with ground shielding on not only upper and lower layers but also right and left sides If a USB connector is used please keep the ESD protection components as close to the USB conn...

Page 56: ...Definition of BT UART Interface Table 15 Pin Definition of Debug UART Interface Pin Name Pin No I O Description Comment DBG_TXD 107 DO Debug UART transmit 1 8 V power domain DBG_RXD 110 DI Debug UART receive 1 8 V power domain Table 16 Logic Levels of Digital I O Parameter Min Max Unit VIL 0 3 0 63 V VIH 1 17 2 1 V VOL 0 0 45 V VOH 1 35 1 8 V Pin Name Pin No I O Description Comment BT_UART_TXD 59 ...

Page 57: ...ther example with transistor translation circuit is shown as below The circuit design of dotted line section can refer to the design of solid line section in terms of both module input and output circuit designs but please pay attention to the direction of connection Figure 23 Reference Circuit with Transistor Circuit 1 Transistor circuit solution is not suitable for applications with high baud ra...

Page 58: ...I2C1_SCL 79 OD I2C serial clock Require external pull up to 1 8 V I2C1_SDA 80 OD I2C serial data The following figure shows a reference design of I2S and I2C interfaces with an external codec IC Figure 24 Reference Circuit of I2S and I2C Application with Audio Codec Pin Name Pin No I O Description Comment CDC_RST 77 DO Codec reset 1 8 V power domain Can be configured to GPIOs I2S_MCLK 81 DO Clock ...

Page 59: ...r supply Connect it to VDD_EXT SDC1_DATA_0 49 IO SDIO data bit 0 1 8 V power domain for eMMC SDC1_DATA_1 50 IO SDIO data bit 1 SDC1_DATA_2 51 IO SDIO data bit 2 SDC1_DATA_3 52 IO SDIO data bit 3 SDC1_CMD 48 IO SDIO command SDC1_DATA_4 53 IO SDIO data bit 4 1 8 V power domain For eMMC configuration by default Can be configured to GPIO SDC1_DATA_5 55 IO SDIO data bit 5 SDC1_DATA_6 56 IO SDIO data bi...

Page 60: ...default and the recommended resistor value is 10 100 kΩ In order to improve signal quality it is recommended to add 0 Ω resistors R1 R9 and R11 in series between the module and eMMC Resistor R10 should be 30 35 Ω The bypass capacitors C1 C11 are reserved and not mounted by default All resistors and bypass capacitors should be placed close to the module It is important to route the SDIO signal trac...

Page 61: ...ing relationship of SPI interfaces The related parameters of SPI timing are shown in the table below Figure 26 SPI Timing Pin Name Pin No I O Description Comment SPI1_CLK 216 DO SPI1 clock 1 8 V power domain Can be configured to GPIO If unused keep them open SPI1_CS 213 DO SPI1 chip select SPI1_MISO 219 DI SPI1 master in salve out SPI1_MOSI 210 DO SPI1 master out slave in SPI2_CLK 103 DO SPI2 cloc...

Page 62: ... 2009 Half full duplex for 10 100 1000 Mbps Support VLAN tagging Can be used to connect to external Ethernet PHY like 88EA1512 or an external switch Table 22 Pin Definition of RGMII Interface Parameter Description Min Typ Max Unit T SPI clock period 20 0 ns t ch SPI clock high level time 9 0 ns t cl SPI clock low level time 9 0 ns t mov SPI master data output valid time 5 0 5 0 ns t mis SPI master...

Page 63: ... clock RGMII_TX_0 20 DO RGMII transmit data bit 0 RGMII_CTL_TX 21 DO RGMII transmit control RGMII_TX_1 22 DO RGMII transmit data bit 1 RGMII_TX_2 23 DO RGMII transmit data bit 2 RGMII_CK_TX 24 DO RGMII transmit clock RGMII_TX_3 25 DO RGMII transmit data bit 3 RGMII_PWR_EN 27 DO Enable external LDO to supply power to RGMII_PWR_IN 1 8 V power domain RGMII_PWR_IN 28 PI Power input for internal RGMII ...

Page 64: ...RGMII matches with that of PHY The voltage of RGMII_INT and RGMII_RST matches with the I O voltage of PHY The typical power consumption of RGMII_PER_IN is 300 mA 1 8 V Keep RGMII data and control signals away from RF and VBAT traces Assure impedance of RGMII signals trace is 50 Ω 20 The length difference among CK_TX CTL_TX and TX_ 0 3 is less than 2 mm The length difference among CK_RX CTL_RX and ...

Page 65: ...inition of WLAN and BT Interfaces Pin Name Pin No I O Description Comment PCIe Interface PCIE_REFCLK_P 40 AO PCIe reference clock Require differential impedance of 95 Ω PCIE_REFCLK_M 38 AO PCIe reference clock PCIE_TX_M 44 AO PCIe transmit PCIE_TX_P 46 AO PCIe transmit PCIE_RX_M 32 AI PCIe receive PCIE_RX_P 34 AI PCIe receive PCIE_CLKREQ 36 DI O PCIe clock request 1 8 V power domain PCIE_RST 39 DO...

Page 66: ...ign for WLAN and BT interfaces application BT_UART_RTS 61 DI BT UART request to send 1 8 V power domain Can be configured to GPIOs BT_UART_CTS 62 DO BT UART clear to send PCM_SYNC 265 IO PCM data frame sync PCM_CLK 262 IO PCM data bit clock PCM_IN 263 DI PCM data input PCM_OUT 261 DO PCM data output Others interfaces WLAN_PWR_EN2 225 DO WLAN power supply enable control 2 1 8 V power domain WLAN_PW...

Page 67: ..._WAKE PCIE_RST PCIE_REFCLKP PCIE_REFCLKM PCIE_RXM PCIE_RXP PCIE_TXP PCIE_TXM COEX_UART_ RXD COEX_UART_ TXD BT_UART_TXD BT_UART_RXD BT_UART_CTS BT_UART_RTS PCM_CLK PCM_SYNC PCM_IN PCM_OUT WLAN_EN BT_EN SLEEP_CLK R1 100K R2 100K VDD_EXT WLAN_PWR_EN1 WLAN_PWR_EN2 VDD_WIFI_VM VDD_WIFI_VH VDD_WIFI_VM VDD_WIFI_VH C1 100 nF C2 100 nF C3 100 nF C4 100 nF Figure 29 Reference Circuit for Connection with WLA...

Page 68: ...als oscillators magnetic devices or RF signal traces It is important to route the PCIe differential traces in inner layer with ground shielding on not only upper and lower layers but also right and left sides 3 17 ADC Interfaces The module provides three analog to digital converter ADC interfaces The voltage value on ADC pins can be read via AT QADC port command through specifying port as 0 1 or 2...

Page 69: ...re powering on the module will force the module into emergency download mode when powered on In emergency download mode the module supports firmware upgrade over USB 2 0 interface Table 26 Pin Definition of USB_BOOT Interface Pin Name Pin No I O Description Comment USB_BOOT 83 DI Force the module into emergency download mode 1 8 V power domain Active high If unused keep it open The following figur...

Page 70: ...es The module provides 11 GPIOs Table 27 Pin Definition of GPIOs Pin Name Pin No I O Description Comment GPIO1 100 IO General purpose input output 1 8 V power domain If unused keep them open GPIO2 101 IO GPIO3 102 IO GPIO4 104 IO GPIO5 116 IO GPIO6 243 IO GPIO7 246 IO GPIO8 249 DO GPIO9 264 IO GPIO10 267 IO GPIO11 289 IO ...

Page 71: ...e 4 1 1 Pin Definition The pin definition of Main Rx diversity antenna interfaces are shown below Table 28 Pin Definition of Main Rx diversity Antenna Interfaces Pin Name Pin No I O Description Comment ANT_MAIN 143 AI AO Main antenna interface 50 Ω impedance ANT_DIV 170 AI Receive diversity antenna interface 50 Ω impedance 4 1 2 Operating Frequency Table 29 Module Operating Frequencies 3GPP Band T...

Page 72: ...D B5 824 849 869 894 MHz LTE FDD B7 2500 2570 2620 2690 MHz LTE FDD B8 880 915 925 960 MHz LTE FDD B9 1749 9 1784 9 1844 9 1879 9 MHz LTE FDD B11 1427 9 1447 9 1475 9 1495 9 MHz LTE FDD B12 698 716 728 746 MHz LTE FDD B13 777 787 746 756 MHz LTE FDD B17 704 716 734 746 MHz LTE FDD B18 815 830 860 875 MHz LTE FDD B19 830 845 875 890 MHz LTE FDD B20 832 862 791 821 MHz LTE FDD B21 1447 9 1462 9 1495...

Page 73: ...66 1710 1780 2110 2200 MHz LTE TDD B71 663 698 617 652 MHz 1 LTE FDD B29 B30 and B32 support Rx only 4 1 3 Reference Design of RF Antenna Interfaces A reference design of main and Rx diversity antenna interfaces is shown as below It is recommended to reserve a π type matching circuit for better RF performance and the π type matching components R1 C1 C2 and R2 C3 C4 should be placed as close to the...

Page 74: ... should be controlled to 50 Ω The impedance of the RF traces is usually determined by the trace width W the materials dielectric constant the height from the reference ground to the signal layer H and the spacing between RF traces and grounds S Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance The following are reference designs of microstrip or co...

Page 75: ...nd should be fully connected to ground The distance between the RF pins and the RF connector should be as short as possible and all the right angle traces should be changed to curved ones The recommended trace angle is 135 There should be clearance under the signal pin of the antenna connector or solder joint The reference ground of RF traces should be complete Meanwhile adding some ground vias ar...

Page 76: ...sity antenna Table 30 Antenna Requirements Type Requirements GSM UMTS LTE VSWR 2 Efficiency 30 Max input power 50 W Input impedance 50 Ω Cable insertion loss 1 dB GSM850 EGSM900 WCDMA B5 B8 B19 LTE FDD B5 B8 B9 B12 B13 B17 B18 B19 B20 B26 B28 B29 B71 Cable insertion loss 1 5 dB DCS1800 PCS1900 WCDMA B1 B2 B3 B4B9 LTE FDD B1 B2 B3 B4 B9 B11 B21 B25 B32 B66 LTE TDD B34 B39 Cable insertion loss 2 dB ...

Page 77: ...dware_Design 76 104 4 2 2 Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection it is recommended to use the HFM connector provided by Rosenberger Figure 36 Description of the HFM Connector For more details visit https www rosenbergerap com ...

Page 78: ...aximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table Table 31 Absolute Maximum Ratings Parameter Min Max Unit VBAT_RF VBAT_BB 0 3 6 0 V USB_VBUS 0 3 5 5 V Peak Current of VBAT_BB 0 0 8 A Peak Current of VBAT_RF 0 2 0 A Voltage at Digital Pins 0 3 2 04 V Voltage at ADC0 0 1 91 V Voltage at ADC1 0 1 91 V Voltage at ADC2 0 1 91 V ...

Page 79: ...ith a maximum power and data rate 2 2 Within extended temperature range the module remains fully functional and retains the ability to establish and maintain functions such as voice SMS data transmission and emergency call without any unrecoverable malfunction Radio spectrum and radio network will not be influenced while one or more specifications such as Pout may undergo a reduction in value exce...

Page 80: ...B suspend TBD mA GSM850 DRX 9 USB disconnected 1 760 mA EGSM900 DRX 2 USB disconnected 3 160 mA EGSM900 DRX 5 USB disconnected 2 181 mA EGSM900 DRX 5 USB suspend TBD mA EGSM900 DRX 9 USB disconnected 1 868 mA DCS DRX 2 USB disconnected 3 191 mA DCS DRX 5 USB disconnected 2 157 mA DCS DRX 5 USB suspend TBD mA DCS DRX 9 USB disconnected 3 175 mA PCS DRX 2 USB disconnected 3 156 mA PCS DRX 5 USB disc...

Page 81: ...USB disconnected 3 849 mA LTE TDD PF 64 USB suspend TBD mA LTE TDD PF 128 USB disconnected 4 128 mA LTE TDD PF 256 USB disconnected 2 849 mA Idle state GSM DRX 5 USB connected 29 93 mA GSM DRX 5 USB disconnected 11 99 mA WCDMA PF 64 USB connected 30 93 mA WCDMA PF 64 USB disconnected 15 59 mA LTE FDD PF 64 USB connected 42 91 mA LTE FDD PF 64 USB disconnected 14 813 mA LTE TDD PF 64 USB connected ...

Page 82: ... 3DL 2UL 29 0dBm 362 5 mA PCS1900 2DL 3UL 26 5 dBm 412 4 mA PCS1900 1DL 4UL 25 5 dBm 469 3 mA EDGE data transfer GNSS OFF GSM850 4DL 1UL 27 0dBm 189 4 mA GSM850 3DL 2UL 26 0dBm 298 5 mA GSM850 2DL 3UL 24 0dBm 348 5 mA GSM850 1DL 4UL 23 0dBm 405 3 mA EGSM900 4DL 1UL 27 0dBm 187 3 mA EGSM900 3DL 2UL 26 0dBm 293 mA EGSM900 2DL 3UL 24 0dBm 343 5 mA EGSM900 1DL 4UL 23 0dBm 395 4 mA DCS1800 4DL 1UL 26 0...

Page 83: ...0 dBm 621 63 mA WCDMA B9 HSDPA 23 0 dBm 613 25 mA WCDMA B19 HSDPA 23 0 dBm 618 04 mA WCDMA B1 HSUPA 23 0 dBm 584 23 mA WCDMA B2 HSUPA 23 0 dBm 603 26 mA WCDMA B3 HSUPA 23 0 dBm 602 99 mA WCDMA B4 HSUPA 23 0 dBm 614 63 mA WCDMA B5 HSUPA 23 0 dBm 549 2 mA WCDMA B8 HSUPA 23 0 dBm 575 01 mA WCDMA B9 HSUPA 23 0 dBm 623 55 mA WCDMA B19 HSUPA 23 0 dBm 584 83 mA LTE data transfer GNSS OFF LTE FDD B1 23 0d...

Page 84: ...617 46 mA LTE FDD B21 23 0dBm 665 74 mA LTE FDD B25 23 0dBm 622 94 mA LTE FDD B26 23 0dBm 623 07 mA LTE FDD B28 23 0dBm 597 96 mA LTE FDD B30 23 0dBm TBD mA LTE TDD B34 23 0dBm 289 2 mA LTE TDD B38 23 0dBm 381 17 mA LTE TDD B39 23 0dBm 266 25 mA LTE TDD B40 23 0dBm 477 97 mA LTE TDD B41 23 0dBm 395 46 mA LTE FDD B66 23 0dBm 617 9 mA LTE FDD B71 23 0dBm 590 43 mA GSM voice call GSM850 PCL 5 32 dBm ...

Page 85: ... mA DCS1800 PCL 15 0dBm 132 mA PCS1900 PCL 0 30 dBm 255 6 mA PCS1900 PCL 7 16 0dBm 138 8 mA PCS1900 PCL 15 0dBm 129 8 mA WCDMA voice call WCDMA B1 22 5 dBm 620 63 mA WCDMA B2 22 5 dBm 666 99 mA WCDMA B3 22 5 dBm 623 mA WCDMA B4 22 5 dBm 659 48 mA WCDMA B5 22 5 dBm 612 57 mA WCDMA B8 23 0dBm 615 13 mA WCDMA B9 23 0dBm 671 92 mA WCDMA B19 23 0dBm 598 64 mA Frequency Max Min EGSM900 33 dBm 2 dB 5 dBm...

Page 86: ...B 49 dBm LTE FDD B1 23 dBm 2 dB 39 dBm LTE FDD B2 23 dBm 2 dB 39 dBm LTE FDD B3 23 dBm 2 dB 39 dBm LTE FDD B4 23 dBm 2 dB 39 dBm LTE FDD B5 23 dBm 2 dB 39 dBm LTE FDD B7 23 dBm 2 dB 39 dBm LTE FDD B8 23 dBm 2 dB 39 dBm LTE FDD B9 23 dBm 2 dB 39 dBm LTE FDD B11 23 dBm 2 dB 39 dBm LTE FDD B12 23 dBm 2 dB 39 dBm LTE FDD B13 23 dBm 2 dB 39 dBm LTE FDD B17 23 dBm 2 dB 39 dBm LTE FDD B18 23 dBm 2 dB 39 ...

Page 87: ...y Unit dBm Frequency Receive Sensitivity Typ Primary Diversity SIMO 3GPP SIMO GSM850 110 62 102 EGSM900 109 34 102 DCS1800 109 26 102 PCS1900 108 80 102 LTE FDD B26 23 dBm 2 dB 39 dBm LTE FDD B28 23 dBm 2 dB 39 dBm LTE FDD B29 23 dBm 2 dB 39 dBm LTE FDD B30 23 dBm 2 dB 39 dBm LTE FDD B32 23 dBm 2 dB 39 dBm LTE TDD B34 23 dBm 2 dB 39 dBm LTE TDD B38 23 dBm 2 dB 39 dBm LTE TDD B39 23 dBm 2 dB 39 dBm...

Page 88: ... LTE FDD B3 10 MHz 99 4 99 102 42 93 3 LTE FDD B4 10 MHz 98 4 99 4 101 92 96 3 LTE FDD B5 10 MHz 99 5 99 4 102 62 94 3 LTE FDD B7 10 MHz 96 9 99 101 42 94 3 LTE FDD B8 10 MHz 99 4 99 8 102 82 93 3 LTE FDD B9 10 MHz 99 5 99 1 102 44 95 3 LTE FDD B11 10 MHz 99 5 99 4 102 62 96 3 LTE FDD B12 10 MHz 98 9 100 92 103 12 93 3 LTE FDD B13 10 MHz 99 2 100 62 103 3 93 3 LTE FDD B17 10 MHz 98 8 100 92 103 12...

Page 89: ...32 101 52 94 3 LTE FDD B66 10 MHz 97 7 99 12 101 52 95 8 LTE FDD B71 10 MHz 100 1 98 82 103 12 93 5 5 7 Electrostatic Discharge The module is not protected against electrostatics discharge ESD in general Consequently it is subject to ESD handling precautions that typically apply to ESD sensitive components Proper ESD handling and packaging procedures must be applied throughout the processing handl...

Page 90: ...heat dissipation performance The reference ground of the area where the module is mounted should be complete and add ground vias as many as possible for better heat dissipation Through holes will create better heat dissipation performance Make sure the ground pads of the module and PCB are fully connected According to customers application demands the heatsink can be mounted on the top of the modu...

Page 91: ...rovides reduced performance such as RF output power and data rate When the maximum BB chip temperature reaches or exceeds 118 C the module will disconnect from the network and it will recover to network connected state after the maximum temperature falls below 118 C Therefore the thermal design should be maximally optimized to make sure the maximum BB chip temperature always maintains below 105 C ...

Page 92: ...are_Design 91 104 6 Mechanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimensional tolerances are 0 05 mm unless otherwise specified 6 1 Mechanical Dimensions Figure 39 Module Top and Side Dimensions ...

Page 93: ...odule Series AG525R GL QuecOpen Hardware Design AG525R GL_QuecOpen_Hardware_Design 92 104 Figure 40 Module Bottom Dimensions Top View The package warpage level of the module conforms to JEITA ED 7306 standard NOTE ...

Page 94: ...dware Design AG525R GL_QuecOpen_Hardware_Design 93 104 6 2 Recommended Footprint Figure 41 Recommended Footprint Top View For convenient maintenance of the module please keep about 3 mm between the module and other components on the motherboard NOTE ...

Page 95: ...ware Design AG525R GL_QuecOpen_Hardware_Design 94 104 6 3 Top and Bottom Views Figure 42 Top View of the Module Figure 43 Bottom View of the Module These are renderings of the module For authentic appearance see the module received from Quectel NOTE ...

Page 96: ...is removed the module must be processed in reflow soldering or other high temperature operations within 24 hours Otherwise the module should be stored in an environment where the relative humidity is less than 10 e g a drying cabinet 4 The module should be pre baked to avoid blistering cracks and inner layer separation in PCB under the following circumstances The module is not stored in Recommende...

Page 97: ...Push the squeegee to apply the solder paste on the surface of stencil thus making the paste fill the stencil openings and then penetrate to the PCB The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass To ensure the module soldering quality the thickness of stencil for the module is recommended to be 0 15 0 18 mm For more details see docume...

Page 98: ...tape and reel carriers One reel is 10 56 meters long and contains 220 modules The figures below show the packaging details measured in mm Factor Recommendation Soak Zone Max slope 1 3 C s Soak time between A and B 150 C and 200 C 70 120 s Reflow Zone Max slope 2 3 C s Reflow time D over 220 C 45 70 s Max temperature 238 246 C Cooling down slope 1 5 to 3 C s Reflow Cycle Max reflow cycle 1 ...

Page 99: ...Automotive Module Series AG525R GL QuecOpen Hardware Design AG525R GL_QuecOpen_Hardware_Design 98 104 Figure 45 Tape Specifications Figure 46 Reel Specifications ...

Page 100: ...4 Quectel_RF_Layout_Application_Note RF Layout Application Note 5 Quectel_LTE_Module_Thermal_Design_Guide Thermal Design Guide for Quectel LTE LTE Standard LTE A Automotive modules 6 Quectel_Module_Secondary_SMT_Application_Note Quectel Module Secondary SMT Application Note 7 Quectel_AG525R GL_QuecOpen_Reference_Design AG525R GL QuecOpen Reference Design Table 40 Terms and Abbreviations Abbreviati...

Page 101: ...on Data Optimized FDD Frequency Division Duplex FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GPS Global Positioning System GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packet Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access I O In...

Page 102: ...re Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SIMO Single Input Multiple Output SMS Short Message Service TDD Time Division Duplexing TDMA Time Division Multiple Access TD SCDMA Time Division Synchronous Code Division Multiple Access TX Transmitting Direction UL Uplink UMTS Universal Mobile Telecommunications System UR...

Page 103: ...alue VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VRWM Reserve Stand Off Voltage VSWR Voltage Standing Wave Ratio WCDMA Wideband...

Page 104: ...B GPRS Coding Schemes Table 41 Description of Different Coding Schemes Scheme CS 1 CS 2 CS 3 CS 4 Code Rate 1 2 2 3 3 4 1 USF 3 3 3 3 Pre coded USF 3 6 6 12 Radio Block excl USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 Coded Bits 456 588 676 456 Punctured Bits 0 132 220 Data Rate Kb s 9 05 13 4 15 6 21 4 ...

Page 105: ...en as 3 1 or 2 2 the first number indicates the amount of downlink timeslots while the second number indicates the amount of uplink timeslots The active slots determine the total number of slots the GPRS device can use simultaneously for both uplink and downlink communications The description of different multi slot classes is shown in the following table Table 42 GPRS Multi slot Classes Multislot...

Page 106: ... Hardware Design AG525R GL_QuecOpen_Hardware_Design 105 104 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 ...

Page 107: ...GMSK 13 4 kbps 26 8 kbps 53 6 kbps CS 3 GMSK 15 6 kbps 31 2 kbps 62 4 kbps CS 4 GMSK 21 4 kbps 42 8 kbps 85 6 kbps MCS 1 GMSK C 8 80 kbps 17 60 kbps 35 20 kbps MCS 2 GMSK B 11 2 kbps 22 4 kbps 44 8 kbps MCS 3 GMSK A 14 8 kbps 29 6 kbps 59 2 kbps MCS 4 GMSK C 17 6 kbps 35 2 kbps 70 4 kbps MCS 5 8 PSK B 22 4 kbps 44 8 kbps 89 6 kbps MCS 6 8 PSK A 29 6 kbps 59 2 kbps 118 4 kbps MCS 7 8 PSK B 44 8 kbp...

Search results

Summary of Contents for QuecOpen AG525R-GL

Reviews:

Related manuals for QuecOpen AG525R-GL

Brands by name

Popular brands

Quectel QuecOpen AG525R-GL, Hardware Design

Search results

Summary of Contents for QuecOpen AG525R-GL

Reviews:

Related manuals for QuecOpen AG525R-GL

Brands by name

Popular brands