Wi-Fi&Bluetooth Module Series
FC80A_Hardware_Design 20 / 43
To ensure that the interface design complies with the SDIO 3.0 specification, the following principles are
recommended to be adopted:
⚫
Route the SDIO differential traces in inner-layer of the PCB and the impedance is controlled
at 50 Ω
±10 %;
⚫
SDIO signals need to be keep away from sensitive signals, such as radio frequency, analog signals,
clocks, and DC-DC noise signals;
⚫
The distance between SDIO signals and other signals must be greater than 2 times the trace width,
and the busload capacitance must be less than 15 pF.
⚫
SDIO signal traces need to be treated with equal length (the distance between the traces is less than
1 mm). According to the transmission rate, the trace length has the following requirements:
1) As for SDR104 mode, the recommended bus length is less than 50 mm, the internal trace length
of the module is 11.36 mm.
2) As for other modes, such as DDR50, SDR104, etc., the recommended bus length is less than
150 mm.
3.5. Bluetooth Application Interface
The following figure shows the block diagram of Bluetooth application interface
connection between
FC80A and a host.
FC80A
Host
UART
PCM
BT_EN
UART
PCM
BT_EN
BT_WAKE_HOST
GPIO_1
HOST_WAKE_BT
GPIO_2
Figure 6: Block Diagram of Bluetooth Application Interface Connection
GPIO_1 connected to BT_WAKE_HOST must be interruptible.
NOTE
