Wi-Fi&Bluetooth Module Series
FC80A_Hardware_Design 23 / 43
The following figure shows the PCM interface connection between FC80A and the host.
FC80A
Host
PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
PCM_CLK
PCM_SYNC
PCM_DIN
PCM_DOUT
Figure 8: PCM Interface Connection
3.6. Other Interfaces
3.6.1. WLAN_SLP_CLK
The 32.768 kHz sleep clock is used in low power modes, such as power saving mode and sleep mode. It
serves as a timer to determine when to wake up FC80A to receive signals in various power saving
schemes, and to maintain basic logic operations when the module is in sleep mode.
Table 13: Pin Definition of WLAN_SLP_CLK Interface
Pin Name
Pin No.
I/O
Description
Comment
WLAN_SLP_CLK 31
DI
External 32.768 kHz low power
clock input
3.6.2. SDIO_VSEL
SDIO voltage domain can be selected through SDIO_VSEL. The following table shows the pin definition
of SDIO_VSEL.
Table 14: Pin Definition of SDIO_VSEL
Pin Name
Pin No.
I/O
Description
Comment
SDIO_VSEL
24
DI
SDIO voltage select
pull down: 3.3 V
pull up: 1.8 V
1.8 V or 3.3 V power domain.
Pull up to VDDIO internally through a
200 k
Ω resistor, high level by default.
