Quectel EG25-G, Hardware Design

Page: 8 / 103

LTE Module Series
EG25-G Hardware Design
EG25-G_Hardware_Design 7 / 100
Figure Index
FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 15
FIGURE 2: PIN ASSIGNMENT (TOP VIEW)..................................................................................................... 17
FIGURE 3: SLEEP MODE APPLICATION VIA UART ....................................................................................... 30
FIGURE 4: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP .................................................... 31
FIGURE 5: SLEEP MODE APPLICATION WITH RI ......................................................................................... 32
FIGURE 6: SLEEP MODE APPLICATION WITHOUT SUSPENSION FUNCTION .......................................... 32
FIGURE 7: POWER SUPPLY LIMITS DURING BURST TRANSMISSION ...................................................... 34
FIGURE 8: STAR STRUCTURE OF THE POWER SUPPLY............................................................................ 35
FIGURE 9: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 35
FIGURE 10: TURN ON THE MODULE BY USING DRIVING CIRCUIT ........................................................... 36
FIGURE 11: TURN ON THE MODULE BY USING KEYSTROKE .................................................................... 37
FIGURE 12: POWER-ON SCENARIO OF MODULE ....................................................................................... 37
FIGURE 13: POWER-OFF SCENARIO OF MODULE ...................................................................................... 38
FIGURE 14: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 39
FIGURE 15: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 40
FIGURE 16: TIMING OF RESETTING MODULE ............................................................................................. 40
FIGURE 17: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR
...................................................................................................................................................................
41
FIGURE 18: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR . 42
FIGURE 19: REFERENCE CIRCUIT OF USB APPLICATION ......................................................................... 43
FIGURE 20: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 46
FIGURE 21: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 46
FIGURE 22: PRIMARY MODE TIMING ............................................................................................................ 47
FIGURE 23: AUXILIARY MODE TIMING .......................................................................................................... 48
FIGURE 24: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC .................................... 49
FIGURE 25: REFERENCE CIRCUIT OF SD CARD ......................................................................................... 50
FIGURE 26: REFERENCE CIRCUIT OF WIRELESS CONNECTIVITY INTERFACES WITH FC20 MODULE
...................................................................................................................................................................
53
FIGURE 27: SIMPLIFIED BLOCK DIAGRAM FOR ETHERNET APPLICATION ............................................. 55
FIGURE 28: REFERENCE CIRCUIT OF SGMII INTERFACE WITH PHY AR8033 APPLICATION................. 56
FIGURE 29: REFERENCE CIRCUIT OF THE NETWORK INDICATOR .......................................................... 58
FIGURE 30: REFERENCE CIRCUITS OF STATUS ......................................................................................... 59
FIGURE 31: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 60
FIGURE 32: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................. 65
FIGURE 33: MICROSTRIP DESIGN ON A 2-LAYER PCB ............................................................................... 66
FIGURE 34: COPLANAR WAVEGUIDE DESIGN ON A 2-LAYER PCB ........................................................... 66
FIGURE 35: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND)
...................................................................................................................................................................
66
FIGURE 36: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND)
...................................................................................................................................................................
67
FIGURE 37: REFERENCE CIRCUIT OF GNSS ANTENNA ............................................................................. 68