LTE Module Series
EG25-G Hardware Design
EG25-G_Hardware_Design 45 / 100
Table 11: Pin Definition of Main UART Interface
Pin Name
Pin No.
I/O
Description
Comment
RI
62
DO
Ring indicator
1.8V power domain
DCD
63
DO
Data carrier detection
CTS
64
DO
Clear to send
RTS
65
DI
Request to send
DTR
66
DI
Data terminal ready,
sleep mode control
TXD
67
DO
Transmit data
RXD
68
DI
Receive data
Table 12: Pin Definition of Debug UART Interface
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
12
DO
Transmit data
1.8V power domain
DBG_RXD
11
DI
Receive data
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
Parameter
Min.
Max.
Unit
V
IL
-
0.3
0.6
V
V
IH
1.2
2.0
V
V
OL
0
0.45
V
V
OH
1.35
1.8
V
The module provides 1.8V UART interface. A level translator should be used if customers’ application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by
Texas Instruments
is
recommended. The following figure shows a reference design.
