LTE Module Series
EG25-G Hardware Design
EG25-G_Hardware_Design 56 / 100
The following figure shows a reference design of SGMII interface with PHY AR8033 application.
SGMII_MDATA
EPHY_INT_N
MDIO
RSTN
MDC
R1
R2
10K
VDD_EXT
Module
AR8033
1.5K
USIM2_VDD
EPHY_RST_N
INT
SGMII_MCLK
C1
C2
C3
C4
SGMII_TX_M
SGMII_TX_P
SGMII_RX_P
SGMII_RX_M
SIP
SIN
SOP
SON
Close to Module
Close to AR8033
Control
SGMII Data
0.1uF
0.1uF
0.1uF
0.1uF
USIM2_VDD
USIM2_VDD
Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability in customers’ applications, please follow the criteria
below in the Ethernet PHY circuit design:
Keep SGMII data and control signals away from other sensitive circuits/signals such as RF circuits,
analog signals, etc., as well as noisy signals such as clock signals, DCDC signals, etc.
Keep the maximum trace length less than 10-inch and keep skew on the differential pairs less than
20mil.
The differential impedance of SGMII data trace is 100Ω±10%, and the reference ground of the area
should be complete.
Make sure the trace spacing between SGMII RX and TX is at least 3 times of the trace width, and the
same to the adjacent signal traces.
3.16.
ADC Interfaces
The module provides two analog-to-digital
converter (ADC) interfaces.
AT+QADC=0
command can be
used to read the voltage value on ADC0 pin.
AT+QADC=1
command can be used to read the voltage
value on ADC1 pin. For more details about these AT commands, please refer to
document [2]
.
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
