Pulsar TCF-10B, System Manual, Page: 170 / 249

proportional to the Vdc at I11 pins 2 and 15. The
clock pulse, determined by I11 (R93 and C29) is
approximately 100 Hz. Unlike the classical power
supply pulse-width modulator, many pulses can
occur between clock pulses because the internal
flip-flop is not used. The optical isolator (I-14) has
an isolation voltage of 2,500 Vdc and a transistor
breakdown of 400 Vdc. I-14, Q2 and associated
components form a 100
µ A current source that
pulses “ON/OFF” through I-14, producing a
variable current for the CLI. Temperature
compensation for the thermal characteristics of I-
14 is provided by RT-1, R116, and R117. You can
use the External CLI Full Scale Adjust poten-
tiometer (R110) to adjust the External CLI Meter
reading to +10 dB, with a 20 kHz input of 3.162
Vp-p. This meter will operate with 10 to 350 Vdc
between pins A/C-12 and A/C-14.
Level Comparator (I5b) determines whether the
input level is below the Receiver MARGIN, set by
resistor R40. I5b turns “ON” low-level LED (D2).
The signal is inverted by Level Comparator (I5c),
which operates low-level signal relay (K1).
15.2.1 Digital Discriminator
The 2 Vp-p signal from (TP1) Buffer Amplifier
(I1a) is applied to Hysteresis Limiter (I3),
converting the 2 Vp-p sign wave to 15 Vp-p
square wave (see Schematic, Figure 15-3). The
20 kHz, 15 Vp-p square wave is applied to two
mono-stable multi-vibrators (I4a, I4b); with I4b
producing 10
µ
sec pulses from the rising edge of
the 15 Vp-p square wave, and I4a producing
10
µ
sec pulses from the falling edge of the
15 Vp-p square wave. The two 10
µ
sec wide pulse
trains are combined in NOR gate (I6a), producing
a 40 kHz square wave train, which is compared
against the output of a programmable divider (I9).
If the frequency from I9 is higher than the 40 kHz
pulse train, the divider number is increased; if the
I9 frequency is lower than the pulse train, the
divider number is decreased. The circuit (I7a, pin
12) monitors the increase/decrease control line. A
square wave is produced (at I12) in which the
frequency and duty cycle are proportional to the
40 kHz pulse train, and the divided reference
frequency (1 MHz). The output of the frequency
pulse train and variable duty cycle is filtered by a
third order Low-Pass Filter (I5d and associated
components).
The output of the Low-Pass Filter is applied to
three window comparators, formed from:
• I8a + I8b (center frequency)
• I8c + I8d (high frequency)
• I10a + I10b (low frequency) and associated
components
The outputs of the Window Comparators (WC)
are buffered by QN1 (a, b, c) and QN2 (d). The
center-frequency WC produces a +15 Vdc output
for f
C
. The high-frequency WC pr15 Vdc
for f
H
, and the low-frequency WC produces -15
Vdc output for f
L
(at pin A-28).
15.2.2 Signal-to-Noise Monitor
These WC outputs are OR’d together by diodes
(D5, D9 and D12). If the received frequency is not
f
C
, f
H
, or f
L
, it is interpreted as noise. This signal is
applied to I10c and is inverted; it is filtered by a
fast-attack, slow-decay integrator (D15, D16).
The output of this stage is compared (by I10d),
and a noise alarm is produced. I10d turns “ON”
Noise LED (D1).
15.3 CLI & Discriminator
Troubleshooting
Should a fault occur in this module, place the
module on an extender board.
Signal levels (both ac and dc) are shown on the
schematic for an input voltage of -1.0 dBm (562
mVp-p). The TP3 voltages shown in Figure 15-2
are helpful when you are adjusting the discrimi-
nator.
Normal signal tracing with an oscilloscope, and/or
dc voltmeter, will locate most faults. You may test
diodes and other components conventionally with
an ohmmeter.
January 1996 Page 15–3
Chapter 15. CLI & Discriminator Module
15