SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
www.power.com/igbt-driver
Page 20
Gate Boosting
The 1SC0450E2B0 driver supports gate boosting. This feature allows the commutation speed of the
collector-emitter voltage to be accelerated at turn-on after the critical phase of the diode reverse recovery
behavior to reduce the IGBT turn-on losses.
A dedicated external circuit as shown in Fig. 11 is required. Detailed gate-boosting recommendations are not
currently available.
Gate-boosting circuit principle
The “Gate Boosting Logic” according to Fig. 11 has to trigger the boosting function at the appropriate time
during the IGBT turn on transition as illustrated in Fig. 12:
The delay time between GBS and the required boosting time needs to be determined by the “Gate
Boosting Logic” circuit.
The pulse length of the boosting pulse also needs to be determined by the “Gate Boosting Logic”
circuit. It must be limited to a few microseconds.
A turn-on pulse of the gate-boosting power switch Q
1
will be generated. This will lead to an increased turn-
on gate current that will be injected into the IGBT gate over R
gb
.
The boosting charge capability can be increased by adding an external capacitor C
gb
. The minimum value C
gb
of the external capacitor can be calculated according to Eq. 11.
C
gb
[
nF
]
=
Q
gb
[
nC
]
V
GH
[V]+
|
V
GL
[V]
|
-22
C
gb
≥0
Eq. 11
where Q
gb
stands for the required boosting gate charge and has to be determined according to the IGBT
module gate charge requirements. V
GH
and V
GL
are the absolute values of the turn-on and turn-off voltage at
the driver output respectively. Their value can be found in the driver data sheet /3/. Note that Eq. 11
assumes a full discharge of C
gb
during a gate-boosting event (worst case).
The gate-boosting capability is further limited by the minimum time span between two consecutive gate
turn-on commands as well as by the gate-boosting power. The minimum required time T
min
between two
consecutive gate turn-on commands is given by Eq. 12. The gate-boosting efficiency is reduced if Eq. 12 is
not respected.
T
min
[
μs
]
=11∙
(
1+
22+C
gb
[
nF
]
22
)
+T
gb
[μs]
Eq. 12
T
gb
stands for the gate-boosting pulse length (Fig. 12). It is recommended to limit it to 1…5μs.
The maximum gate-boosting power must be within the absolute maximum ratings of the driver data sheet
/3/. Eq. 13 gives a worst case approximation of the real gate-boosting power P
gb
. It is sufficient to design
the gate boosting such that P
gb
is lower than the corresponding absolute maximum rating of the driver data
sheet /3/.
P
gb
[
W
]
=10
-6
∙
(
C
gb
[
nF
]
+22+6.5∙T
gb
[
μs
])
∙
(
V
GH
[
V
] + |
V
GL
[
V
]|)
2
∙f[kHz]
Eq. 13