BIOS Setup Information
ROBO-8713BVG2 User’s Manual
4-10
4.6
Advanced Chipset Features
This section allows user to configure the system based on the specific features of the
Intel 865 GMCH/MCH and ICH5 chipset for ROBO-8713VG2A. This chipset
manages bus speeds and access to system memory resources, such as DRAM (DDR
SDRAM) and the external cache. It also coordinates communications between the
conventional ISA bus and the PCI bus. It must be stated that these items should
never need to be altered. The default settings have been chosen because they
provide the best operating conditions for the system. The only time user might
consider making any changes would be if you discovered that data was being lost
while during system operation.
Phoenix- AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable
[By SPD]
X CAS Latency Time
[2.5]
X Active to Precharge Delay
[7]
X DRAM RAS# to CAS# Delay [3]
X DRAM RAS# Precharge
[3]
Memory Frequency For
[Auto]
System BIOS Cacheable
[Enabled]
Video BIOS Cacheable
[Enabled]
Memory Hole At 15M-16M
[Disabled]
Delay Prior to Thermal
[16 Min]
AGP Aperture Size (MB)
[128]
Init Display First
[PCI Slot]
** On-Chip VGA Setting **
On-Chip VGA
[Enabled]
On-Chip Frame Buffer Size
[8MB]
Boot Display
[Auto]
Onboard LAN Control
[Enabled]
Menu Level
f
↑↓→←
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
This chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered
if data is being lost. Such a scenario might well occur if your system had mixed
speed DRAM chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
