ECM-3410/3410L/3410N
ECM-3410/3410L/3410N User’s Manual
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4.5.5 Chipset Setup
ADVANCED OPTIONS. The parameters in this screen are for system designers, service
personnel, and technically competent users only. Do not reset these values unless you
understand the consequences of your changes.
4.5.5.1 SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. Do not reset this field from the default value specified by the system
designer.
The choice: Auto, 2T, 3T.
4.5.5.2 SDRAM Clock Ratio Div By
This item allows user to set the DRAM timing.
4.5.5.3 16-bit I/O Recovery (CLK)
The I/O recovery mechanism adds bus clock cycles between PCI-originated I/O cycles to
the ISA bus. This delay takes place because the PCI bus is so much faster than the ISA
bus.
The choice: from 1 to 16 CPU clocks.
