User’s Manual
24
ROBO-503/ROBO-503N User’s Manual
3.7.8 TFT Panel Connector (CN3)
Signal
PIN
Signal
VDDSAFE5
2
1
VDDSAFE5
GND
4
3
GND
VDDSAFE3
6
5
VDDSAFE3
GND
8
7
NC
NC
10
9
NC
P3
12
11
P2
P5
14
13
P4
P7
16
15
P6
NC
18
17
NC
P11
20
19
P10
P13
22
21
P12
P15
24
23
P14
NC
26
25
NC
P19
28
27
P18
P21
30
29
P20
P23
32
31
P22
GND
34
33
GND
FLM
36
35
SHFCLK
LP
38
37
M
ENVEE
40
39
ENBKL
3.7.9 Signal Description – TFT Panel Connector (CN3)
P [23:18]
P [15:10]
P [7:2]
Flat panel data output for 9, 12, or 18 bit TFT flat panels. Refer to table below for
configurations for various panel types. The flat panel data and control outputs are all on-
board controlled for secure power-on/off sequencing.
SHFCLK
Shift Clock. Pixel clock for flat panel data.
LP
Latch Pulse. Flat panel equivalent of HSYNC. (horizontal synchronisation)
FLM
First Line Marker. Flat panel equivalent of VSYNC. (vertical synchronisation)
M
Multipurpose signal, function depends on panel type. May be used as AC drive control
signal or as BLANK# or Display Enable signal.
ENBKL
Enable backlight signal. This signal is controlled as a part of the panel power sequencing
ENVEE
Enable VEE. Signal to control the panel power-on/off sequencing. A high level may turn on
the VEE (LCD bias voltage) supply to the panel.
VDDSAFE5
LCD Backlight V5V or +12V* selected by J2 / Pin 2, 4, 6
VDDSAFE3
LCD Driving V5V or 3.3V* selected by J2 / Pin 1, 3, 5
* default