BIOS Setup Information
PEB-7431VL User’s Manual
4-23
4.14
BIOS POST Check Point List
AWARDBIOS provides all IBM standard Power On Self Test (POST) routines as well
as enhanced AWARDBIOS POST routines. The POST routines support CPU
internal diagnostics. The POST checkpoint codes are accessible via the
Manufacturing Test Port (I/O port 80h).
Whenever a recoverable error occurs during the POST, the system BIOS will display
an error message describing the message and explaining the problem in detail so
that the problem can be corrected.
During the POST, the BIOS signals a checkpoint by issuing one code to I/O address
80H. This code can be used to establish how far the BIOS has executed through the
power-on sequence and what test is currently being performed. This is done to
help troubleshoot faulty system board.
If the BIOS detects a terminal error condition, it will halt the POST process and
attempt to display the checkpoint code written to port 80H. If the system hangs
before the BIOS detects the terminal error, the value at port 80H will be the last test
performed. In this case, the terminal error cannot be displayed on the screen. The
following POST checkpoint codes are valid for all AWARDBIOS products with a
core BIOS date of 07/15/95 version 6.27 (Enhanced).
CODE (hex)
DESCRIPTION
CFh
Test CMOS R/W functionality.
C0h
Early chipset initialization:
- Disable shadow RAM
- Disable L2 cache (socket 7 or below)
- Program basic chipset registers
C1h
Detect
memory
- Auto-detection of DRAM size, type and ECC.
- Auto-detection of L2 cache (socket 7 or below)
C3h
Expand compressed BIOS code to DRAM
C5h
Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.
0h1
Expand the Xgroup codes locating in physical address 1000:0
02h
Reserved
03h
Initial Superio_Early_Init switch.
04h
Reserved
05h
1. Blank out screen
2. Clear CMOS error flag
06h
Reserved
07h
1. Clear 8042 interface
2. Initialize 8042 self-test
08h
Test special keyboard controller for Winbond 977 series Super I/O
chips.
