PEX 8680 Quick Start Hardware Design Guide, Version 1.1
20
© 2011 PLX Technology, Inc. All Rights Reserved.
Parallel plane capacitance exists between a PCB’s DC power and ground planes. PCB reference planes
have a small amount of series inductance; therefore, their effective frequency range is much higher than
that of discrete capacitors. Low-valued discrete capacitors can typically be effective for frequencies up to
250 MHz. For frequency components higher than 250 MHz, plane capacitance provides the only effective
means for de-coupling.
illustrates attenuation curves measured for a PCI Express test board.
The plot illustrates the bare board power-to-ground impedance (indicated in black), compared with
the impedance of various power planes after de-coupling capacitors are populated. Notice that as
frequencies surpass 200 MHz, the impedance profile is affected only by the bare-board capacitance. Also
note the impedance holes at 7 MHz. It is suggested that discrete capacitor values be adjusted to
eliminate measured holes.
Power Plane Impedance vs Frequency
0.0001
0.0010
0.0100
0.1000
1.0000
10.0000
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
Frequency - Hz
Z -
ohm
PCB
3.3V
2.5V
1.5V
1.0V
Figure 16. Power Plane Impedance versus Frequency
A power and ground plane separation of 0.254 mm (0.010 in.) results in approximately 100 pF/in
2
, while a
separation of 0.102 mm (0.004 in.) provides approximately 200 pF/in
2
As for discrete capacitors, the footprint and physical size of discrete capacitors have a significant effect
on the frequencies in which the capacitors provide effective de-coupling. To minimize series inductance,
use smaller-packaged ceramic capacitors (
such as
0402 or 0201) for mid-ranged frequency de-coupling
(20 to 250 MHz). Use a mixed selection of capacitor values,
such as
0.1 and 0.01 µF, to lower the
impedance across a wide frequency range.
. Plane capacitors provide other
important benefits,
such as
a low-impedance path for AC return currents, in cases where a given
reference plane has a discontinuity.
Capacitor footprint layout is important in determining the frequencies at which they are effective. Avoid
adding trace segments from the capacitor pads to the vias. These segments add more series inductance,
thereby lowering the discrete capacitor LC resonant frequency. Place the vias tangentially to the
capacitor pads, and if possible, add multiple vias per pad. (Refer to
Right the First Time: A Practical
Handbook on High Speed PCB and System Design,
by Lee Ritchie.) If a plane capacitor is used, the
placement of small discrete capacitors is not critical. Place the capacitors on the solder side of the board,
under the BGA footprint (in the solder ball void area) and directly outside the BGA matrix. If a plane
capacitor is not possible (this is typically the case for 4- and 6-layer boards), place the capacitors as close
to the balls as possible. If a PCB layer stackup is such that plane capacitors are not possible, add power
or ground fill areas on the signal layers, as follows:
