PLX Technology PEX 8680, Hardware Design Manual

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PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved.
17
9 PEX 8680 Configuration Strapping Balls
The PEX 8680 has a total of 47 Strapping balls. Twenty-six of them service different configuration
functions
(STRAP_NT_ENABLE#, STRAP_NT_UPSTRM_PORTSEL[4:0],
STRAP_UPSTRM_PORTSEL[4:0], STRAP_STNx_PORTCFG[1:0] for each of the six Stations, and
STRAP_VS_MODE[2:0]). For the PEX 8680, internal pull-up and pull-down resistors set the default
configuration. External pull-up and pull-down resistors are not required unless the strapping signals are
connected to circuit traces (the internal resistors are relatively weak, and may not be strong enough to
hold the circuit traces to the default input states).
Table 4 lists the names, functions and default values of
the PEX 8680 Configuration Strapping balls.
Table 4. Configuration Strapping Balls
Ball/Signal Name Functions Default
STRAP_FAST_BRINGUP# Factory Test Only. Internal pull-up
STRAP_G1_COMPATIBLE#
When this ball is tied High, the
Data Rate Identifier symbol in the
TS Ordered-Sets always
advertises support for both the
Gen 2 data rate and Autonomous
Change.
When this ball is tied Low, if the
Link training sequence fails during
configuration, the next time the
LTSSM exits the detect state, TS
Ordered-Sets advertise only the
Gen 1 data rate, and no
Autonomous Change support.
Internal pull-up
STRAP_I2C_CFG_EN#
When this ball is tied Low, the I2C
Bus configures the device. The
Links do not start training until I2C
Sets the
Configuration Release
register Initiate Configuration bit.
When this ball is tied High, the
device operates normally.
Internal pull-up
STRAP_SMBUS_EN#
When this ball is tied Low, SMBus
Slave protocol is implemented on
the I2C_SCL0 and I2C_SDA0 2-
wire bus.
When this ball is tied High, I2C
Slave protocol is implemented on
the I2C_SCL0 and I2C_SDA0 2-
wire bus
Internal pull-up
STRAP_NT_P2P_EN#
This input should be pulled Low,
unless the NT PCI-to-PCI bridge
between the internal Virtual PCI
Bus and the NT Port Virtual
Interface must be disabled for
software compatibility to earlier NT
mode switches.
Internal pull-up
STRAP_PLL_BYPASS#
Factory Test Only. When pulled
Low, PLL that generates
internal clock is bypassed.
Internal pull-up
STRAP_PROBE_MODE# Factory Test Only. Internal pull-up
STRAP_SERDES_MODE_EN# Factory Test Only. Internal pull-up
STRAP_RESERVED[1:0]
Factory Test Only. NOTE:
Internal pull-up