PEX 8680 Quick Start Hardware Design Guide, Version 1.1
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© 2011 PLX Technology, Inc. All Rights Reserved.
1.2
Receiver
The Receiver’s role is to recover the differential bitstream coming across the channel from the Transmitter,
and latch it so it can be de-serialized and forwarded to the logical sub-block. The main components of
a Receiver are the receive buffer and the CDR circuit.
The PCI Express receive buffer input threshold is 175 mV for 2.5 GT/s data rate and 120 mV for a
5.0 GT/s data rate. PCI Express Receivers are required to have a DC common mode voltage of 0V.
The receive buffer will provide bits to the CDR circuit to be sampled and forwarded to the de-serializer.
Digital-based CDRs must track the edges of the incoming bits and determine the best time to sample
each bit, which is typically the center of eye (0.5 UI). The CDR base Reference Clock(s) is provided by
the PLL. A CDR must be able to track either a fixed phase offset (common clock system) or small
continuous phase offset (non-common clock system) between the incoming data/clock and the CDR base
clock. Jitter on the base CDR clock and/or the incoming data stream can cause bit sampling errors to
occur.
Although outside of the scope of the PCI Express specification, Receivers may implement some form of
Receiver equalization to help compensate for the low-pass characteristics of the channel. In general,
Receiver equalization only needs to be used on longer channels.
The PEX 8680 provides a programmable receive equalization function. Ports 0, 4, 8, 16, and 20 each
have a set of
Receiver Equalizer
registers, located at offsets 0xBA4h and 0xBA8h, to control a group of
16 SerDes. Each individual SerDes has a 4-bit control word.
describes the Receiver equalization
effects.
Table 1. Receiver Equalization Settings
SerDes N Receiver Equalizer[3:0]
Equalization
0000b
Off
0010b
Low
0110b
Medium
1110b
High
1.3
Reference Clock
The Reference Clock is a key component to a Link that was often overlooked by system designers in first
generation PCI Express systems. The Reference Clock provides a 100-MHz base frequency for the PLL.
The PLL provides a frequency synthesis function, generating the higher speed clocks required to transmit
data at a rate of either 2.5 GT/s or 5.0 GT/s. In designs that implement digital CDRs, the PLL output also
provides the Reference Clocks to the CDR circuit; hence, jitter on the Reference Clock can affect both the
Transmitter and Receiver components.
The PLL has a low-pass, filter-jitter transfer function from its reference input to the high speed output
clocks; therefore, it is important to minimize the low-frequency jitter in the pass band of the PLL.
Low-frequency jitter below the PLL loop bandwidth passes directly to output clocks, which, in turn, drives
the Transmitter and CDR circuits. Jitter at the loop bandwidth is especially critical, given most PLLs have
some amount of gain at the cut-off frequency. High-frequency jitter on the Reference Clock input above
the loop bandwidth is typically attenuated, and is therefore of less concern.
The jitter transfer function of a CDR circuit is modeled as a high-pass filter. Low-frequency jitter, including
Spread-Spectrum Clock (SSC) modulation, is tracked by the CDR circuit, whereas higher-frequency jitter
content causes eye closure at the Receiver. The cut-off frequency of the CDR high-pass function is
usually less than the cut-off frequency of the Transmitter PLL low-pass function. The pass band between
these cut-off frequencies is where Reference Clock jitter causes the most problems.
