PEX 8680 Quick Start Hardware Design Guide, Version 1.1
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© 2011 PLX Technology, Inc. All Rights Reserved.
1.4
Channel
In PCI Express, the channel refers to the board level copper interconnects (including connectors) that lie
between the Transmitter and Receiver balls. The channel is represented as a transmission line, which
can be modeled by a distributed series of Resistance Inductance Conductance Capacitance (RLGC)
circuits. A transmission line behaves like a low-pass filter due to frequency-dependent dielectric and
conductor losses.
In PCI Express, the channel contributes to amplitude loss and deterministic jitter, which is why it is
important to minimize discontinuities,
such as
vias and stubs, to minimize channel effects.
A common issue that presents itself to PCI Express system designers is determining allowable channel
length. This is a question that does not have a simple answer. The best way to determine if a particular
channel length is allowable is to simulate the channel using the HSPICE models for the PEX8680
provided by PLX and available on the product website atPCI Express Base
Specification, Revision 2.0
provides additional details for simulating a channel.
2
PCB Layout and Stackup Considerations
PCB layout is of critical importance for PCI Express systems. Numerous form factor specifications (
PCI
Express Base Specification, Revision 2.0
and
PCI Express Card Electromechanical (CEM) Specification,
Revisions 1.0a and 1.1
) exist for providing important implementation guidelines for a given form factor. It
is important to understand the type of system being designed before starting layout.
For example
, the
PCI
Express Card Electromechanical (CEM) Specification
defines two platforms, referred to as
system boards
and
add-in cards (boards)
. Each platform has its own criteria, in terms of jitter and loss budget, trace
lengths and length matching, and so forth.
2.1
PEX 8680 BGA Routing Escape and De-Coupling Capacitor Placement
The PEX 8680 is in a 35x35 mm
2
Each pair is split between two rows on the package; hence, the pairs start off with a 1-mm (39.4-mil)
offset And small serpentines may be necessary to match the lengths within the pair. When implemented,
make the serpentines as close to the BGA as possible to allow the differential signal to be tightly coupled
as it travels down the channel.
FCBGA package with 1-mm ball pitch. Power and ground pads have
small “dog-bone” nets from the pad to a via which will connect it with an internal power or ground plane.
The PEX 8680 places all Transmitter differential pairs on the outer two rows of balls and Receiver
differential pairs on rows four and five. This means only two signal layers are required in a PCB stackup
to escape the differential pairs from the BGA. All Transmitters can escape on the top layer, whereas the
Receiver pairs can escape on either the bottom layer or some other internal signal layer. The positive and
negative conductors of a pair should be coupled together as quickly as possible, after escaping from the
BGA.
and
demonstrate one means of escaping the differential pairs from a typical PLX PCIe
switch using two routing layers.
The PEX 8680 is a full matrix, 1-mm pitch BGA. Hence, placing de-coupling capacitors underneath the
BGA can be tricky. It is best to use 0201-sized ceramic capacitors under the BGA matrix (bottom layer),
so that the capacitors can be placed as close to the power balls as possible.
typical placement of 0201 de-coupling capacitors underneath the PLX PCIe switch.
